The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock.

Signed-off-by: Chris Zhong zyw@rock-chips.com ---

.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 1753f0c..4d59df3 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -5,6 +5,7 @@ Required properties: - #address-cells: Should be <1>. - #size-cells: Should be <0>. - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". + "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference @@ -13,6 +14,10 @@ Required properties: - ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl.

+Optional properties: +- clocks, clock-names: phandle to the dw-mipi phy clock, name should be + "phy_cfg". + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/media/video-interfaces.txt

The vopb/vopl switch register of rk3399 mipi is different from rk3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init.

Signed-off-by: Chris Zhong zyw@rock-chips.com Signed-off-by: Mark Yao mark.yao@rock-chips.com ---

drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 70 ++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index dedc65b..100da01 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -28,9 +28,17 @@

#define DRIVER_NAME "dw-mipi-dsi"

-#define GRF_SOC_CON6 0x025c -#define DSI0_SEL_VOP_LIT (1 << 6) -#define DSI1_SEL_VOP_LIT (1 << 9) +#define RK3288_GRF_SOC_CON6 0x025c +#define RK3288_DSI0_SEL_VOP_LIT BIT(6) +#define RK3288_DSI1_SEL_VOP_LIT BIT(9) + +#define RK3399_GRF_SOC_CON19 0x6250 +#define RK3399_DSI0_SEL_VOP_LIT BIT(0) +#define RK3399_DSI1_SEL_VOP_LIT BIT(4) + +/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */ +#define RK3399_GRF_SOC_CON22 0x6258 +#define RK3399_GRF_DSI_MODE 0xffff0000

#define DSI_VERSION 0x00 #define DSI_PWR_UP 0x04 @@ -147,7 +155,6 @@ #define LPRX_TO_CNT(p) ((p) & 0xffff)

#define DSI_BTA_TO_CNT 0x8c - #define DSI_LPCLK_CTRL 0x94 #define AUTO_CLKLANE_CTRL BIT(1) #define PHY_TXREQUESTCLKHS BIT(0) @@ -263,6 +270,11 @@ enum { };

struct dw_mipi_dsi_plat_data { + u32 dsi0_en_bit; + u32 dsi1_en_bit; + u32 grf_switch_reg; + u32 grf_dsi0_mode; + u32 grf_dsi0_mode_reg; unsigned int max_data_lanes; enum drm_mode_status (*mode_valid)(struct drm_connector *connector, struct drm_display_mode *mode); @@ -279,6 +291,7 @@ struct dw_mipi_dsi {

struct clk *pllref_clk; struct clk *pclk; + struct clk *phy_cfg_clk;

unsigned int lane_mbps; /* per lane */ u32 channel; @@ -400,6 +413,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)

dsi_write(dsi, DSI_PWR_UP, POWERUP);

+ if (!IS_ERR(dsi->phy_cfg_clk)) { + ret = clk_prepare_enable(dsi->phy_cfg_clk); + if (ret) { + dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n"); + return ret; + } + } + dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE | VCO_RANGE_CON_SEL(vco) | VCO_IN_CAP_CON_LOW | @@ -444,17 +465,19 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US); if (ret < 0) { dev_err(dsi->dev, "failed to wait for phy lock state\n"); - return ret; + goto phy_init_end; }

ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS, val, val & STOP_STATE_CLK_LANE, 1000, PHY_STATUS_TIMEOUT_US); - if (ret < 0) { + if (ret < 0) dev_err(dsi->dev, "failed to wait for phy clk lane stop state\n"); - return ret; - } + +phy_init_end: + if (!IS_ERR(dsi->phy_cfg_clk)) + clk_disable_unprepare(dsi->phy_cfg_clk);

return ret; } @@ -878,6 +901,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder) { struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); + const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata; int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); u32 val;

@@ -886,6 +910,10 @@ static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder) return; }

+ if (pdata->grf_dsi0_mode_reg) + regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, + pdata->grf_dsi0_mode); + dw_mipi_dsi_phy_init(dsi); dw_mipi_dsi_wait_for_two_frames(dsi);

@@ -895,11 +923,11 @@ static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder) clk_disable_unprepare(dsi->pclk);

if (mux) - val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16); + val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16); else - val = DSI0_SEL_VOP_LIT << 16; + val = pdata->dsi0_en_bit << 16;

- regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val); + regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val); dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG"); }

@@ -1075,6 +1103,19 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid( }

static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = { + .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT, + .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT, + .grf_switch_reg = RK3288_GRF_SOC_CON6, + .max_data_lanes = 4, + .mode_valid = rk3288_mipi_dsi_mode_valid, +}; + +static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { + .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT, + .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT, + .grf_switch_reg = RK3399_GRF_SOC_CON19, + .grf_dsi0_mode = RK3399_GRF_DSI_MODE, + .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, .max_data_lanes = 4, .mode_valid = rk3288_mipi_dsi_mode_valid, }; @@ -1083,6 +1124,9 @@ static const struct of_device_id dw_mipi_dsi_dt_ids[] = { { .compatible = "rockchip,rk3288-mipi-dsi", .data = &rk3288_mipi_dsi_drv_data, + }, { + .compatible = "rockchip,rk3399-mipi-dsi", + .data = &rk3399_mipi_dsi_drv_data, }, { /* sentinel */ } }; @@ -1133,6 +1177,10 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, return ret; }

+ dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(dsi->phy_cfg_clk)) + dev_dbg(dev, "have not phy_cfg_clk\n"); + ret = clk_prepare_enable(dsi->pllref_clk); if (ret) { dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);

At the first time of bind, there is no any panel attach in mipi. Add a DRM_CONNECTOR_POLL_HPD porperty to detect the panel status, when panel probe, the dw_mipi_dsi_host_attach would be called, then mipi-dsi will trigger a event to notify the drm framework.

Signed-off-by: Chris Zhong zyw@rock-chips.com ---

drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 41 ++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 15ba796..72d7f48 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -285,6 +285,7 @@ struct dw_mipi_dsi { struct drm_encoder encoder; struct drm_connector connector; struct mipi_dsi_host dsi_host; + struct device_node *panel_node; struct drm_panel *panel; struct device *dev; struct regmap *grf_regmap; @@ -462,7 +463,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ);

- ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS, val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US); if (ret < 0) { @@ -550,11 +550,11 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, dsi->lanes = device->lanes; dsi->channel = device->channel; dsi->format = device->format; - dsi->panel = of_drm_find_panel(device->dev.of_node); - if (dsi->panel) - return drm_panel_attach(dsi->panel, &dsi->connector); + dsi->panel_node = device->dev.of_node; + if (dsi->connector.dev) + drm_helper_hpd_irq_event(dsi->connector.dev);

- return -EINVAL; + return 0; }

static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, @@ -562,7 +562,10 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, { struct dw_mipi_dsi *dsi = host_to_dsi(host);

- drm_panel_detach(dsi->panel); + dsi->panel_node = NULL; + + if (dsi->connector.dev) + drm_helper_hpd_irq_event(dsi->connector.dev);

return 0; } @@ -1022,13 +1025,33 @@ static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = { static enum drm_connector_status dw_mipi_dsi_detect(struct drm_connector *connector, bool force) { - return connector_status_connected; + struct dw_mipi_dsi *dsi = con_to_dsi(connector); + + + if (!dsi->panel) { + dsi->panel = of_drm_find_panel(dsi->panel_node); + if (dsi->panel) + drm_panel_attach(dsi->panel, &dsi->connector); + } else if (!dsi->panel_node) { + struct drm_encoder *encoder; + + encoder = platform_get_drvdata(to_platform_device(dsi->dev)); + dw_mipi_dsi_encoder_disable(encoder); + drm_panel_detach(dsi->panel); + dsi->panel = NULL; + } + + if (dsi->panel) + return connector_status_connected; + + return connector_status_disconnected; }

static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector) { drm_connector_unregister(connector); drm_connector_cleanup(connector); + connector->dev = NULL; }

static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = { @@ -1069,6 +1092,8 @@ static int dw_mipi_dsi_register(struct drm_device *drm, return ret; }

+ connector->polled = DRM_CONNECTOR_POLL_HPD; + drm_connector_helper_add(connector, &dw_mipi_dsi_connector_helper_funcs);

@@ -1225,6 +1250,8 @@ static void dw_mipi_dsi_unbind(struct device *dev, struct device *master, { struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);

+ dw_mipi_dsi_encoder_disable(&dsi->encoder); + mipi_dsi_host_unregister(&dsi->dsi_host); pm_runtime_disable(dev); clk_disable_unprepare(dsi->pllref_clk);

Before phy init, the detection of phy state should be controlled manually. After that, we can switch the detection to hardward, it is automatic. Hence move PHY_TXREQUESTCLKHS setting to the end of phy init.

Signed-off-by: Chris Zhong zyw@rock-chips.com ---

drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 72d7f48..8401185 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -477,6 +477,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dev_err(dsi->dev, "failed to wait for phy clk lane stop state\n");

+ dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); + phy_init_end: if (!IS_ERR(dsi->phy_cfg_clk)) clk_disable_unprepare(dsi->phy_cfg_clk); @@ -714,7 +716,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) | PHY_RSTZ | PHY_SHUTDOWNZ); dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | TX_ESC_CLK_DIVIDSION(7)); - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); }

static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,