The backend needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time.
Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
---
Changes from v1: - Add test on the clk_set_rate_exclusive return value --- drivers/gpu/drm/sun4i/sun4i_backend.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index 4e29f4fe4a05..072ea113e6be 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -856,6 +856,13 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, ret = PTR_ERR(backend->mod_clk); goto err_disable_bus_clk; } + + ret = clk_set_rate_exclusive(backend->mod_clk, 300000000); + if (ret) { + dev_err(dev, "Couldn't set the module clock frequency\n"); + goto err_disable_bus_clk; + } + clk_prepare_enable(backend->mod_clk);
backend->ram_clk = devm_clk_get(dev, "ram"); @@ -932,6 +939,7 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, err_disable_ram_clk: clk_disable_unprepare(backend->ram_clk); err_disable_mod_clk: + clk_rate_exclusive_put(backend->mod_clk); clk_disable_unprepare(backend->mod_clk); err_disable_bus_clk: clk_disable_unprepare(backend->bus_clk); @@ -952,6 +960,7 @@ static void sun4i_backend_unbind(struct device *dev, struct device *master, sun4i_backend_free_sat(dev);
clk_disable_unprepare(backend->ram_clk); + clk_rate_exclusive_put(backend->mod_clk); clk_disable_unprepare(backend->mod_clk); clk_disable_unprepare(backend->bus_clk); reset_control_assert(backend->reset);
The DRC needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time.
Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
---
Changes from v1: - Add test on the clk_set_rate_exclusive return value --- drivers/gpu/drm/sun4i/sun6i_drc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c index f7ab72244796..4fbe9a6b5182 100644 --- a/drivers/gpu/drm/sun4i/sun6i_drc.c +++ b/drivers/gpu/drm/sun4i/sun6i_drc.c @@ -56,6 +56,13 @@ static int sun6i_drc_bind(struct device *dev, struct device *master, ret = PTR_ERR(drc->mod_clk); goto err_disable_bus_clk; } + + ret = clk_set_rate_exclusive(drc->mod_clk, 300000000); + if (ret) { + dev_err(dev, "Couldn't set the module clock frequency\n"); + goto err_disable_bus_clk; + } + clk_prepare_enable(drc->mod_clk);
return 0; @@ -72,6 +79,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master, { struct sun6i_drc *drc = dev_get_drvdata(dev);
+ clk_rate_exclusive_put(drc->mod_clk); clk_disable_unprepare(drc->mod_clk); clk_disable_unprepare(drc->bus_clk); reset_control_assert(drc->reset);
On Wed, Jan 8, 2020 at 1:00 AM Maxime Ripard maxime@cerno.tech wrote:
The DRC needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time.
Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
Reviewed-by: Chen-Yu Tsai wens@csie.org
On Wed, Jan 08, 2020 at 01:28:34AM +0800, Chen-Yu Tsai wrote:
On Wed, Jan 8, 2020 at 1:00 AM Maxime Ripard maxime@cerno.tech wrote:
The DRC needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time.
Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
Reviewed-by: Chen-Yu Tsai wens@csie.org
APplied both, thanks! Maxime
On Wed, Jan 8, 2020 at 1:00 AM Maxime Ripard maxime@cerno.tech wrote:
The backend needs to run at 300MHz to be functional. This was done so far using assigned-clocks in the device tree, but that is easy to forget, and dosen't provide any other guarantee than the rate is going to be roughly the one requested at probe time.
Therefore it's pretty fragile, so let's just use the exclusive clock API to enforce it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
Reviewed-by: Chen-Yu Tsai wens@csie.org
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