For whatever reason this old series was never merged. Please let's get this done.
For i915 DP this still needs a patch to start using the model size from DPCD.
BR, Jani.
Jani Nikula (6): drm/dsc: use rc_model_size from DSC config for PPS drm/i915/dsc: configure hardware using specified rc_model_size drm/i915/dsc: make rc_model_size an encoder defined value drm/dsc: add helper for calculating rc buffer size from DPCD drm/i915/bios: fill in DSC rc_model_size from VBT drm/i915/dsi: use VBT data for rc_model_size
drivers/gpu/drm/drm_dsc.c | 30 +++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-- include/drm/drm_dsc.h | 1 + 5 files changed, 41 insertions(+), 13 deletions(-)
The PPS is supposed to reflect the DSC config instead of hard coding the rc_model_size. Make it so.
Currently all users of drm_dsc_pps_payload_pack() hard code the size to 8192 also in the DSC config, so this change should have no impact, other than allowing the drivers to use other sizes as needed.
Cc: Alex Deucher alexdeucher@gmail.com Cc: Harry Wentland hwentlan@amd.com Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Reviewed-by: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/drm_dsc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index 4a475d9696ff..09afbc01ea94 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -186,8 +186,7 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
/* PPS 38, 39 */ - pps_payload->rc_model_size = - cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
/* PPS 40 */ pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
The rc_model_size is specified in the DSC config, and the hardware programming should respect that instead of hard coding a value of 8192.
Regardless, the rc_model_size in DSC config is currently hard coded to the same value, so this should have no impact, other than allowing the use of other sizes as needed.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Reviewed-by: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index e2716a67b281..22d08679844f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -741,7 +741,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
/* Populate PICTURE_PARAMETER_SET_9 registers */ pps_val = 0; - pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | + pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) {
Move the intialization of the rc_model_size from the common code into encoder code, allowing different encoders to specify the size according to their needs. Keep using the hard coded value in the encoders for now to make this a non-functional change.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 2 -- 3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index a9439b415603..676e40172fe9 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
vdsc_cfg->convert_rgb = true;
+ /* FIXME: initialize from VBT */ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + ret = intel_dsc_compute_params(encoder, crtc_state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb5e42c3ecd5..b2bc0c8c39c7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, u8 line_buf_depth; int ret;
+ /* + * RC_MODEL_SIZE is currently a constant across all configurations. + * + * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and + * DP_DSC_RC_BUF_SIZE for this. + */ + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + ret = intel_dsc_compute_params(encoder, crtc_state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 22d08679844f..f58cc5700784 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, else if (vdsc_cfg->bits_per_component == 12) vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
- /* RC_MODEL_SIZE is a constant across all configurations */ - vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
On Tue, Dec 08, 2020 at 02:33:52PM +0200, Jani Nikula wrote:
Move the intialization of the rc_model_size from the common code into encoder code, allowing different encoders to specify the size according to their needs. Keep using the hard coded value in the encoders for now to make this a non-functional change.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
So still using the hardcoded value since thats in the DSC C model, Looks good to me
Reviewed-by: Manasi Navare manasi.d.navare@intel.com
Manasi
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 2 -- 3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index a9439b415603..676e40172fe9 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1535,6 +1535,9 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
vdsc_cfg->convert_rgb = true;
- /* FIXME: initialize from VBT */
- vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
- ret = intel_dsc_compute_params(encoder, crtc_state); if (ret) return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cb5e42c3ecd5..b2bc0c8c39c7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2289,6 +2289,14 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, u8 line_buf_depth; int ret;
- /*
* RC_MODEL_SIZE is currently a constant across all configurations.** FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and* DP_DSC_RC_BUF_SIZE for this.*/- vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
- ret = intel_dsc_compute_params(encoder, crtc_state); if (ret) return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 22d08679844f..f58cc5700784 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -454,8 +454,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, else if (vdsc_cfg->bits_per_component == 12) vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
- /* RC_MODEL_SIZE is a constant across all configurations */
- vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
-- 2.20.1
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Add a helper for calculating the rc buffer size from the DCPD offsets DP_DSC_RC_BUF_BLK_SIZE and DP_DSC_RC_BUF_SIZE.
Cc: Alex Deucher alexdeucher@gmail.com Cc: Harry Wentland hwentlan@amd.com Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Reviewed-by: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/drm_dsc.c | 27 +++++++++++++++++++++++++++ include/drm/drm_dsc.h | 1 + 2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index 09afbc01ea94..ff602f7ec65b 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -49,6 +49,33 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header) } EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+/** + * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes + * @rc_buffer_block_size: block size code, according to DPCD offset 62h + * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h + * + * return: + * buffer size in bytes, or 0 on invalid input + */ +int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size) +{ + int size = 1024 * (rc_buffer_size + 1); + + switch (rc_buffer_block_size) { + case DP_DSC_RC_BUF_BLK_SIZE_1: + return 1 * size; + case DP_DSC_RC_BUF_BLK_SIZE_4: + return 4 * size; + case DP_DSC_RC_BUF_BLK_SIZE_16: + return 16 * size; + case DP_DSC_RC_BUF_BLK_SIZE_64: + return 64 * size; + default: + return 0; + } +} +EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size); + /** * drm_dsc_pps_payload_pack() - Populates the DSC PPS * diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index 53c51231b31c..cf43561e60fa 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -603,6 +603,7 @@ struct drm_dsc_pps_infoframe { } __packed;
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); +int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
The VBT fields match the DPCD data, so use the same helper.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_bios.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4cc949b228f2..06c3310446a2 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->dsc.slice_count);
/* - * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the - * implementation specific physical rate buffer size. Currently we use - * the required rate buffer model size calculated in - * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E. - * * The VBT rc_buffer_block_size and rc_buffer_size definitions - * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC - * implementation should also use the DPCD (or perhaps VBT for eDP) - * provided value for the buffer size. + * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. */ + vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, + dsc->rc_buffer_size);
/* FIXME: DSI spec says bpc + 1 for this one */ vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
The VBT fields match the DPCD data, so use the same helper.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
Only for DSI so far right?
In that case looks good
Reviewed-by: Manasi Navare manasi.d.navare@intel.com
Manasi
drivers/gpu/drm/i915/display/intel_bios.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4cc949b228f2..06c3310446a2 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->dsc.slice_count);
/*
* FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the* implementation specific physical rate buffer size. Currently we use* the required rate buffer model size calculated in* drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.*
- The VBT rc_buffer_block_size and rc_buffer_size definitions
* correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC* implementation should also use the DPCD (or perhaps VBT for eDP)* provided value for the buffer size.
* correspond to DP 1.4 DPCD offsets 0x62 and 0x63.*/
vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
dsc->rc_buffer_size);/* FIXME: DSI spec says bpc + 1 for this one */ vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
-- 2.20.1
On Tue, 08 Dec 2020, "Navare, Manasi" manasi.d.navare@intel.com wrote:
On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
The VBT fields match the DPCD data, so use the same helper.
Cc: Manasi Navare manasi.d.navare@intel.com Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
Only for DSI so far right?
Yes. We'll still need a patch to start using the rc_model_size from DPCD for DP.
In that case looks good
Reviewed-by: Manasi Navare manasi.d.navare@intel.com
Thanks for the reviews. Pushed up to and including this one to drm-intel-next. The last patch in the series still to be reviewed.
BR, Jani.
Manasi
drivers/gpu/drm/i915/display/intel_bios.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4cc949b228f2..06c3310446a2 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->dsc.slice_count);
/*
* FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the* implementation specific physical rate buffer size. Currently we use* the required rate buffer model size calculated in* drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.*
- The VBT rc_buffer_block_size and rc_buffer_size definitions
* correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC* implementation should also use the DPCD (or perhaps VBT for eDP)* provided value for the buffer size.
* correspond to DP 1.4 DPCD offsets 0x62 and 0x63.*/
vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
dsc->rc_buffer_size);/* FIXME: DSI spec says bpc + 1 for this one */ vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
-- 2.20.1
Stop overriding the VBT defined value for rc_model_size.
Cc: Vandita Kulkarni vandita.kulkarni@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 676e40172fe9..a9439b415603 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1535,9 +1535,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
vdsc_cfg->convert_rgb = true;
- /* FIXME: initialize from VBT */ - vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; - ret = intel_dsc_compute_params(encoder, crtc_state); if (ret) return ret;
On Tue, 08 Dec 2020, Jani Nikula jani.nikula@intel.com wrote:
For whatever reason this old series was never merged. Please let's get this done.
Daniel, Maarten, may I have an ack to merge patches 1 and 4 via drm-intel?
BR, Jani.
For i915 DP this still needs a patch to start using the model size from DPCD.
BR, Jani.
Jani Nikula (6): drm/dsc: use rc_model_size from DSC config for PPS drm/i915/dsc: configure hardware using specified rc_model_size drm/i915/dsc: make rc_model_size an encoder defined value drm/dsc: add helper for calculating rc buffer size from DPCD drm/i915/bios: fill in DSC rc_model_size from VBT drm/i915/dsi: use VBT data for rc_model_size
drivers/gpu/drm/drm_dsc.c | 30 +++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-- include/drm/drm_dsc.h | 1 + 5 files changed, 41 insertions(+), 13 deletions(-)
On Wed, Dec 09, 2020 at 11:34:44AM +0200, Jani Nikula wrote:
On Tue, 08 Dec 2020, Jani Nikula jani.nikula@intel.com wrote:
For whatever reason this old series was never merged. Please let's get this done.
Daniel, Maarten, may I have an ack to merge patches 1 and 4 via drm-intel?
Ack. -Daniel
BR, Jani.
For i915 DP this still needs a patch to start using the model size from DPCD.
BR, Jani.
Jani Nikula (6): drm/dsc: use rc_model_size from DSC config for PPS drm/i915/dsc: configure hardware using specified rc_model_size drm/i915/dsc: make rc_model_size an encoder defined value drm/dsc: add helper for calculating rc buffer size from DPCD drm/i915/bios: fill in DSC rc_model_size from VBT drm/i915/dsi: use VBT data for rc_model_size
drivers/gpu/drm/drm_dsc.c | 30 +++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_bios.c | 11 +++------ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-- include/drm/drm_dsc.h | 1 + 5 files changed, 41 insertions(+), 13 deletions(-)
-- Jani Nikula, Intel Open Source Graphics Center
dri-devel@lists.freedesktop.org
-
Daniel Vetter -
Jani Nikula -
Navare, Manasi