This addresses all the review comments from the earlier patch series: https://patchwork.freedesktop.org/series/15771/
DP 1.2 compliance testing can be acheived using DPR-120's CTS suite. This compliance unit sends a short pulse to initiate link training and video pattern generation compliance tests and sends a long pulse to initate EDID compliance tests. It also sets the AUTOMATED TEST REQUEST bit in Device IRQ to 1. These patches add support in the kernel to respond to these test requests sent by DPR-120. The test handler has been added for Link training/EDID and Video pattern compliance tests that gets invoked on short/long pulse sent by DPR-120. The test handler for each of the tests reads the corresponding DPCD registers to read the test parameters.
These tests need to be run with the IGT DP compliance automation tool. Link Training Tests (4.3.1.1 - 4.3.2.3): It reads the DPCD registers to get the link rate and lane count requested by test and sends a hotplug uevent for the userspace to redo a modeset in order to train the link at the requested test parameters.
EDID Tests (4.2.2.3 - 4.2.2.6): It reads the EDID set by the DPR-120, if EDID read succeeds, it sets the video mode to PREFERRED and sets the test_active flag. This flag wakes up the IGT compliance tool that then fills the framebuffers and triggers a modeset.
Video Pattern Tests (4.3.3.1): It reads the DPCD registers to set the requested video pattern parameters. It then sets the test active flag that wakes up the IGT tool, userspace reads the video pattern values from corresponding debugfs files and fills the framebuffers and triggers a modeset.
Manasi Navare (5): drm/i915: Move all the DP compliance data to a separate struct drm/i915: Add support for DP link training compliance drm/i915: Fixes to support DP Compliance EDID tests drm: Add definitions for DP compliance Video pattern tests drm/i915: Add support for DP Video pattern compliance tests
drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++-- drivers/gpu/drm/i915/intel_dp.c | 153 +++++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_dp_mst.c | 7 +- drivers/gpu/drm/i915/intel_drv.h | 19 ++++- include/drm/drm_dp_helper.h | 58 ++++++++++++++ 5 files changed, 232 insertions(+), 27 deletions(-)
This patch does not change anything functionally, just cleans up the DP compliance related variables and stores them all together in a separate struct intel_dp_compliance. There is another struct intel_dp_compliance_data to store all the test data. This makes it easy to reset the compliance variables through a memset instead of individual resetting.
Signed-off-by: Manasi Navare manasi.d.navare@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@ffwl.ch --- drivers/gpu/drm/i915/i915_debugfs.c | 13 ++++++++----- drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 14 +++++++++++--- 3 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a746130..b2ff532 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4463,9 +4463,9 @@ static ssize_t i915_displayport_test_active_write(struct file *file, * testing code, only accept an actual value of 1 here */ if (val == 1) - intel_dp->compliance_test_active = 1; + intel_dp->compliance.test_active = 1; else - intel_dp->compliance_test_active = 0; + intel_dp->compliance.test_active = 0; } } out: @@ -4492,7 +4492,7 @@ static int i915_displayport_test_active_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder); - if (intel_dp->compliance_test_active) + if (intel_dp->compliance.test_active) seq_puts(m, "1"); else seq_puts(m, "0"); @@ -4536,7 +4536,10 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder); - seq_printf(m, "%lx", intel_dp->compliance_test_data); + if (intel_dp->compliance.test_type == + DP_TEST_LINK_EDID_READ) + seq_printf(m, "%lx", + intel_dp->compliance.test_data.edid); } else seq_puts(m, "0"); } @@ -4575,7 +4578,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder); - seq_printf(m, "%02lx", intel_dp->compliance_test_type); + seq_printf(m, "%02lx", intel_dp->compliance.test_type); } else seq_puts(m, "0"); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index db75bb9..c1e107c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3834,7 +3834,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count); - intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; + intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; } else { struct edid *block = intel_connector->detect_edid;
@@ -3850,11 +3850,11 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; - intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; + intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD; }
/* Set test active flag here so userspace doesn't interrupt things */ - intel_dp->compliance_test_active = 1; + intel_dp->compliance.test_active = 1;
return test_result; } @@ -3880,22 +3880,22 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) switch (rxdata) { case DP_TEST_LINK_TRAINING: DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); - intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; + intel_dp->compliance.test_type = DP_TEST_LINK_TRAINING; response = intel_dp_autotest_link_training(intel_dp); break; case DP_TEST_LINK_VIDEO_PATTERN: DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); - intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; + intel_dp->compliance.test_type = DP_TEST_LINK_VIDEO_PATTERN; response = intel_dp_autotest_video_pattern(intel_dp); break; case DP_TEST_LINK_EDID_READ: DRM_DEBUG_KMS("EDID test requested\n"); - intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; + intel_dp->compliance.test_type = DP_TEST_LINK_EDID_READ; response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); - intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; + intel_dp->compliance.test_type = DP_TEST_LINK_PHY_TEST_PATTERN; response = intel_dp_autotest_phy_pattern(intel_dp); break; default: @@ -4019,7 +4019,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) return;
/* if link training is requested we should perform it always */ - if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || + if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) || (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", intel_encoder->base.name); @@ -4053,9 +4053,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) * Clearing compliance test variables to allow capturing * of values for next automated test request. */ - intel_dp->compliance_test_active = 0; - intel_dp->compliance_test_type = 0; - intel_dp->compliance_test_data = 0; + memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
/* * Now read the DPCD to see if it's actually running @@ -4372,9 +4370,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, status = connector_status_disconnected;
if (status == connector_status_disconnected) { - intel_dp->compliance_test_active = 0; - intel_dp->compliance_test_type = 0; - intel_dp->compliance_test_data = 0; + memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
if (intel_dp->is_mst) { DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8f4ddca..f8c7046 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -884,6 +884,16 @@ struct intel_dp_desc { u8 sw_minor_rev; } __packed;
+struct intel_dp_compliance_data { + unsigned long edid; +}; + +struct intel_dp_compliance { + unsigned long test_type; + struct intel_dp_compliance_data test_data; + bool test_active; +}; + struct intel_dp { i915_reg_t output_reg; i915_reg_t aux_ch_ctl_reg; @@ -959,9 +969,7 @@ struct intel_dp { void (*prepare_link_retrain)(struct intel_dp *intel_dp);
/* Displayport compliance testing */ - unsigned long compliance_test_type; - unsigned long compliance_test_data; - bool compliance_test_active; + struct intel_dp_compliance compliance; };
struct intel_lspcon {
On Fri, 09 Dec 2016, Manasi Navare manasi.d.navare@intel.com wrote:
This patch does not change anything functionally, just cleans up the DP compliance related variables and stores them all together in a separate struct intel_dp_compliance. There is another struct intel_dp_compliance_data to store all the test data. This makes it easy to reset the compliance variables through a memset instead of individual resetting.
Signed-off-by: Manasi Navare manasi.d.navare@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@ffwl.ch
drivers/gpu/drm/i915/i915_debugfs.c | 13 ++++++++----- drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 14 +++++++++++--- 3 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a746130..b2ff532 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4463,9 +4463,9 @@ static ssize_t i915_displayport_test_active_write(struct file *file, * testing code, only accept an actual value of 1 here */ if (val == 1)
intel_dp->compliance_test_active = 1;
intel_dp->compliance.test_active = 1; else
intel_dp->compliance_test_active = 0;
intel_dp->compliance.test_active = 0;out: @@ -4492,7 +4492,7 @@ static int i915_displayport_test_active_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder);
if (intel_dp->compliance_test_active)
if (intel_dp->compliance.test_active) seq_puts(m, "1"); else seq_puts(m, "0");@@ -4536,7 +4536,10 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder);
seq_printf(m, "%lx", intel_dp->compliance_test_data);
if (intel_dp->compliance.test_type ==DP_TEST_LINK_EDID_READ)seq_printf(m, "%lx",intel_dp->compliance.test_data.edid);
The commit message says no functional changes, but this is one. Probably better to make this change separately.
With that fixed,
Reviewed-by: Jani Nikula jani.nikula@intel.com
} else seq_puts(m, "0");} @@ -4575,7 +4578,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data) if (connector->status == connector_status_connected && connector->encoder != NULL) { intel_dp = enc_to_intel_dp(connector->encoder);
seq_printf(m, "%02lx", intel_dp->compliance_test_type);
seq_printf(m, "%02lx", intel_dp->compliance.test_type);diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index db75bb9..c1e107c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3834,7 +3834,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count);
intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;@@ -3850,11 +3850,11 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD;}
/* Set test active flag here so userspace doesn't interrupt things */
- intel_dp->compliance_test_active = 1;
intel_dp->compliance.test_active = 1;
return test_result;
} @@ -3880,22 +3880,22 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) switch (rxdata) { case DP_TEST_LINK_TRAINING: DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
intel_dp->compliance.test_type = DP_TEST_LINK_TRAINING;
intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
intel_dp->compliance.test_type = DP_TEST_LINK_VIDEO_PATTERN;
intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
intel_dp->compliance.test_type = DP_TEST_LINK_EDID_READ;
intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
intel_dp->compliance.test_type = DP_TEST_LINK_PHY_TEST_PATTERN;@@ -4019,7 +4019,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) return;
/* if link training is requested we should perform it always */
- if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
- if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) || (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", intel_encoder->base.name);
@@ -4053,9 +4053,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) * Clearing compliance test variables to allow capturing * of values for next automated test request. */
- intel_dp->compliance_test_active = 0;
- intel_dp->compliance_test_type = 0;
- intel_dp->compliance_test_data = 0;
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
/*
- Now read the DPCD to see if it's actually running
@@ -4372,9 +4370,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, status = connector_status_disconnected;
if (status == connector_status_disconnected) {
intel_dp->compliance_test_active = 0;intel_dp->compliance_test_type = 0;intel_dp->compliance_test_data = 0;
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));if (intel_dp->is_mst) { DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8f4ddca..f8c7046 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -884,6 +884,16 @@ struct intel_dp_desc { u8 sw_minor_rev; } __packed;
+struct intel_dp_compliance_data {
- unsigned long edid;
+};
+struct intel_dp_compliance {
- unsigned long test_type;
- struct intel_dp_compliance_data test_data;
- bool test_active;
+};
struct intel_dp { i915_reg_t output_reg; i915_reg_t aux_ch_ctl_reg; @@ -959,9 +969,7 @@ struct intel_dp { void (*prepare_link_retrain)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
- unsigned long compliance_test_type;
- unsigned long compliance_test_data;
- bool compliance_test_active;
- struct intel_dp_compliance compliance;
};
struct intel_lspcon {
This patch adds support to handle automated DP compliance link training test requests. This patch has been tested with Unigraf DPR-120 DP Compliance device for testing Link Training Compliance. After we get a short pulse Compliance test request, test request values are read and hotplug uevent is sent in order to trigger another modeset during which the pipe is configured and link is retrained and enabled for link parameters requested by the test.
v2: * Validate the test lane count before using it in intel_dp_compute_config (Jani Nikula) Signed-off-by: Manasi Navare manasi.d.navare@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 62 +++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c1e107c..bbf8cdc 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -278,6 +278,21 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp, common_rates); }
+static int intel_dp_link_rate_index(struct intel_dp *intel_dp, + int *common_rates, int link_rate) +{ + int common_len; + int index; + + common_len = intel_dp_common_rates(intel_dp, common_rates); + for (index = 0; index < common_len; index++) { + if (link_rate == common_rates[common_len - index - 1]) + return common_len - index - 1; + } + + return -1; +} + static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -1544,6 +1559,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, /* Conveniently, the link BW constants become indices with a shift...*/ int min_clock = 0; int max_clock; + int link_rate_index; int bpp, mode_rate; int link_avail, link_clock; int common_rates[DP_MAX_SUPPORTED_RATES] = {}; @@ -1585,6 +1601,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) return false;
+ /* Use values requested by Compliance Test Request */ + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { + link_rate_index = intel_dp_link_rate_index(intel_dp, + common_rates, + drm_dp_bw_code_to_link_rate(intel_dp->compliance.test_link_rate)); + if (link_rate_index >= 0) + min_clock = max_clock = link_rate_index; + if (min_lane_count <= intel_dp->compliance.test_lane_count + && intel_dp->compliance.test_lane_count >= max_lane_count) + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + } DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %d pixel clock %iKHz\n", max_lane_count, common_rates[max_clock], @@ -1632,6 +1659,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, } } } + }
return false; @@ -3804,6 +3832,27 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_ACK; + int status = 0; + /* (DP CTS 1.2) + * 4.3.1.11 + */ + /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, + &intel_dp->compliance.test_lane_count); + + if (status <= 0) { + DRM_DEBUG_KMS("Lane count read failed\n"); + return 0; + } + intel_dp->compliance.test_lane_count &= DP_MAX_LANE_COUNT_MASK; + + status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, + &intel_dp->compliance.test_link_rate); + if (status <= 0) { + DRM_DEBUG_KMS("Link Rate read failed\n"); + return 0; + } + return test_result; }
@@ -4018,9 +4067,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) if (WARN_ON_ONCE(!intel_dp->lane_count)) return;
- /* if link training is requested we should perform it always */ - if ((intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) || - (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { + /* Retrain if Channel EQ or CR not ok */ + if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", intel_encoder->base.name);
@@ -4045,6 +4093,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) intel_dp_short_pulse(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; u8 sink_irq_vector = 0; u8 old_sink_count = intel_dp->sink_count; bool ret; @@ -4078,7 +4127,7 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) sink_irq_vector);
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) - DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); + intel_dp_handle_test_request(intel_dp); if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); } @@ -4086,6 +4135,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); intel_dp_check_link_status(intel_dp); drm_modeset_unlock(&dev->mode_config.connection_mutex); + if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { + DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); + /* Send a Hotplug Uevent to userspace to start modeset */ + drm_kms_helper_hotplug_event(intel_encoder->base.dev); + }
return true; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7046..dbd580a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -892,6 +892,8 @@ struct intel_dp_compliance { unsigned long test_type; struct intel_dp_compliance_data test_data; bool test_active; + u8 test_link_rate; + u8 test_lane_count; };
struct intel_dp {
This patch addresses a few issues from the original patch for DP Compliance EDID test support submitted by Todd Previtetodd.previte@gmail.com
Video Mode requested in the EDID test handler for the EDID Read test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
Signed-off-by: Manasi Navare manasi.d.navare@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bbf8cdc..fb6f9e5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3864,7 +3864,7 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) { - uint8_t test_result = DP_TEST_NAK; + uint8_t test_result = DP_TEST_ACK; struct intel_connector *intel_connector = intel_dp->attached_connector; struct drm_connector *connector = &intel_connector->base;
@@ -3899,7 +3899,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Failed to write EDID checksum\n");
test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; - intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_STANDARD; + intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; }
/* Set test active flag here so userspace doesn't interrupt things */
v2: * Add all the other DP Complianec TEST register defs (Jani Nikula) Cc: dri-devel@lists.freedesktop.org Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com Signed-off-by: Manasi Navare manasi.d.navare@intel.com --- include/drm/drm_dp_helper.h | 58 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 55bbeb0..3525d95 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -416,6 +416,64 @@ #define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221 +# define DP_NO_TEST_PATTERN (0x0) +# define DP_COLOR_RAMP (0x1) +# define DP_BLACK_AND_WHITE_VERTICAL_LINES (0x2) +# define DP_COLOR_SQUARE (0x3) + +#define DP_TEST_H_TOTAL_HI 0x222 +#define DP_TEST_H_TOTAl_LO 0x223 + +#define DP_TEST_V_TOTAL_HI 0x224 +#define DP_TEST_V_TOTAl_LO 0x225 + +#define DP_TEST_H_START_HI 0x226 +#define DP_TEST_H_START_LO 0x227 + +#define DP_TEST_V_START_HI 0x228 +#define DP_TEST_V_START_LO 0x229 + +#define DP_TEST_HSYNC_HI 0x22A +#define DP_TEST_HSYNC_LO 0x22B + +#define DP_TEST_VSYNC_HI 0x22C +#define DP_TEST_VSYNC_LO 0x22D + +#define DP_TEST_H_WIDTH_HI 0x22E +#define DP_TESt_H_WIDTH_LO 0x22F + +#define DP_TEST_V_HEIGHT_HI 0x230 +#define DP_TEST_V_HEIGHT_LO 0x231 + +#define DP_TEST_MISC_LO 0x232 +# define DP_TEST_SYNC_CLOCK_MASK (1 << 0) +# define DP_CLOCK_ASYNC (0x0) +# define DP_CLOCK_SYNC (0x1) +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1) +# define DP_TEST_COLOR_FORMAT_SHIFT 1 +# define DP_COLOR_FORMAT_RGB (0x0) +# define DP_COLOR_FORMAT_YCbCr422 (0x1) +# define DP_COLOR_FORMAT_YCbCr444 (0x2) +# define DP_TEST_DYNAMIC_RANGE_MASK (1 << 3) +# define DP_TEST_DYNAMIC_RANGE_SHIFT 3 +# define DP_VESA_RANGE (0x0) +# define DP_CEA_RANGE (0x1) +# define DP_TEST_BIT_DEPTH_MASK (7 << 5) +# define DP_TEST_BIT_DEPTH_SHIFT 5 +# define DP_TEST_BIT_DEPTH_6 (0x0) +# define DP_TEST_BIT_DEPTH_8 (0x1) +# define DP_TEST_BIT_DEPTH_10 (0x2) +# define DP_TEST_BIT_DEPTH_12 (0x3) +# define DP_TEST_BIT_DEPTH_16 (0x4) +#define DP_TEST_MISC_HI 0x233 +# define DP_TEST_REFRESH_DENOMINATOR_MASK (1 << 0) +# define REFRESH_DENOMINATOR_1 (0x0) +# define REFRESH_DENOMINATOR_1_001 (0x1) +# define DP_TEST_INTERLACED_MASK (1 << 1) +# define DP_NON_INTERLACED (0x0) +# define DP_INTERLACED (0x1) + +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
#define DP_TEST_CRC_R_CR 0x240 #define DP_TEST_CRC_G_Y 0x242
The intel_dp_autotest_video_pattern() function gets invoked through the compliance test handler on a HPD short pulse if the test type is set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers reads to read the requested test pattern, video pattern resolution, frame rate and bits per color value. The results of this analysis are handed off to userspace so that the userspace app can set the video pattern mode appropriately for the test result/response. When the test is requested with specific BPC value, we read the BPC value from the DPCD register. If this BPC value in intel_dp structure has a non-zero value and we're on a display port connector, then we use the value to calculate the bpp for the pipe.
The compliance_test_active flag is set at the end of the individual test handling functions. This is so that the kernel-side operations can be completed without the risk of interruption from the userspace app that is polling on that flag.
v2: * Updated the DPCD Register reads based on proper defines in header (Jani Nikula) * Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani Nikula) Signed-off-by: Manasi Navare manasi.d.navare@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Daniel Vetter daniel.vetter@intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++ drivers/gpu/drm/i915/intel_dp.c | 67 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++- drivers/gpu/drm/i915/intel_drv.h | 3 ++ 4 files changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b2ff532..e87a46d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4540,6 +4540,15 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data) DP_TEST_LINK_EDID_READ) seq_printf(m, "%lx", intel_dp->compliance.test_data.edid); + else if (intel_dp->compliance.test_type == + DP_TEST_LINK_VIDEO_PATTERN) { + seq_printf(m, "hdisplay: %d\n", + intel_dp->compliance.test_data.hdisplay); + seq_printf(m, "vdisplay: %d\n", + intel_dp->compliance.test_data.vdisplay); + seq_printf(m, "bpc: %u\n", + intel_dp->compliance.test_data.bpc); + } } else seq_puts(m, "0"); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fb6f9e5..5e91bfc 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -28,8 +28,10 @@ #include <linux/i2c.h> #include <linux/slab.h> #include <linux/export.h> +#include <linux/types.h> #include <linux/notifier.h> #include <linux/reboot.h> +#include <asm/byteorder.h> #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> @@ -1539,6 +1541,12 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, if (bpc > 0) bpp = min(bpp, 3*bpc);
+ /* For DP Compliance we override the computed bpp for the pipe */ + if (intel_dp->compliance.test_data.bpc != 0) { + pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; + DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", + pipe_config->pipe_bpp); + } return bpp; }
@@ -3859,6 +3867,65 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_NAK; + uint8_t test_pattern; + uint16_t test_misc; + __be16 h_width, v_height; + int status = 0; + + /* Read the TEST_PATTERN (DP CTS 3.1.5) */ + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN, + &test_pattern, 1); + if (status <= 0) { + DRM_DEBUG_KMS("Test pattern read failed\n"); + return 0; + } + if (test_pattern != DP_COLOR_RAMP) + return test_result; + intel_dp->compliance.test_data.video_pattern = test_pattern; + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, + &h_width, 2); + if (status <= 0) { + DRM_DEBUG_KMS("H Width read failed\n"); + return 0; + } + intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, + &v_height, 2); + if (status <= 0) { + DRM_DEBUG_KMS("V Height read failed\n"); + return 0; + } + intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC_LO, + &test_misc, 1); + if (status <= 0) { + DRM_DEBUG_KMS("TEST MISC read failed\n"); + return 0; + } + if (((test_misc & DP_TEST_COLOR_FORMAT_MASK) >> DP_TEST_COLOR_FORMAT_SHIFT) != + DP_COLOR_FORMAT_RGB) + return test_result; + if (((test_misc & DP_TEST_DYNAMIC_RANGE_MASK) >> DP_TEST_DYNAMIC_RANGE_SHIFT) != + DP_VESA_RANGE) + return test_result; + switch ((test_misc & DP_TEST_BIT_DEPTH_MASK) >> DP_TEST_BIT_DEPTH_SHIFT) { + case DP_TEST_BIT_DEPTH_6: + intel_dp->compliance.test_data.bpc = 6; + break; + case DP_TEST_BIT_DEPTH_8: + intel_dp->compliance.test_data.bpc = 8; + break; + default: + return test_result; + } + /* Set test active flag here so userspace doesn't interrupt things */ + intel_dp->compliance.test_active = 1; + + test_result = DP_TEST_ACK; + return test_result; }
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 205fe47..29a9af1 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -47,6 +47,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = false; bpp = 24; + if (intel_dp->compliance.test_data.bpc) { + bpp = intel_dp->compliance.test_data.bpc * 3; + DRM_DEBUG_KMS("Setting pipe bpp to %d\n", + bpp); + } /* * for MST we always configure max link bw - the spec doesn't * seem to suggest we should do otherwise. @@ -55,7 +60,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = 24; + pipe_config->pipe_bpp = bpp; pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
state = pipe_config->base.state; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index dbd580a..fb02e06 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -886,6 +886,9 @@ struct intel_dp_desc {
struct intel_dp_compliance_data { unsigned long edid; + uint8_t video_pattern; + uint16_t hdisplay, vdisplay; + uint8_t bpc; };
struct intel_dp_compliance {
dri-devel@lists.freedesktop.org
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Jani Nikula -
Manasi Navare