The VESA specification suggests a 2.2 ms timeout on DDC channels. Use exactly that (as the i915 driver does) instead of hard-coding a jiffy count.
Signed-off-by: Jean Delvare jdelvare@suse.de Reviewed-by: Keith Packard keithp@keithp.com Cc: Dave Airlie airlied@gmail.com Cc: Alex Deucher alexdeucher@gmail.com --- Already sent on: 2011-10-21.
drivers/gpu/drm/radeon/radeon_i2c.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) --- linux-3.3-rc1.orig/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:37:51.722069517 +0100 +++ linux-3.3-rc1/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:39:26.996070929 +0100 @@ -925,9 +925,7 @@ struct radeon_i2c_chan *radeon_i2c_creat i2c->algo.bit.getsda = get_data; i2c->algo.bit.getscl = get_clock; i2c->algo.bit.udelay = 10; - /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always - * make this, 2 jiffies is a lot more reliable */ - i2c->algo.bit.timeout = 2; + i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ i2c->algo.bit.data = i2c; ret = i2c_bit_add_bus(&i2c->adapter); if (ret) {
On Sat, Jan 28, 2012 at 5:08 AM, Jean Delvare jdelvare@suse.de wrote:
The VESA specification suggests a 2.2 ms timeout on DDC channels. Use exactly that (as the i915 driver does) instead of hard-coding a jiffy count.
Signed-off-by: Jean Delvare jdelvare@suse.de Reviewed-by: Keith Packard keithp@keithp.com Cc: Dave Airlie airlied@gmail.com Cc: Alex Deucher alexdeucher@gmail.com
Reviewed-by: Alex Deucher alexdeucher@gmail.com
Already sent on: 2011-10-21.
drivers/gpu/drm/radeon/radeon_i2c.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) --- linux-3.3-rc1.orig/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:37:51.722069517 +0100 +++ linux-3.3-rc1/drivers/gpu/drm/radeon/radeon_i2c.c 2012-01-28 10:39:26.996070929 +0100 @@ -925,9 +925,7 @@ struct radeon_i2c_chan *radeon_i2c_creat i2c->algo.bit.getsda = get_data; i2c->algo.bit.getscl = get_clock; i2c->algo.bit.udelay = 10;
- /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
- * make this, 2 jiffies is a lot more reliable */
- i2c->algo.bit.timeout = 2;
- i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */
i2c->algo.bit.data = i2c; ret = i2c_bit_add_bus(&i2c->adapter); if (ret) {
-- Jean Delvare Suse L3
On Sat, 28 Jan 2012 11:08:58 +0100, Jean Delvare jdelvare@suse.de wrote:
The VESA specification suggests a 2.2 ms timeout on DDC channels. Use exactly that (as the i915 driver does) instead of hard-coding a jiffy count.
The Vesa spec seems to say 2ms; at least according to the DDC/CI spec paragraph 6.6. usecs_to_jiffies rounds the value it gets up, so we should never get an interval less than 2ms if we pass 2000us to it.
Hi Keith,
On Sunday 29 January 2012 02:34:05 am Keith Packard wrote:
On Sat, 28 Jan 2012 11:08:58 +0100, Jean Delvare jdelvare@suse.de wrote:
The VESA specification suggests a 2.2 ms timeout on DDC channels. Use exactly that (as the i915 driver does) instead of hard-coding a jiffy count.
The Vesa spec seems to say 2ms; at least according to the DDC/CI spec paragraph 6.6.
To be honest, I did not read it, I don't even think it is publicly available, is it? I did naively trust the comment in radeon_i2c.c: "vesa says 2.2 ms is enough". Not sure where this value came from if you claim the spec says 2 ms. Jerome, you wrote this comment in the first place, want to comment on that?
The Intel drivers are using 2.2 ms too, since November 2008 (added to i915 driver by Jesse Barnes.) Maybe this all originates from X11 driver code?
usecs_to_jiffies rounds the value it gets up, so we should never get an interval less than 2ms if we pass 2000us to it.
Technically I agree, all we need to agree on is the value, 2000 us or 2200 us. I don't mind either way, I am not aware of specific complaints about the current code, I was just trying to clean things up, as hard- coding jiffy counts is bad and having different timeouts in the various drivers makes little sense IMHO.
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