Hi Marcel,

On Tue, 2021-03-23 at 00:23 +0000, Marcel Ziswiler wrote:

On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:

...

This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner. The RGB pixels with padding low per component are transmitted on a 30-bit input bus(10-bit per component) from a display controller or a 36-bit output bus(12-bit per component) to a pixel link.

Reviewed-by: Robert Foss robert.foss-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Reviewed-by: Laurent Pinchart laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org Signed-off-by: Liu Ying victor.liu-3arQi8VN3Tc@public.gmane.org

---

v5->v6:

• Add Laurent's R-b tag.

v4->v5:

• Add Robert's R-b tag.

v3->v4:

• No change.

v2->v3:

• No change.

v1->v2:

• No change.

include/uapi/linux/media-bus-format.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 0dfc11e..ec3323d 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,7 +34,7 @@

#define MEDIA_BUS_FMT_FIXED 0x0001

-/* RGB - next is 0x101e */ +/* RGB - next is 0x1022 */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -59,9 +59,13 @@ #define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e +#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 +#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020 +#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021 #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a

I haven't figured out what exactly the idea of this strange ordering of things is about? Could you enlighten me?

The existing comment in this header file mentions 'The bus formats are grouped by type, bus_width, bits per component, samples per pixel and order of subsamples. Numerical values are sorted using generic numerical sort order (8 thus comes before 10).'

So, the way I read the ordering is that fomarts are first grouped as 'type', like 'RGB', 'YUV' and 'Bayer', then sorted by 'bus_width', like '2x8', '1x30' and '1x36', then sorted by 'bits per component', like 'RGB666', 'RGB888' and 'RGB121212'.

It looks like 'samples per pixel' and 'order of subsamples' are 'YUV' type relevant.

HTH, Liu Ying

Hi Marcel,

On Tue, 2021-03-23 at 00:34 +0000, Marcel Ziswiler wrote:

On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:

...

This patch adds bindings for i.MX8qm/qxp pixel combiner.

Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Liu Ying victor.liu@nxp.com

---

v5->v6:

• No change.

v4->v5:

• No change.

v3->v4:

• No change.

v2->v3:

• Add Rob's R-b tag.

v1->v2:

• Use graph schema. (Laurent)
• Use enum instead of oneOf + const for the reg property of pixel combiner channels. (Rob)

.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml new file mode 100644 index 00000000..50bae21 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....

+title: Freescale i.MX8qm/qxp Pixel Combiner

+maintainers:

• • Liu Ying victor.liu@nxp.com

+description: |

• The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
• single display controller and manipulates the two streams to support a number
• of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
• either one screen, two screens, or virtual screens. The pixel combiner is
• also responsible for generating some of the control signals for the pixel link
• output channel.

+properties:

• compatible:
• enum:

•  - fsl,imx8qm-pixel-combiner
  

•  - fsl,imx8qxp-pixel-combiner
  

• "#address-cells":
• const: 1
• "#size-cells":
• const: 0
• reg:
• maxItems: 1
• clocks:
• maxItems: 1
• clock-names:
• const: apb
• power-domains:
• maxItems: 1

+patternProperties:

• "^channel@[0-1]$":
• type: object
• description: Represents a display stream of pixel combiner.
• properties:

•  "#address-cells":
  

•    const: 1
  

•  "#size-cells":
  

•    const: 0
  

•  reg:
  

•    description: The display stream index.
  

•    enum: [ 0, 1 ]
  

•  port@0:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: Input endpoint of the display stream.
  

•  port@1:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: Output endpoint of the display stream.
  

• required:

•  - "#address-cells"
  

•  - "#size-cells"
  

•  - reg
  

•  - port@0
  

•  - port@1
  

• additionalProperties: false

+required:

• • compatible
• • "#address-cells"
• • "#size-cells"
• • reg
• • clocks
• • clock-names
• • power-domains

+additionalProperties: false

+examples:

• • |
• #include <dt-bindings/clock/imx8-lpcg.h>
• #include <dt-bindings/firmware/imx/rsrc.h>
• pixel-combiner@56020000 {

•    compatible = "fsl,imx8qxp-pixel-combiner";
  

•    #address-cells = <1>;
  

•    #size-cells = <0>;
  

•    reg = <0x56020000 0x10000>;
  

•    clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
  

•    clock-names = "apb";
  

•    power-domains = <&pd IMX_SC_R_DC_0>;
  

•    channel@0 {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        reg = <0>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
  

•                remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
  

While I acknowledge this just being an example you seem to call these as follows elsewhere:

Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml

dc0_dpu_disp0_dc0_pixel_combiner_ch0 pixel_combiner0_ch0_dpu0_disp0

Hmm, just like you said, this is just an example. And, it passes 'make dt_binding_check'. Phandle 'pixel_combiner0_ch0_dpu0_disp0' is used in the example of DPU[1]. It equals to phandle 'dc0_pixel_combiner_ch0_dc0_dpu_disp0' in this pixel combiner example.

We'll eventually wire all those endpoints up to form display pipes in real DT files with correct phandles. So, if no objections, I'll keep those phandles as-is in the examples.

[1] https://www.spinics.net/lists/arm-kernel/msg878544.html

Regards, Liu Ying

Or am I just missing something?

...

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
  

•                remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
  

•            };
  

•        };
  

•    };
  

•    channel@1 {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        reg = <1>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
  

•                remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
  

ditto

...

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
  

•                remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
  

do.

...

•            };
  

•        };
  

•    };
  

• };

Hi Marcel,

On Tue, 2021-03-23 at 00:38 +0000, Marcel Ziswiler wrote:

On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:

...

This patch adds bindings for i.MX8qm/qxp display pixel link.

Reviewed-by: Rob Herring robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Signed-off-by: Liu Ying victor.liu-3arQi8VN3Tc@public.gmane.org

---

v5->v6:

• No change.

v4->v5:

• No change.

v3->v4:

• No change.

v2->v3:

• Add Rob's R-b tag.

v1->v2:

• Use graph schema. (Laurent)
• Require all four pixel link output ports. (Laurent)
• Mention pixel link is accessed via SCU firmware. (Rob)

.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..3af67cc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.... +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree....

+title: Freescale i.MX8qm/qxp Display Pixel Link

+maintainers:

• • Liu Ying victor.liu-3arQi8VN3Tc@public.gmane.org

+description: |

• The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
• asynchronous linkage between pixel sources(display controller or
• camera module) and pixel consumers(imaging or displays).
• It consists of two distinct functions, a pixel transfer function and a
• control interface. Multiple pixel channels can exist per one control channel.
• This binding documentation is only for pixel links whose pixel sources are
• display controllers.
• The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
• firmware.

+properties:

• compatible:
• enum:

•  - fsl,imx8qm-dc-pixel-link
  

•  - fsl,imx8qxp-dc-pixel-link
  

• ports:
• $ref: /schemas/graph.yaml#/properties/ports
• properties:

•  port@0:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: The pixel link input port node from upstream video source.
  

• patternProperties:

•  "^port@[1-4]$":
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: The pixel link output port node to downstream bridge.
  

• required:

•  - port@0
  

•  - port@1
  

•  - port@2
  

•  - port@3
  

•  - port@4
  

+required:

• • compatible
• • ports

+additionalProperties: false

+examples:

• • |
• dc0-pixel-link0 {

•    compatible = "fsl,imx8qxp-dc-pixel-link";
  

•    ports {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        /* from dc0 pixel combiner channel0 */
  

•        port@0 {
  

•            reg = <0>;
  

•            dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
  

•                remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
  

•            };
  

•        };
  

•        /* to PXL2DPIs in MIPI/LVDS combo subsystems */
  

•        port@1 {
  

•            #address-cells = <1>;
  

•            #size-cells = <0>;
  

•            reg = <1>;
  

•            dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
  

•                reg = <0>;
  

•                remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
  

•            };
  

•            dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
  

•                reg = <1>;
  

•                remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
  

Those also seem absent from other examples.

Patch 8/14 adds dt-binding for PXL2DPI. An example for the PXL2DPI instance in 'mipi_lvds_0' subsystem is provided there. It doesn't make too much sense to provide examples for both 'mipi_lvds_0' subsystem and 'mipi_lvds_1' subsystem, IMHO. I think it's common that people usually provide an example for one hardware instance.

Regards, Liu Ying

...

•            };
  

•        };
  

•        /* unused */
  

•        port@2 {
  

•            reg = <2>;
  

•        };
  

•        /* unused */
  

•        port@3 {
  

•            reg = <3>;
  

•        };
  

•        /* to imaging subsystem */
  

•        port@4 {
  

•            reg = <4>;
  

•        };
  

•    };
  

• };

Hey Liu,

checkpatch --strict had some complaints, with those fixed feel free to add my r-b.

Reviewed-by: Robert Foss robert.foss@linaro.org

On Wed, 17 Mar 2021 at 04:57, Liu Ying victor.liu@nxp.com wrote:

This patch adds a drm bridge driver for i.MX8qxp pixel link to display pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit data output and the DSI controller’s MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap the pixel color codings between those modules. The PXL2DPI is purely combinatorial.

Signed-off-by: Liu Ying victor.liu@nxp.com

v5->v6:

• No change.

v4->v5:

• No change.

v3->v4:

• Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with the PXL2DPI instance instead of using alias ID. (Rob)

v2->v3:

• Call syscon_node_to_regmap() to get regmap instead of syscon_regmap_lookup_by_phandle().

v1->v2:

• Drop unnecessary port availability check.

drivers/gpu/drm/bridge/imx/Kconfig | 8 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 +++++++++++++++++++++++++++ 3 files changed, 494 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 4d1f027..1ea1ce7 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -14,3 +14,11 @@ config DRM_IMX8QXP_PIXEL_LINK help Choose this to enable display pixel link found in Freescale i.MX8qm/qxp processors.

+config DRM_IMX8QXP_PIXEL_LINK_TO_DPI

•   tristate "Freescale i.MX8QXP pixel link to display pixel interface"
  

•   depends on OF
  

•   select DRM_KMS_HELPER
  

•   help
  

•     Choose this to enable pixel link to display pixel interface(PXL2DPI)
  

•     found in Freescale i.MX8qxp processor.
  

diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index c15469f..e74dd64 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c new file mode 100644 index 00000000..6696855 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: GPL-2.0+

+/*

• • Copyright 2020 NXP
• */

+#include <linux/firmware/imx/svc/misc.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h>

+#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+#include <dt-bindings/firmware/imx/rsrc.h>

+#define PXL2DPI_CTRL 0x40 +#define CFG1_16BIT 0x0 +#define CFG2_16BIT 0x1 +#define CFG3_16BIT 0x2 +#define CFG1_18BIT 0x3 +#define CFG2_18BIT 0x4 +#define CFG_24BIT 0x5

+#define DRIVER_NAME "imx8qxp-pxl2dpi"

+struct imx8qxp_pxl2dpi {

•   struct regmap *regmap;
  

•   struct drm_bridge bridge;
  

•   struct drm_bridge *next_bridge;
  

•   struct drm_bridge *companion;
  

•   struct device *dev;
  

•   struct imx_sc_ipc *ipc_handle;
  

•   u32 sc_resource;
  

•   u32 in_bus_format;
  

•   u32 out_bus_format;
  

•   u32 pl_sel;
  

+};

+#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge)

+static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge,

•                                    enum drm_bridge_attach_flags flags)
  

+{

•   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
  

•   if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "do not support creating a drm_connector\n");
  

•           return -EINVAL;
  

•   }
  

•   if (!bridge->encoder) {
  

•           DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
  

•           return -ENODEV;
  

•   }
  

•   return drm_bridge_attach(bridge->encoder,
  

•                            p2d->next_bridge, bridge,
  

•                            DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  

+}

+static int +imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge,

•                               struct drm_bridge_state *bridge_state,
  

•                               struct drm_crtc_state *crtc_state,
  

•                               struct drm_connector_state *conn_state)
  

+{

•   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
  

•   p2d->in_bus_format = bridge_state->input_bus_cfg.format;
  

•   p2d->out_bus_format = bridge_state->output_bus_cfg.format;
  

•   return 0;
  

+}

+static void +imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge,

•                           const struct drm_display_mode *mode,
  

•                           const struct drm_display_mode *adjusted_mode)
  

+{

•   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
  

•   struct imx8qxp_pxl2dpi *companion_p2d;
  

•   int ret;
  

•   ret = pm_runtime_get_sync(p2d->dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "failed to get runtime PM sync: %d\n", ret);
  

•   ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->sc_resource,
  

•                                 IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel);
  

•   if (ret)
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "failed to set pixel link selection(%u): %d\n",
  

•                                                   p2d->pl_sel, ret);
  

•   switch (p2d->out_bus_format) {
  

•   case MEDIA_BUS_FMT_RGB888_1X24:
  

•           regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT);
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
  

•           regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT);
  

•           break;
  

•   default:
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "unsupported output bus format 0x%08x\n",
  

•                                                   p2d->out_bus_format);
  

•   }
  

•   if (p2d->companion) {
  

•           companion_p2d = bridge_to_p2d(p2d->companion);
  

•           companion_p2d->in_bus_format = p2d->in_bus_format;
  

•           companion_p2d->out_bus_format = p2d->out_bus_format;
  

•           p2d->companion->funcs->mode_set(p2d->companion, mode,
  

•                                                   adjusted_mode);
  

•   }
  

+}

+static void +imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge,

•                                 struct drm_bridge_state *old_bridge_state)
  

+{

•   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
  

•   int ret;
  

•   ret = pm_runtime_put(p2d->dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret);
  

•   if (p2d->companion)
  

•           p2d->companion->funcs->atomic_disable(p2d->companion,
  

•                                                   old_bridge_state);
  

+}

+static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = {

•   MEDIA_BUS_FMT_RGB888_1X24,
  

•   MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
  

+};

+static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt) +{

•   int i;
  

•   for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) {
  

•           if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt)
  

•                   return true;
  

•   }
  

•   return false;
  

+}

+static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   u32 output_fmt,
  

•                                   unsigned int *num_input_fmts)
  

+{

CHECK: Alignment should match open parenthesis #217: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:164: +imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state,

•   u32 *input_fmts;
  

•   if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt))
  

•           return NULL;
  

•   *num_input_fmts = 1;
  

•   input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
  

•   if (!input_fmts)
  

•           return NULL;
  

•   switch (output_fmt) {
  

•   case MEDIA_BUS_FMT_RGB888_1X24:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
  

•           break;
  

•   default:
  

•           kfree(input_fmts);
  

•           input_fmts = NULL;
  

•           break;
  

•   }
  

•   return input_fmts;
  

+}

+static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   unsigned int *num_output_fmts)
  

CHECK: Alignment should match open parenthesis #252: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:199: +imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state,

+{

•   *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts);
  

•   return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts,
  

•                   sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL);
  

+}

+static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = {

•   .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  

•   .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
  

•   .atomic_reset           = drm_atomic_helper_bridge_reset,
  

•   .attach                 = imx8qxp_pxl2dpi_bridge_attach,
  

•   .atomic_check           = imx8qxp_pxl2dpi_bridge_atomic_check,
  

•   .mode_set               = imx8qxp_pxl2dpi_bridge_mode_set,
  

•   .atomic_disable         = imx8qxp_pxl2dpi_bridge_atomic_disable,
  

•   .atomic_get_input_bus_fmts =
  

•                   imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts,
  

•   .atomic_get_output_bus_fmts =
  

•                   imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts,
  

+};

+static struct device_node * +imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d,

•                                      u32 port_id)
  

+{

•   struct device_node *port, *ep;
  

•   int ep_cnt;
  

•   port = of_graph_get_port_by_id(p2d->dev->of_node, port_id);
  

•   if (!port) {
  

•           DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id);
  

•           return ERR_PTR(-ENODEV);
  

•   }
  

•   ep_cnt = of_get_available_child_count(port);
  

•   if (ep_cnt == 0) {
  

•           DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n",
  

•                                                           port_id);
  

CHECK: Alignment should match open parenthesis #292: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:239: + DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n", + port_id);

•           ep = ERR_PTR(-ENODEV);
  

•           goto out;
  

•   } else if (ep_cnt > 1) {
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                   "invalid available endpoints of port@%u\n", port_id);
  

CHECK: Alignment should match open parenthesis #297: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:244: + DRM_DEV_ERROR(p2d->dev, + "invalid available endpoints of port@%u\n", port_id);

•           ep = ERR_PTR(-ENOTSUPP);
  

WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP #298: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:245: + ep = ERR_PTR(-ENOTSUPP);

Maybe the more correct return value would be -EINVAL.

•           goto out;
  

•   }
  

•   ep = of_get_next_available_child(port, NULL);
  

•   if (!ep) {
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "failed to get available endpoint of port@%u\n",
  

•                                                           port_id);
  

This ^^ indentation also looks funny.

•           ep = ERR_PTR(-ENODEV);
  

•           goto out;
  

•   }
  

+out:

•   of_node_put(port);
  

•   return ep;
  

+}

+static struct drm_bridge * +imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d) +{

•   struct device_node *ep, *remote;
  

•   struct drm_bridge *next_bridge;
  

•   int ret;
  

•   ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1);
  

•   if (IS_ERR(ep)) {
  

•           ret = PTR_ERR(ep);
  

•           return ERR_PTR(ret);
  

•   }
  

•   remote = of_graph_get_remote_port_parent(ep);
  

•   if (!remote || !of_device_is_available(remote)) {
  

•           DRM_DEV_ERROR(p2d->dev, "no available remote\n");
  

•           next_bridge = ERR_PTR(-ENODEV);
  

•           goto out;
  

•   } else if (!of_device_is_available(remote->parent)) {
  

•           DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n");
  

•           next_bridge = ERR_PTR(-ENODEV);
  

•           goto out;
  

•   }
  

•   next_bridge = of_drm_find_bridge(remote);
  

•   if (!next_bridge) {
  

•           next_bridge = ERR_PTR(-EPROBE_DEFER);
  

•           goto out;
  

•   }
  

+out:

•   of_node_put(remote);
  

•   of_node_put(ep);
  

•   return next_bridge;
  

+}

+static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d) +{

•   struct device_node *ep;
  

•   struct of_endpoint endpoint;
  

•   int ret;
  

•   ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0);
  

•   if (IS_ERR(ep))
  

•           return PTR_ERR(ep);
  

•   ret = of_graph_parse_endpoint(ep, &endpoint);
  

•   if (ret) {
  

•           DRM_DEV_ERROR(p2d->dev,
  

•                         "failed to parse endpoint of port@0: %d\n", ret);
  

•           goto out;
  

•   }
  

•   p2d->pl_sel = endpoint.id;
  

+out:

•   of_node_put(ep);
  

•   return ret;
  

+}

+static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d) +{

•   struct imx8qxp_pxl2dpi *companion_p2d;
  

•   struct device *dev = p2d->dev;
  

•   struct device_node *companion;
  

•   struct device_node *port1, *port2;
  

•   const struct of_device_id *match;
  

•   int dual_link;
  

•   int ret = 0;
  

•   /* Locate the companion PXL2DPI for dual-link operation, if any. */
  

•   companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0);
  

•   if (!companion)
  

•           return 0;
  

•   if (!of_device_is_available(companion)) {
  

•           DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n");
  

•           ret = -ENODEV;
  

•           goto out;
  

•   }
  

•   /*
  

•    * Sanity check: the companion bridge must have the same compatible
  

•    * string.
  

•    */
  

•   match = of_match_device(dev->driver->of_match_table, dev);
  

•   if (!of_device_is_compatible(companion, match->compatible)) {
  

•           DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n");
  

•           ret = -ENXIO;
  

•           goto out;
  

•   }
  

•   p2d->companion = of_drm_find_bridge(companion);
  

•   if (!p2d->companion) {
  

•           ret = -EPROBE_DEFER;
  

•           DRM_DEV_DEBUG_DRIVER(p2d->dev,
  

•                           "failed to find companion bridge: %d\n", ret);
  

CHECK: Alignment should match open parenthesis #411: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:358: + DRM_DEV_DEBUG_DRIVER(p2d->dev, + "failed to find companion bridge: %d\n", ret);

•           goto out;
  

•   }
  

•   companion_p2d = bridge_to_p2d(p2d->companion);
  

•   /*
  

•    * We need to work out if the sink is expecting us to function in
  

•    * dual-link mode.  We do this by looking at the DT port nodes that
  

•    * the next bridges are connected to.  If they are marked as expecting
  

•    * even pixels and odd pixels than we need to use the companion PXL2DPI.
  

•    */
  

•   port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1);
  

•   port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1);
  

•   dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
  

•   of_node_put(port1);
  

•   of_node_put(port2);
  

•   if (dual_link < 0) {
  

•           ret = dual_link;
  

•           DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n",
  

•                                                                   ret);
  

CHECK: Alignment should match open parenthesis #432: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:379: + DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n", + ret);

•           goto out;
  

•   }
  

•   DRM_DEV_DEBUG_DRIVER(dev,
  

•           "dual-link configuration detected (companion bridge %pOF)\n",
  

•                                                           companion);
  

CHECK: Alignment should match open parenthesis #437: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:384: + DRM_DEV_DEBUG_DRIVER(dev, + "dual-link configuration detected (companion bridge %pOF)\n",

+out:

•   of_node_put(companion);
  

•   return ret;
  

+}

+static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev) +{

•   struct imx8qxp_pxl2dpi *p2d;
  

•   struct device *dev = &pdev->dev;
  

•   struct device_node *np = dev->of_node;
  

•   int ret;
  

•   p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
  

•   if (!p2d)
  

•           return -ENOMEM;
  

•   p2d->regmap = syscon_node_to_regmap(np->parent);
  

•   if (IS_ERR(p2d->regmap)) {
  

•           ret = PTR_ERR(p2d->regmap);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
  

•           return ret;
  

•   }
  

•   ret = imx_scu_get_handle(&p2d->ipc_handle);
  

•   if (ret) {
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
  

•                                                                   ret);
  

CHECK: Alignment should match open parenthesis #467: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:414: + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n", + ret);

•           return ret;
  

•   }
  

•   p2d->dev = dev;
  

•   ret = of_property_read_u32(np, "fsl,sc-resource", &p2d->sc_resource);
  

•   if (ret) {
  

•           DRM_DEV_ERROR(dev, "failed to get SC resource %d\n", ret);
  

•           return ret;
  

•   }
  

•   p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d);
  

•   if (IS_ERR(p2d->next_bridge)) {
  

•           ret = PTR_ERR(p2d->next_bridge);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
  

•                                                                   ret);
  

CHECK: Alignment should match open parenthesis #484: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c:431: + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", + ret);

•           return ret;
  

•   }
  

•   ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d);
  

•   if (ret)
  

•           return ret;
  

•   ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d);
  

•   if (ret)
  

•           return ret;
  

•   platform_set_drvdata(pdev, p2d);
  

•   pm_runtime_enable(dev);
  

•   p2d->bridge.driver_private = p2d;
  

•   p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
  

•   p2d->bridge.of_node = np;
  

•   drm_bridge_add(&p2d->bridge);
  

•   return ret;
  

+}

+static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev) +{

•   struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev);
  

•   drm_bridge_remove(&p2d->bridge);
  

•   pm_runtime_disable(&pdev->dev);
  

•   return 0;
  

+}

+static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = {

•   { .compatible = "fsl,imx8qxp-pxl2dpi", },
  

•   { /* sentinel */ }
  

+}; +MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids);

+static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = {

•   .probe  = imx8qxp_pxl2dpi_bridge_probe,
  

•   .remove = imx8qxp_pxl2dpi_bridge_remove,
  

•   .driver = {
  

•           .of_match_table = imx8qxp_pxl2dpi_dt_ids,
  

•           .name = DRIVER_NAME,
  

•   },
  

+}; +module_platform_driver(imx8qxp_pxl2dpi_bridge_driver);

+MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2");

+MODULE_ALIAS("platform:" DRIVER_NAME);

2.7.4

Hey Liu,

checkpatch --strict lists some nit and a warning. With those fixed feel free to add my r-b.

On Wed, 17 Mar 2021 at 04:57, Liu Ying victor.liu@nxp.com wrote:

This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB) which is officially named as pixel mapper. The LDB has two channels. Each of them supports up to 24bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels cannot be used simultaneously, that is to say, the user should pick one of them to use. Two LDB channels from two LDB instances can work together in LDB split mode to support a dual link LVDS display. The channel indexes have to be different. Channel0 outputs odd pixels and channel1 outputs even pixels. This patch supports the LDB single mode and split mode.

Signed-off-by: Liu Ying victor.liu@nxp.com

Note that this patch depends on the patch 'phy: Add LVDS configuration options', which has already been sent with the following series to add Mixel combo PHY found in i.MX8qxp: https://www.spinics.net/lists/arm-kernel/msg879957.html

v5->v6:

• No change.

v4->v5:

• Link with the imx-ldb-helper object. (Robert)
• Correspondingly, rename 'imx8qxp-ldb.c' to 'imx8qxp-ldb-drv.c'.

v3->v4:

• No change.

v2->v3:

• No change.

v1->v2:

• Drop unnecessary DT validation.
• Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to get the input remote endpoint in imx8qxp_ldb_set_di_id().
• Avoid using companion_port OF node after putting it in imx8qxp_ldb_parse_dt_companion().
• Mention i.MX8qxp LDB official name 'pixel mapper' in the bridge driver and Kconfig help message.

drivers/gpu/drm/bridge/imx/Kconfig | 9 + drivers/gpu/drm/bridge/imx/Makefile | 3 + drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 720 +++++++++++++++++++++++++++ 3 files changed, 732 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 1ea1ce7..94f8db4d 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -1,3 +1,12 @@ +config DRM_IMX8QXP_LDB

•   tristate "Freescale i.MX8QXP LVDS display bridge"
  

•   depends on OF
  

•   depends on COMMON_CLK
  

•   select DRM_KMS_HELPER
  

•   help
  

•     Choose this to enable the internal LVDS Display Bridge(LDB) found in
  

•     Freescale i.MX8qxp processor.  Official name of LDB is pixel mapper.
  

config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index e74dd64..96d5d1e 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,3 +1,6 @@ +imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o +obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o

obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c new file mode 100644 index 00000000..d7f59c1 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0+

+/*

• • Copyright 2020 NXP
• */

+#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h>

+#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+#include "imx-ldb-helper.h"

+#define LDB_CH_SEL (1 << 28)

+#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2))

+#define DRIVER_NAME "imx8qxp-ldb"

+struct imx8qxp_ldb_channel {

•   struct ldb_channel base;
  

•   struct phy *phy;
  

•   unsigned int di_id;
  

+};

+struct imx8qxp_ldb {

•   struct ldb base;
  

•   struct device *dev;
  

•   struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
  

•   struct clk *clk_pixel;
  

•   struct clk *clk_bypass;
  

•   struct drm_bridge *companion;
  

•   int active_chno;
  

+};

+static inline struct imx8qxp_ldb_channel * +base_to_imx8qxp_ldb_channel(struct ldb_channel *base) +{

•   return container_of(base, struct imx8qxp_ldb_channel, base);
  

+}

+static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) +{

•   return container_of(base, struct imx8qxp_ldb, base);
  

+}

+static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,

•                               unsigned long di_clk, bool is_split,
  

•                               struct phy_configure_opts_lvds *phy_cfg)
  

+{

•   phy_cfg->bits_per_lane_and_dclk_cycle = 7;
  

•   phy_cfg->lanes = 4;
  

•   if (is_split) {
  

•           phy_cfg->differential_clk_rate = di_clk / 2;
  

•           phy_cfg->is_slave = !imx8qxp_ldb->companion;
  

•   } else {
  

•           phy_cfg->differential_clk_rate = di_clk;
  

•           phy_cfg->is_slave = false;
  

•   }
  

+}

+static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,

•                              struct drm_bridge_state *bridge_state,
  

•                              struct drm_crtc_state *crtc_state,
  

•                              struct drm_connector_state *conn_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct drm_display_mode *adj = &crtc_state->adjusted_mode;
  

•   unsigned long di_clk = adj->clock * 1000;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   union phy_configure_opts opts = { };
  

•   struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
  

•   int ret;
  

•   ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
  

•                                           crtc_state, conn_state);
  

•   if (ret)
  

•           return ret;
  

•   imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
  

•   ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
  

•   if (ret < 0) {
  

•           DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,
  

•                                "failed to validate PHY: %d\n", ret);
  

•           return ret;
  

•   }
  

•   if (is_split && companion) {
  

•           ret = companion->funcs->atomic_check(companion,
  

•                                   bridge_state, crtc_state, conn_state);
  

•           if (ret)
  

•                   return ret;
  

•   }
  

•   return ret;
  

+}

+static void +imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge,

•                       const struct drm_display_mode *mode,
  

•                       const struct drm_display_mode *adjusted_mode)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb_channel *companion_ldb_ch;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   unsigned long di_clk = adjusted_mode->clock * 1000;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   union phy_configure_opts opts = { };
  

•   struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
  

•   u32 chno = ldb_ch->chno;
  

•   int ret;
  

•   ret = pm_runtime_get_sync(dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
  

•   ret = phy_init(imx8qxp_ldb_ch->phy);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
  

•   ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret);
  

•   if (is_split && companion) {
  

•           companion_ldb_ch = bridge_to_ldb_ch(companion);
  

•           companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format;
  

•           companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format;
  

•   }
  

•   clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk);
  

•   clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk);
  

•   imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
  

•   ret = phy_configure(imx8qxp_ldb_ch->phy, &opts);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
  

•   if (chno == 0)
  

•           ldb->ldb_ctrl &= ~LDB_CH_SEL;
  

•   else
  

•           ldb->ldb_ctrl |= LDB_CH_SEL;
  

•   /* input VSYNC signal from pixel link is active low */
  

•   if (imx8qxp_ldb_ch->di_id == 0)
  

•           ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
  

•   else
  

•           ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
  

•   /*
  

•    * For split mode, settle input VSYNC signal polarity and
  

•    * channel selection down early.
  

•    */
  

•   if (is_split)
  

•           regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
  

•   ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
  

•   if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
  

•   else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL,
  

•                              CH_VSYNC_M(chno), CH_PVSYNC(chno));
  

•   if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
  

•   else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL,
  

•                              CH_HSYNC_M(chno), CH_PHSYNC(chno));
  

•   if (is_split && companion)
  

•           companion->funcs->mode_set(companion, mode, adjusted_mode);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge,

•                                struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   clk_prepare_enable(imx8qxp_ldb->clk_pixel);
  

•   clk_prepare_enable(imx8qxp_ldb->clk_bypass);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_pre_enable(companion, old_bridge_state);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge,

•                            struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   int ret;
  

•   if (ldb_ch->chno == 0 || is_split) {
  

•           ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
  

•           ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
  

•                           LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1;
  

•   }
  

•   if (ldb_ch->chno == 1 || is_split) {
  

•           ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
  

•           ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
  

•                           LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;
  

•   }
  

•   ldb_bridge_enable_helper(bridge);
  

•   ret = phy_power_on(imx8qxp_ldb_ch->phy);
  

•   if (ret)
  

•           DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_enable(companion, old_bridge_state);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge,

•                             struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   int ret;
  

•   ret = phy_power_off(imx8qxp_ldb_ch->phy);
  

•   if (ret)
  

•           DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
  

•   ret = phy_exit(imx8qxp_ldb_ch->phy);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret);
  

•   ldb_bridge_disable_helper(bridge);
  

•   clk_disable_unprepare(imx8qxp_ldb->clk_bypass);
  

•   clk_disable_unprepare(imx8qxp_ldb->clk_pixel);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_disable(companion, old_bridge_state);
  

•   ret = pm_runtime_put(dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
  

+}

+static const u32 imx8qxp_ldb_bus_output_fmts[] = {

•   MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  

•   MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  

•   MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
  

•   MEDIA_BUS_FMT_FIXED,
  

+};

+static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) +{

•   int i;
  

•   for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) {
  

•           if (imx8qxp_ldb_bus_output_fmts[i] == fmt)
  

•                   return true;
  

•   }
  

•   return false;
  

+}

+static u32 * +imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   u32 output_fmt,
  

•                                   unsigned int *num_input_fmts)
  

+{

•   struct drm_display_info *di;
  

•   const struct drm_format_info *finfo;
  

•   u32 *input_fmts;
  

•   if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt))
  

•           return NULL;
  

•   *num_input_fmts = 1;
  

•   input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
  

•   if (!input_fmts)
  

•           return NULL;
  

•   switch (output_fmt) {
  

•   case MEDIA_BUS_FMT_FIXED:
  

•           di = &conn_state->connector->display_info;
  

•           /*
  

•            * Look at the first bus format to determine input format.
  

•            * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match.
  

•            */
  

•           if (di->num_bus_formats) {
  

•                   finfo = drm_format_info(di->bus_formats[0]);
  

•                   input_fmts[0] = finfo->depth == 18 ?
  

•                                   MEDIA_BUS_FMT_RGB666_1X24_CPADHI :
  

•                                   MEDIA_BUS_FMT_RGB888_1X24;
  

•           } else {
  

•                   input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
  

•           }
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  

•   case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
  

•           break;
  

•   default:
  

•           kfree(input_fmts);
  

•           input_fmts = NULL;
  

•           break;
  

•   }
  

•   return input_fmts;
  

+}

+static u32 * +imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   unsigned int *num_output_fmts)
  

+{

•   *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts);
  

•   return kmemdup(imx8qxp_ldb_bus_output_fmts,
  

•                   sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL);
  

+}

+static enum drm_mode_status +imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge,

•                         const struct drm_display_info *info,
  

•                         const struct drm_display_mode *mode)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   bool is_single = ldb_channel_is_single_link(ldb_ch);
  

•   if (mode->clock > 170000)
  

•           return MODE_CLOCK_HIGH;
  

•   if (mode->clock > 150000 && is_single)
  

•           return MODE_CLOCK_HIGH;
  

•   return MODE_OK;
  

+}

+static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = {

•   .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  

•   .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
  

•   .atomic_reset           = drm_atomic_helper_bridge_reset,
  

•   .mode_valid             = imx8qxp_ldb_bridge_mode_valid,
  

•   .attach                 = ldb_bridge_attach_helper,
  

•   .atomic_check           = imx8qxp_ldb_bridge_atomic_check,
  

•   .mode_set               = imx8qxp_ldb_bridge_mode_set,
  

•   .atomic_pre_enable      = imx8qxp_ldb_bridge_atomic_pre_enable,
  

•   .atomic_enable          = imx8qxp_ldb_bridge_atomic_enable,
  

•   .atomic_disable         = imx8qxp_ldb_bridge_atomic_disable,
  

•   .atomic_get_input_bus_fmts =
  

•                   imx8qxp_ldb_bridge_atomic_get_input_bus_fmts,
  

•   .atomic_get_output_bus_fmts =
  

•                   imx8qxp_ldb_bridge_atomic_get_output_bus_fmts,
  

+};

+static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) +{

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                    &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
  

•   struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
  

•   struct device_node *ep, *remote;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   struct of_endpoint endpoint;
  

•   int ret;
  

•   ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1);
  

•   if (!ep) {
  

•           DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n");
  

•           return -EINVAL;
  

•   }
  

•   remote = of_graph_get_remote_endpoint(ep);
  

•   of_node_put(ep);
  

•   if (!remote) {
  

•           DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n");
  

•           return -EINVAL;
  

•   }
  

•   ret = of_graph_parse_endpoint(remote, &endpoint);
  

•   of_node_put(remote);
  

•   if (ret) {
  

•           DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n",
  

•                                                                   ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb_ch->di_id = endpoint.id;
  

•   return 0;
  

+}

+static int +imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) +{

•   if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) ||
  

•       (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1))
  

•           return -EINVAL;
  

•   return 0;
  

+}

+static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) +{

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                    &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
  

•   struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
  

•   struct ldb_channel *companion_ldb_ch;
  

•   struct device_node *companion;
  

•   struct device_node *child;
  

•   struct device_node *companion_port = NULL;
  

•   struct device_node *port1, *port2;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   const struct of_device_id *match;
  

•   u32 i;
  

•   int dual_link;
  

•   int ret;
  

•   /* Locate the companion LDB for dual-link operation, if any. */
  

•   companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0);
  

•   if (!companion)
  

•           return 0;
  

•   if (!of_device_is_available(companion)) {
  

•           DRM_DEV_ERROR(dev, "companion LDB is not available\n");
  

•           ret = -ENODEV;
  

•           goto out;
  

•   }
  

•   /*
  

•    * Sanity check: the companion bridge must have the same compatible
  

•    * string.
  

•    */
  

•   match = of_match_device(dev->driver->of_match_table, dev);
  

•   if (!of_device_is_compatible(companion, match->compatible)) {
  

•           DRM_DEV_ERROR(dev, "companion LDB is incompatible\n");
  

•           ret = -ENXIO;
  

•           goto out;
  

•   }
  

•   for_each_available_child_of_node(companion, child) {
  

•           ret = of_property_read_u32(child, "reg", &i);
  

•           if (ret || i > MAX_LDB_CHAN_NUM - 1) {
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "invalid channel node address: %u\n", i);
  

•                   ret = -EINVAL;
  

•                   of_node_put(child);
  

•                   goto out;
  

•           }
  

•           /*
  

•            * Channel numbers have to be different, because channel0
  

•            * transmits odd pixels and channel1 transmits even pixels.
  

•            */
  

•           if (i == (ldb_ch->chno ^ 0x1)) {
  

•                   companion_port = child;
  

•                   break;
  

•           }
  

•   }
  

•   if (companion_port == NULL) {
  

•           DRM_DEV_ERROR(dev,
  

•                         "failed to find companion LDB channel port\n");
  

•           ret = -EINVAL;
  

•           goto out;
  

•   }
  

•   /*
  

•    * We need to work out if the sink is expecting us to function in
  

•    * dual-link mode.  We do this by looking at the DT port nodes we are
  

•    * connected to.  If they are marked as expecting odd pixels and
  

•    * even pixels than we need to enable LDB split mode.
  

•    */
  

•   port1 = of_graph_get_port_by_id(ldb_ch->np, 1);
  

•   port2 = of_graph_get_port_by_id(companion_port, 1);
  

•   dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
  

•   of_node_put(port1);
  

•   of_node_put(port2);
  

•   switch (dual_link) {
  

•   case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
  

•           ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
  

•           break;
  

•   case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
  

•           ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS;
  

•           break;
  

•   default:
  

•           ret = dual_link;
  

•           DRM_DEV_ERROR(dev,
  

•                         "failed to get dual link pixel order: %d\n", ret);
  

•           goto out;
  

•   }
  

•   ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link);
  

•   if (ret < 0) {
  

•           DRM_DEV_ERROR(dev,
  

•                         "unmatched channel number(%u) vs dual link(%d)\n",
  

•                                                   ldb_ch->chno, dual_link);
  

•           goto out;
  

•   }
  

•   imx8qxp_ldb->companion = of_drm_find_bridge(companion_port);
  

•   if (!imx8qxp_ldb->companion) {
  

•           ret = -EPROBE_DEFER;
  

•           DRM_DEV_DEBUG_DRIVER(dev,
  

•                  "failed to find bridge for companion bridge: %d\n", ret);
  

•           goto out;
  

•   }
  

•   DRM_DEV_DEBUG_DRIVER(dev,
  

•           "dual-link configuration detected (companion bridge %pOF)\n",
  

•                                                           companion);
  

•   companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion);
  

•   companion_ldb_ch->link_type = ldb_ch->link_type;
  

+out:

•   of_node_put(companion_port);
  

•   of_node_put(companion);
  

•   return ret;
  

+}

+static int imx8qxp_ldb_probe(struct platform_device *pdev) +{

•   struct device *dev = &pdev->dev;
  

•   struct imx8qxp_ldb *imx8qxp_ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch;
  

•   struct ldb *ldb;
  

•   struct ldb_channel *ldb_ch;
  

•   int ret, i;
  

•   imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL);
  

•   if (!imx8qxp_ldb)
  

•           return -ENOMEM;
  

•   imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel");
  

•   if (IS_ERR(imx8qxp_ldb->clk_pixel)) {
  

•           ret = PTR_ERR(imx8qxp_ldb->clk_pixel);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "failed to get pixel clock: %d\n", ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass");
  

•   if (IS_ERR(imx8qxp_ldb->clk_bypass)) {
  

•           ret = PTR_ERR(imx8qxp_ldb->clk_bypass);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "failed to get bypass clock: %d\n", ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb->dev = dev;
  

•   ldb = &imx8qxp_ldb->base;
  

•   ldb->dev = dev;
  

•   ldb->ctrl_reg = 0xe0;
  

•   for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
  

•           ldb->channel[i] = &imx8qxp_ldb->channel[i].base;
  

•   ret = ldb_init_helper(ldb);
  

•   if (ret)
  

•           return ret;
  

•   if (ldb->available_ch_cnt == 0) {
  

•           DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
  

•           return 0;
  

•   } else if (ldb->available_ch_cnt > 1) {
  

•           DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n",
  

•                                                   ldb->available_ch_cnt);
  

•           return -ENOTSUPP;
  

•   }
  

WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP #683: FILE: drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c:625: + return -ENOTSUPP;

Maybe -EINVAL is a better return value.

Hey Liu,

checkpatch --strict lists some nits and a warning. I think the kconfig warning can be ignored. With the rest fixed, feel free to add my r-b.

Reviewed-by: Robert Foss robert.foss@linaro.org

On Wed, 17 Mar 2021 at 04:57, Liu Ying victor.liu@nxp.com wrote:

This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB) which is officially named as pixel mapper. The LDB has two channels. Each of them supports up to 24bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels cannot be used simultaneously, that is to say, the user should pick one of them to use. Two LDB channels from two LDB instances can work together in LDB split mode to support a dual link LVDS display. The channel indexes have to be different. Channel0 outputs odd pixels and channel1 outputs even pixels. This patch supports the LDB single mode and split mode.

Signed-off-by: Liu Ying victor.liu@nxp.com

Note that this patch depends on the patch 'phy: Add LVDS configuration options', which has already been sent with the following series to add Mixel combo PHY found in i.MX8qxp: https://www.spinics.net/lists/arm-kernel/msg879957.html

v5->v6:

• No change.

v4->v5:

• Link with the imx-ldb-helper object. (Robert)
• Correspondingly, rename 'imx8qxp-ldb.c' to 'imx8qxp-ldb-drv.c'.

v3->v4:

• No change.

v2->v3:

• No change.

v1->v2:

• Drop unnecessary DT validation.
• Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to get the input remote endpoint in imx8qxp_ldb_set_di_id().
• Avoid using companion_port OF node after putting it in imx8qxp_ldb_parse_dt_companion().
• Mention i.MX8qxp LDB official name 'pixel mapper' in the bridge driver and Kconfig help message.

drivers/gpu/drm/bridge/imx/Kconfig | 9 + drivers/gpu/drm/bridge/imx/Makefile | 3 + drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 720 +++++++++++++++++++++++++++ 3 files changed, 732 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 1ea1ce7..94f8db4d 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -1,3 +1,12 @@ +config DRM_IMX8QXP_LDB

•   tristate "Freescale i.MX8QXP LVDS display bridge"
  

•   depends on OF
  

•   depends on COMMON_CLK
  

•   select DRM_KMS_HELPER
  

•   help
  

•     Choose this to enable the internal LVDS Display Bridge(LDB) found in
  

•     Freescale i.MX8qxp processor.  Official name of LDB is pixel mapper.
  

config DRM_IMX8QXP_PIXEL_COMBINER tristate "Freescale i.MX8QM/QXP pixel combiner" depends on OF diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index e74dd64..96d5d1e 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,3 +1,6 @@ +imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o +obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o

obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c new file mode 100644 index 00000000..d7f59c1 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0+

+/*

• • Copyright 2020 NXP
• */

+#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h>

+#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+#include "imx-ldb-helper.h"

+#define LDB_CH_SEL (1 << 28)

+#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2))

+#define DRIVER_NAME "imx8qxp-ldb"

+struct imx8qxp_ldb_channel {

•   struct ldb_channel base;
  

•   struct phy *phy;
  

•   unsigned int di_id;
  

+};

+struct imx8qxp_ldb {

•   struct ldb base;
  

•   struct device *dev;
  

•   struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
  

•   struct clk *clk_pixel;
  

•   struct clk *clk_bypass;
  

•   struct drm_bridge *companion;
  

•   int active_chno;
  

+};

+static inline struct imx8qxp_ldb_channel * +base_to_imx8qxp_ldb_channel(struct ldb_channel *base) +{

•   return container_of(base, struct imx8qxp_ldb_channel, base);
  

+}

+static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) +{

•   return container_of(base, struct imx8qxp_ldb, base);
  

+}

+static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,

•                               unsigned long di_clk, bool is_split,
  

•                               struct phy_configure_opts_lvds *phy_cfg)
  

+{

•   phy_cfg->bits_per_lane_and_dclk_cycle = 7;
  

•   phy_cfg->lanes = 4;
  

•   if (is_split) {
  

•           phy_cfg->differential_clk_rate = di_clk / 2;
  

•           phy_cfg->is_slave = !imx8qxp_ldb->companion;
  

•   } else {
  

•           phy_cfg->differential_clk_rate = di_clk;
  

•           phy_cfg->is_slave = false;
  

•   }
  

+}

+static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,

•                              struct drm_bridge_state *bridge_state,
  

•                              struct drm_crtc_state *crtc_state,
  

•                              struct drm_connector_state *conn_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct drm_display_mode *adj = &crtc_state->adjusted_mode;
  

•   unsigned long di_clk = adj->clock * 1000;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   union phy_configure_opts opts = { };
  

•   struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
  

•   int ret;
  

•   ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
  

•                                           crtc_state, conn_state);
  

•   if (ret)
  

•           return ret;
  

•   imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
  

•   ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
  

•   if (ret < 0) {
  

•           DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,
  

•                                "failed to validate PHY: %d\n", ret);
  

•           return ret;
  

•   }
  

•   if (is_split && companion) {
  

•           ret = companion->funcs->atomic_check(companion,
  

•                                   bridge_state, crtc_state, conn_state);
  

•           if (ret)
  

•                   return ret;
  

•   }
  

•   return ret;
  

+}

+static void +imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge,

•                       const struct drm_display_mode *mode,
  

•                       const struct drm_display_mode *adjusted_mode)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb_channel *companion_ldb_ch;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   unsigned long di_clk = adjusted_mode->clock * 1000;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   union phy_configure_opts opts = { };
  

•   struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
  

•   u32 chno = ldb_ch->chno;
  

•   int ret;
  

•   ret = pm_runtime_get_sync(dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
  

•   ret = phy_init(imx8qxp_ldb_ch->phy);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
  

•   ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret);
  

•   if (is_split && companion) {
  

•           companion_ldb_ch = bridge_to_ldb_ch(companion);
  

•           companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format;
  

•           companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format;
  

•   }
  

•   clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk);
  

•   clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk);
  

•   imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
  

•   ret = phy_configure(imx8qxp_ldb_ch->phy, &opts);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
  

•   if (chno == 0)
  

•           ldb->ldb_ctrl &= ~LDB_CH_SEL;
  

•   else
  

•           ldb->ldb_ctrl |= LDB_CH_SEL;
  

•   /* input VSYNC signal from pixel link is active low */
  

•   if (imx8qxp_ldb_ch->di_id == 0)
  

•           ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
  

•   else
  

•           ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
  

•   /*
  

•    * For split mode, settle input VSYNC signal polarity and
  

•    * channel selection down early.
  

•    */
  

•   if (is_split)
  

•           regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
  

•   ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
  

•   if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
  

•   else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL,
  

•                              CH_VSYNC_M(chno), CH_PVSYNC(chno));
  

•   if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
  

•   else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  

•           regmap_update_bits(ldb->regmap, SS_CTRL,
  

•                              CH_HSYNC_M(chno), CH_PHSYNC(chno));
  

•   if (is_split && companion)
  

•           companion->funcs->mode_set(companion, mode, adjusted_mode);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge,

•                                struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   clk_prepare_enable(imx8qxp_ldb->clk_pixel);
  

•   clk_prepare_enable(imx8qxp_ldb->clk_bypass);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_pre_enable(companion, old_bridge_state);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge,

•                            struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   int ret;
  

•   if (ldb_ch->chno == 0 || is_split) {
  

•           ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
  

•           ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
  

•                           LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1;
  

•   }
  

•   if (ldb_ch->chno == 1 || is_split) {
  

•           ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
  

•           ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
  

•                           LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;
  

•   }
  

•   ldb_bridge_enable_helper(bridge);
  

•   ret = phy_power_on(imx8qxp_ldb_ch->phy);
  

•   if (ret)
  

•           DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_enable(companion, old_bridge_state);
  

+}

+static void +imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge,

•                             struct drm_bridge_state *old_bridge_state)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   struct ldb *ldb = ldb_ch->ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                                   base_to_imx8qxp_ldb_channel(ldb_ch);
  

•   struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
  

•   struct drm_bridge *companion = imx8qxp_ldb->companion;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   bool is_split = ldb_channel_is_split_link(ldb_ch);
  

•   int ret;
  

•   ret = phy_power_off(imx8qxp_ldb_ch->phy);
  

•   if (ret)
  

•           DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
  

•   ret = phy_exit(imx8qxp_ldb_ch->phy);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret);
  

•   ldb_bridge_disable_helper(bridge);
  

•   clk_disable_unprepare(imx8qxp_ldb->clk_bypass);
  

•   clk_disable_unprepare(imx8qxp_ldb->clk_pixel);
  

•   if (is_split && companion)
  

•           companion->funcs->atomic_disable(companion, old_bridge_state);
  

•   ret = pm_runtime_put(dev);
  

•   if (ret < 0)
  

•           DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
  

+}

+static const u32 imx8qxp_ldb_bus_output_fmts[] = {

•   MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  

•   MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  

•   MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
  

•   MEDIA_BUS_FMT_FIXED,
  

+};

+static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) +{

•   int i;
  

•   for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) {
  

•           if (imx8qxp_ldb_bus_output_fmts[i] == fmt)
  

•                   return true;
  

•   }
  

•   return false;
  

+}

+static u32 * +imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   u32 output_fmt,
  

•                                   unsigned int *num_input_fmts)
  

+{

•   struct drm_display_info *di;
  

•   const struct drm_format_info *finfo;
  

•   u32 *input_fmts;
  

•   if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt))
  

•           return NULL;
  

•   *num_input_fmts = 1;
  

•   input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
  

•   if (!input_fmts)
  

•           return NULL;
  

•   switch (output_fmt) {
  

•   case MEDIA_BUS_FMT_FIXED:
  

•           di = &conn_state->connector->display_info;
  

•           /*
  

•            * Look at the first bus format to determine input format.
  

•            * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match.
  

•            */
  

•           if (di->num_bus_formats) {
  

•                   finfo = drm_format_info(di->bus_formats[0]);
  

•                   input_fmts[0] = finfo->depth == 18 ?
  

•                                   MEDIA_BUS_FMT_RGB666_1X24_CPADHI :
  

•                                   MEDIA_BUS_FMT_RGB888_1X24;
  

•           } else {
  

•                   input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
  

•           }
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
  

•           break;
  

•   case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  

•   case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  

•           input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
  

•           break;
  

•   default:
  

•           kfree(input_fmts);
  

•           input_fmts = NULL;
  

•           break;
  

•   }
  

•   return input_fmts;
  

+}

+static u32 * +imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,

•                                   struct drm_bridge_state *bridge_state,
  

•                                   struct drm_crtc_state *crtc_state,
  

•                                   struct drm_connector_state *conn_state,
  

•                                   unsigned int *num_output_fmts)
  

+{

•   *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts);
  

•   return kmemdup(imx8qxp_ldb_bus_output_fmts,
  

•                   sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL);
  

+}

+static enum drm_mode_status +imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge,

•                         const struct drm_display_info *info,
  

•                         const struct drm_display_mode *mode)
  

+{

•   struct ldb_channel *ldb_ch = bridge->driver_private;
  

•   bool is_single = ldb_channel_is_single_link(ldb_ch);
  

•   if (mode->clock > 170000)
  

•           return MODE_CLOCK_HIGH;
  

•   if (mode->clock > 150000 && is_single)
  

•           return MODE_CLOCK_HIGH;
  

•   return MODE_OK;
  

+}

+static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = {

•   .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  

•   .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
  

•   .atomic_reset           = drm_atomic_helper_bridge_reset,
  

•   .mode_valid             = imx8qxp_ldb_bridge_mode_valid,
  

•   .attach                 = ldb_bridge_attach_helper,
  

•   .atomic_check           = imx8qxp_ldb_bridge_atomic_check,
  

•   .mode_set               = imx8qxp_ldb_bridge_mode_set,
  

•   .atomic_pre_enable      = imx8qxp_ldb_bridge_atomic_pre_enable,
  

•   .atomic_enable          = imx8qxp_ldb_bridge_atomic_enable,
  

•   .atomic_disable         = imx8qxp_ldb_bridge_atomic_disable,
  

•   .atomic_get_input_bus_fmts =
  

•                   imx8qxp_ldb_bridge_atomic_get_input_bus_fmts,
  

•   .atomic_get_output_bus_fmts =
  

•                   imx8qxp_ldb_bridge_atomic_get_output_bus_fmts,
  

+};

+static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) +{

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                    &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
  

•   struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
  

•   struct device_node *ep, *remote;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   struct of_endpoint endpoint;
  

•   int ret;
  

•   ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1);
  

•   if (!ep) {
  

•           DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n");
  

•           return -EINVAL;
  

•   }
  

•   remote = of_graph_get_remote_endpoint(ep);
  

•   of_node_put(ep);
  

•   if (!remote) {
  

•           DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n");
  

•           return -EINVAL;
  

•   }
  

•   ret = of_graph_parse_endpoint(remote, &endpoint);
  

•   of_node_put(remote);
  

•   if (ret) {
  

•           DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n",
  

•                                                                   ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb_ch->di_id = endpoint.id;
  

•   return 0;
  

+}

+static int +imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) +{

•   if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) ||
  

•       (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1))
  

•           return -EINVAL;
  

•   return 0;
  

+}

+static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) +{

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
  

•                    &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
  

•   struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
  

•   struct ldb_channel *companion_ldb_ch;
  

•   struct device_node *companion;
  

•   struct device_node *child;
  

•   struct device_node *companion_port = NULL;
  

•   struct device_node *port1, *port2;
  

•   struct device *dev = imx8qxp_ldb->dev;
  

•   const struct of_device_id *match;
  

•   u32 i;
  

•   int dual_link;
  

•   int ret;
  

•   /* Locate the companion LDB for dual-link operation, if any. */
  

•   companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0);
  

•   if (!companion)
  

•           return 0;
  

•   if (!of_device_is_available(companion)) {
  

•           DRM_DEV_ERROR(dev, "companion LDB is not available\n");
  

•           ret = -ENODEV;
  

•           goto out;
  

•   }
  

•   /*
  

•    * Sanity check: the companion bridge must have the same compatible
  

•    * string.
  

•    */
  

•   match = of_match_device(dev->driver->of_match_table, dev);
  

•   if (!of_device_is_compatible(companion, match->compatible)) {
  

•           DRM_DEV_ERROR(dev, "companion LDB is incompatible\n");
  

•           ret = -ENXIO;
  

•           goto out;
  

•   }
  

•   for_each_available_child_of_node(companion, child) {
  

•           ret = of_property_read_u32(child, "reg", &i);
  

•           if (ret || i > MAX_LDB_CHAN_NUM - 1) {
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "invalid channel node address: %u\n", i);
  

•                   ret = -EINVAL;
  

•                   of_node_put(child);
  

•                   goto out;
  

•           }
  

•           /*
  

•            * Channel numbers have to be different, because channel0
  

•            * transmits odd pixels and channel1 transmits even pixels.
  

•            */
  

•           if (i == (ldb_ch->chno ^ 0x1)) {
  

•                   companion_port = child;
  

•                   break;
  

•           }
  

•   }
  

•   if (companion_port == NULL) {
  

•           DRM_DEV_ERROR(dev,
  

•                         "failed to find companion LDB channel port\n");
  

•           ret = -EINVAL;
  

•           goto out;
  

•   }
  

•   /*
  

•    * We need to work out if the sink is expecting us to function in
  

•    * dual-link mode.  We do this by looking at the DT port nodes we are
  

•    * connected to.  If they are marked as expecting odd pixels and
  

•    * even pixels than we need to enable LDB split mode.
  

•    */
  

•   port1 = of_graph_get_port_by_id(ldb_ch->np, 1);
  

•   port2 = of_graph_get_port_by_id(companion_port, 1);
  

•   dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
  

•   of_node_put(port1);
  

•   of_node_put(port2);
  

•   switch (dual_link) {
  

•   case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
  

•           ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
  

•           break;
  

•   case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
  

•           ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS;
  

•           break;
  

•   default:
  

•           ret = dual_link;
  

•           DRM_DEV_ERROR(dev,
  

•                         "failed to get dual link pixel order: %d\n", ret);
  

•           goto out;
  

•   }
  

•   ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link);
  

•   if (ret < 0) {
  

•           DRM_DEV_ERROR(dev,
  

•                         "unmatched channel number(%u) vs dual link(%d)\n",
  

•                                                   ldb_ch->chno, dual_link);
  

•           goto out;
  

•   }
  

•   imx8qxp_ldb->companion = of_drm_find_bridge(companion_port);
  

•   if (!imx8qxp_ldb->companion) {
  

•           ret = -EPROBE_DEFER;
  

•           DRM_DEV_DEBUG_DRIVER(dev,
  

•                  "failed to find bridge for companion bridge: %d\n", ret);
  

•           goto out;
  

•   }
  

•   DRM_DEV_DEBUG_DRIVER(dev,
  

•           "dual-link configuration detected (companion bridge %pOF)\n",
  

•                                                           companion);
  

•   companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion);
  

•   companion_ldb_ch->link_type = ldb_ch->link_type;
  

+out:

•   of_node_put(companion_port);
  

•   of_node_put(companion);
  

•   return ret;
  

+}

+static int imx8qxp_ldb_probe(struct platform_device *pdev) +{

•   struct device *dev = &pdev->dev;
  

•   struct imx8qxp_ldb *imx8qxp_ldb;
  

•   struct imx8qxp_ldb_channel *imx8qxp_ldb_ch;
  

•   struct ldb *ldb;
  

•   struct ldb_channel *ldb_ch;
  

•   int ret, i;
  

•   imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL);
  

•   if (!imx8qxp_ldb)
  

•           return -ENOMEM;
  

•   imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel");
  

•   if (IS_ERR(imx8qxp_ldb->clk_pixel)) {
  

•           ret = PTR_ERR(imx8qxp_ldb->clk_pixel);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "failed to get pixel clock: %d\n", ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass");
  

•   if (IS_ERR(imx8qxp_ldb->clk_bypass)) {
  

•           ret = PTR_ERR(imx8qxp_ldb->clk_bypass);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev,
  

•                                 "failed to get bypass clock: %d\n", ret);
  

•           return ret;
  

•   }
  

•   imx8qxp_ldb->dev = dev;
  

•   ldb = &imx8qxp_ldb->base;
  

•   ldb->dev = dev;
  

•   ldb->ctrl_reg = 0xe0;
  

•   for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
  

•           ldb->channel[i] = &imx8qxp_ldb->channel[i].base;
  

•   ret = ldb_init_helper(ldb);
  

•   if (ret)
  

•           return ret;
  

•   if (ldb->available_ch_cnt == 0) {
  

•           DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
  

•           return 0;
  

•   } else if (ldb->available_ch_cnt > 1) {
  

•           DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n",
  

•                                                   ldb->available_ch_cnt);
  

•           return -ENOTSUPP;
  

•   }
  

•   for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
  

•           imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i];
  

•           ldb_ch = &imx8qxp_ldb_ch->base;
  

•           if (ldb_ch->is_available) {
  

•                   imx8qxp_ldb->active_chno = ldb_ch->chno;
  

•                   break;
  

•           }
  

•   }
  

•   imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy");
  

•   if (IS_ERR(imx8qxp_ldb_ch->phy)) {
  

•           ret = PTR_ERR(imx8qxp_ldb_ch->phy);
  

•           if (ret != -EPROBE_DEFER)
  

•                   DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n",
  

•                                           imx8qxp_ldb->active_chno, ret);
  

•           return ret;
  

•   }
  

•   ret = ldb_find_next_bridge_helper(ldb);
  

•   if (ret)
  

•           return ret;
  

•   ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb);
  

•   if (ret)
  

•           return ret;
  

•   ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb);
  

•   if (ret)
  

•           return ret;
  

•   platform_set_drvdata(pdev, imx8qxp_ldb);
  

•   pm_runtime_enable(dev);
  

•   ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs);
  

•   return ret;
  

+}

+static int imx8qxp_ldb_remove(struct platform_device *pdev) +{

•   struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev);
  

•   struct ldb *ldb = &imx8qxp_ldb->base;
  

•   ldb_remove_bridge_helper(ldb);
  

•   pm_runtime_disable(&pdev->dev);
  

•   return 0;
  

+}

+static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) +{

•   return 0;
  

+}

+static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) +{

•   struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev);
  

•   struct ldb *ldb = &imx8qxp_ldb->base;
  

•   /* disable LDB by resetting the control register to POR default */
  

•   regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
  

•   return 0;
  

+}

+static const struct dev_pm_ops imx8qxp_ldb_pm_ops = {

•   SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend,
  

•                      imx8qxp_ldb_runtime_resume, NULL)
  

+};

+static const struct of_device_id imx8qxp_ldb_dt_ids[] = {

•   { .compatible = "fsl,imx8qxp-ldb" },
  

•   { /* sentinel */ }
  

+}; +MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids);

+static struct platform_driver imx8qxp_ldb_driver = {

•   .probe  = imx8qxp_ldb_probe,
  

•   .remove = imx8qxp_ldb_remove,
  

•   .driver = {
  

•           .pm = &imx8qxp_ldb_pm_ops,
  

•           .name = DRIVER_NAME,
  

•           .of_match_table = imx8qxp_ldb_dt_ids,
  

•   },
  

+}; +module_platform_driver(imx8qxp_ldb_driver);

+MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); +MODULE_AUTHOR("Liu Ying victor.liu@nxp.com"); +MODULE_LICENSE("GPL v2");

+MODULE_ALIAS("platform:" DRIVER_NAME);

2.7.4