I am using an Analogix SP6001 SlimPort Micro-USB to 4K HDMI Adapter to connect my Nexus 5 phone to an external display. The external display is not fully working yet however I think I'm close. When I plug the cable into the phone, the interrupt for the hot plug detect GPIO for the HDMI bridge (Analogix ANX7808) fires and anx78xx_handle_common_int_4() shows that the interrupt status bit is set to SP_HPD_ESYNC_ERR.
The second hot plug detect pin (for qcom,hdmi-tx-8974 for the MSM KMS/DRM driver) does not fire, and the clocks are not configured via msm_hdmi_phy_pll_init(). I suspect that this is the issue that I need to solve next.
I verified in the downstream MSM sources that IRQ 8 on the mdss is the correct IRQ number for hdmi-tx. Here's the relevant line from /proc/interrupts showing that no interrupts are triggered: 93: 0 0 0 0 mdss 8 Edge hdmi_isr.
I'm going to continue digging through the code but I'd appreciate any suggestions for things to check. I assume that the IRQs for both hot plug detect pins should fire when I plug the cable in. Unfortunately, the display doesn't work for me with the downstream kernel and I only have access to a running downstream kernel over the serial console.
High-level changes since v1: - Hot plug detect interrupt now working properly on HDMI bridge - Introduce msm8974 PLL support
I've held back some cosmetic changes to the drivers and only included the necessary changes required to get this functional. This requires the following patch I sent out on 2019-09-22 to analogix-anx78xx that corrects an i2c address: https://lore.kernel.org/lkml/20190922175940.5311-1-masneyb@onstation.org/
Brian Masney (5): drm/bridge: analogix-anx78xx: add support for avdd33 regulator drm/msm/hdmi: add msm8974 PLL support ARM: dts: qcom: pm8941: add 5vs2 regulator node ARM: dts: qcom: msm8974: add HDMI nodes ARM: dts: qcom: msm8974-hammerhead: add support for external display
.../qcom-msm8974-lge-nexus5-hammerhead.dts | 142 ++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 78 ++ arch/arm/boot/dts/qcom-pm8941.dtsi | 10 + drivers/gpu/drm/bridge/analogix-anx78xx.c | 33 + drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/hdmi/hdmi.h | 6 + drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 4 +- drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c | 684 ++++++++++++++++++ 8 files changed, 957 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c
Add support for the avdd33 regulator to the analogix-anx78xx driver. Note that the regulator is currently enabled during driver probe and disabled when the driver is removed. This is currently how the downstream MSM kernel sources do this.
Let's not merge this upstream for the mean time until I get the external display fully working on the Nexus 5 and then I can submit proper support then that powers down this regulator in the power off function.
Signed-off-by: Brian Masney masneyb@onstation.org --- Changes since v1: - None
drivers/gpu/drm/bridge/analogix-anx78xx.c | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c index dec3f7e66aa0..e25fae36dbe1 100644 --- a/drivers/gpu/drm/bridge/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c @@ -56,6 +56,7 @@ static const u8 anx781x_i2c_addresses[] = {
struct anx78xx_platform_data { struct regulator *dvdd10; + struct regulator *avdd33; struct gpio_desc *gpiod_hpd; struct gpio_desc *gpiod_pd; struct gpio_desc *gpiod_reset; @@ -715,10 +716,42 @@ static int anx78xx_start(struct anx78xx *anx78xx) return err; }
+static void anx78xx_disable_regulator_action(void *_data) +{ + struct anx78xx_platform_data *pdata = _data; + + regulator_disable(pdata->avdd33); +} + static int anx78xx_init_pdata(struct anx78xx *anx78xx) { struct anx78xx_platform_data *pdata = &anx78xx->pdata; struct device *dev = &anx78xx->client->dev; + int err; + + /* 3.3V digital core power regulator */ + pdata->avdd33 = devm_regulator_get(dev, "avdd33"); + if (IS_ERR(pdata->avdd33)) { + err = PTR_ERR(pdata->avdd33); + if (err != -EPROBE_DEFER) + DRM_ERROR("avdd33 regulator not found\n"); + + return err; + } + + err = regulator_enable(pdata->avdd33); + if (err) { + DRM_ERROR("Failed to enable avdd33 regulator: %d\n", err); + return err; + } + + err = devm_add_action(dev, anx78xx_disable_regulator_action, + pdata); + if (err < 0) { + dev_err(dev, "Failed to setup regulator cleanup action %d\n", + err); + return err; + }
/* 1.0V digital core power regulator */ pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
Hi Brian,
Thank you for the patch.
On Sun, Oct 06, 2019 at 09:45:05PM -0400, Brian Masney wrote:
Add support for the avdd33 regulator to the analogix-anx78xx driver. Note that the regulator is currently enabled during driver probe and disabled when the driver is removed. This is currently how the downstream MSM kernel sources do this.
Let's not merge this upstream for the mean time until I get the external display fully working on the Nexus 5 and then I can submit proper support then that powers down this regulator in the power off function.
Please then also update the corresponding DT bindings to describe the avdd33 supply.
Signed-off-by: Brian Masney masneyb@onstation.org
Changes since v1:
- None
drivers/gpu/drm/bridge/analogix-anx78xx.c | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix-anx78xx.c index dec3f7e66aa0..e25fae36dbe1 100644 --- a/drivers/gpu/drm/bridge/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c @@ -56,6 +56,7 @@ static const u8 anx781x_i2c_addresses[] = {
struct anx78xx_platform_data { struct regulator *dvdd10;
- struct regulator *avdd33; struct gpio_desc *gpiod_hpd; struct gpio_desc *gpiod_pd; struct gpio_desc *gpiod_reset;
@@ -715,10 +716,42 @@ static int anx78xx_start(struct anx78xx *anx78xx) return err; }
+static void anx78xx_disable_regulator_action(void *_data) +{
- struct anx78xx_platform_data *pdata = _data;
- regulator_disable(pdata->avdd33);
+}
static int anx78xx_init_pdata(struct anx78xx *anx78xx) { struct anx78xx_platform_data *pdata = &anx78xx->pdata; struct device *dev = &anx78xx->client->dev;
int err;
/* 3.3V digital core power regulator */
pdata->avdd33 = devm_regulator_get(dev, "avdd33");
if (IS_ERR(pdata->avdd33)) {
err = PTR_ERR(pdata->avdd33);if (err != -EPROBE_DEFER)DRM_ERROR("avdd33 regulator not found\n");return err;}
err = regulator_enable(pdata->avdd33);
if (err) {
DRM_ERROR("Failed to enable avdd33 regulator: %d\n", err);return err;}
err = devm_add_action(dev, anx78xx_disable_regulator_action,
pdata);if (err < 0) {
dev_err(dev, "Failed to setup regulator cleanup action %d\n",err);return err;}
/* 1.0V digital core power regulator */ pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
Add msm8974 Phase-Locked Loop (PLL) support to the MSM HDMI so that an external display can be used on this SoC.
Signed-off-by: Brian Masney masneyb@onstation.org --- Changes since v1: - New patch introduced in v2
drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/hdmi/hdmi.h | 6 + drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 4 +- drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c | 684 +++++++++++++++++++++++ 4 files changed, 694 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7a05cbf2f820..fa1c9cf86e38 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -100,6 +100,7 @@ msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o +msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8974.o msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h index 982865866a29..59c3cf09cb0d 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -184,6 +184,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK int msm_hdmi_pll_8960_init(struct platform_device *pdev); +int msm_hdmi_pll_8974_init(struct platform_device *pdev); int msm_hdmi_pll_8996_init(struct platform_device *pdev); #else static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) @@ -191,6 +192,11 @@ static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) return -ENODEV; }
+static inline int msm_hdmi_pll_8974_init(struct platform_device *pdev) +{ + return -ENODEV; +} + static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev) { return -ENODEV; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c index 8a38d4b95102..29d01004ee3b 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy.c @@ -123,6 +123,9 @@ static int msm_hdmi_phy_pll_init(struct platform_device *pdev, case MSM_HDMI_PHY_8960: ret = msm_hdmi_pll_8960_init(pdev); break; + case MSM_HDMI_PHY_8x74: + ret = msm_hdmi_pll_8974_init(pdev); + break; case MSM_HDMI_PHY_8996: ret = msm_hdmi_pll_8996_init(pdev); break; @@ -130,7 +133,6 @@ static int msm_hdmi_phy_pll_init(struct platform_device *pdev, * we don't have PLL support for these, don't report an error for now */ case MSM_HDMI_PHY_8x60: - case MSM_HDMI_PHY_8x74: default: ret = 0; break; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c new file mode 100644 index 000000000000..6ce0648ae71d --- /dev/null +++ b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8974.c @@ -0,0 +1,684 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 Brian Masney masneyb@onstation.org + * + * Based on clock-mdss-8974.c in downstream MSM sources. + * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. + * + * Based on hdmi_pll_8960.c + * Copyright (C) 2013 Red Hat + * Copyright (c) 2016 The Linux Foundation. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/delay.h> + +#include "hdmi.h" + +/* hdmi phy registers */ +#define HDMI_PHY_ANA_CFG0 0x0000 +#define HDMI_PHY_ANA_CFG1 0x0004 +#define HDMI_PHY_ANA_CFG2 0x0008 +#define HDMI_PHY_ANA_CFG3 0x000c +#define HDMI_PHY_PD_CTRL0 0x0010 +#define HDMI_PHY_PD_CTRL1 0x0014 +#define HDMI_PHY_GLB_CFG 0x0018 +#define HDMI_PHY_DCC_CFG0 0x001c +#define HDMI_PHY_DCC_CFG1 0x0020 +#define HDMI_PHY_TXCAL_CFG0 0x0024 +#define HDMI_PHY_TXCAL_CFG1 0x0028 +#define HDMI_PHY_TXCAL_CFG2 0x002c +#define HDMI_PHY_TXCAL_CFG3 0x0030 +#define HDMI_PHY_BIST_CFG0 0x0034 +#define HDMI_PHY_BIST_CFG1 0x0038 +#define HDMI_PHY_BIST_PATN0 0x003c +#define HDMI_PHY_BIST_PATN1 0x0040 +#define HDMI_PHY_BIST_PATN2 0x0044 +#define HDMI_PHY_BIST_PATN3 0x0048 +#define HDMI_PHY_STATUS 0x005c + +/* hdmi phy unified pll registers */ +#define HDMI_UNI_PLL_REFCLK_CFG 0x0000 +#define HDMI_UNI_PLL_POSTDIV1_CFG 0x0004 +#define HDMI_UNI_PLL_CHFPUMP_CFG 0x0008 +#define HDMI_UNI_PLL_VCOLPF_CFG 0x000c +#define HDMI_UNI_PLL_VREG_CFG 0x0010 +#define HDMI_UNI_PLL_PWRGEN_CFG 0x0014 +#define HDMI_UNI_PLL_GLB_CFG 0x0020 +#define HDMI_UNI_PLL_POSTDIV2_CFG 0x0024 +#define HDMI_UNI_PLL_POSTDIV3_CFG 0x0028 +#define HDMI_UNI_PLL_LPFR_CFG 0x002c +#define HDMI_UNI_PLL_LPFC1_CFG 0x0030 +#define HDMI_UNI_PLL_LPFC2_CFG 0x0034 +#define HDMI_UNI_PLL_SDM_CFG0 0x0038 +#define HDMI_UNI_PLL_SDM_CFG1 0x003c +#define HDMI_UNI_PLL_SDM_CFG2 0x0040 +#define HDMI_UNI_PLL_SDM_CFG3 0x0044 +#define HDMI_UNI_PLL_SDM_CFG4 0x0048 +#define HDMI_UNI_PLL_SSC_CFG0 0x004c +#define HDMI_UNI_PLL_SSC_CFG1 0x0050 +#define HDMI_UNI_PLL_SSC_CFG2 0x0054 +#define HDMI_UNI_PLL_SSC_CFG3 0x0058 +#define HDMI_UNI_PLL_LKDET_CFG0 0x005c +#define HDMI_UNI_PLL_LKDET_CFG1 0x0060 +#define HDMI_UNI_PLL_LKDET_CFG2 0x0064 +#define HDMI_UNI_PLL_CAL_CFG0 0x006c +#define HDMI_UNI_PLL_CAL_CFG1 0x0070 +#define HDMI_UNI_PLL_CAL_CFG2 0x0074 +#define HDMI_UNI_PLL_CAL_CFG3 0x0078 +#define HDMI_UNI_PLL_CAL_CFG4 0x007c +#define HDMI_UNI_PLL_CAL_CFG5 0x0080 +#define HDMI_UNI_PLL_CAL_CFG6 0x0084 +#define HDMI_UNI_PLL_CAL_CFG7 0x0088 +#define HDMI_UNI_PLL_CAL_CFG8 0x008c +#define HDMI_UNI_PLL_CAL_CFG9 0x0090 +#define HDMI_UNI_PLL_CAL_CFG10 0x0094 +#define HDMI_UNI_PLL_CAL_CFG11 0x0098 +#define HDMI_UNI_PLL_STATUS 0x00c0 + +struct msm8974_hdmi { + struct platform_device *pdev; + struct clk_hw clk_hw; + void __iomem *mmio; + unsigned long pixclk; +}; + +#define hw_clk_to_msm8974_hdmi(x) container_of(x, struct msm8974_hdmi, clk_hw) + +struct msm8974_hdmi_reg { + void (*write)(struct msm8974_hdmi *hdmi, u32 reg, u32 data); + u32 val; + u32 reg; +}; + +#define MSM8974_HDMI_NUM_REGS 38 + +struct msm8974_hdmi_rate { + unsigned long rate; + struct msm8974_hdmi_reg regs[MSM8974_HDMI_NUM_REGS]; +}; + +static u32 msm8974_hdmi_pll_read(struct msm8974_hdmi *hdmi, u32 reg) +{ + return msm_readl(hdmi->mmio + reg); +} + +static void msm8974_hdmi_pll_write(struct msm8974_hdmi *hdmi, u32 reg, u32 data) +{ + msm_writel(data, hdmi->mmio + reg); +} + +static u32 msm8974_hdmi_phy_read(struct msm8974_hdmi *hdmi, u32 reg) +{ + struct hdmi_phy *phy = platform_get_drvdata(hdmi->pdev); + + return hdmi_phy_read(phy, reg); +} + +static void msm8974_hdmi_phy_write(struct msm8974_hdmi *hdmi, u32 reg, u32 data) +{ + struct hdmi_phy *phy = platform_get_drvdata(hdmi->pdev); + + hdmi_phy_write(phy, reg, data); +} + +/* NOTE: keep sorted highest to lowest frequencies */ +static const struct msm8974_hdmi_rate msm8974_hdmi_freqtbl[] = { + { 297000000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x65, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0xac, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0xcd, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x06, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x03, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + { 268500000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x36, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x61, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0xf6, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0x3e, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x11, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + { 148500000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x52, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0x56, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0xe6, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x02, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + { 108000000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x5B, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0x38, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + /* 720p60/720p50/1080i60/1080i50, 1080p24/1080p30/1080p25 case */ + { 74250000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x52, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0x56, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0xe6, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x02, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + { 65000000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x4f, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x55, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0xed, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0x8A, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x02, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + /* 480p60/480i60 case */ + { 27030000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x54, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x66, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0x1d, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x03, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0x2a, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x03, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + /* 576p50/576i50 case */ + { 27000000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x54, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0x18, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x03, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0x2a, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x03, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + }, + + /* 640x480p60 */ + { 25200000, { + { msm8974_hdmi_phy_write, 0x81, HDMI_PHY_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_REFCLK_CFG }, + { msm8974_hdmi_pll_write, 0x19, HDMI_UNI_PLL_VCOLPF_CFG }, + { msm8974_hdmi_pll_write, 0x0e, HDMI_UNI_PLL_LPFR_CFG }, + { msm8974_hdmi_pll_write, 0x20, HDMI_UNI_PLL_LPFC1_CFG }, + { msm8974_hdmi_pll_write, 0x0d, HDMI_UNI_PLL_LPFC2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG0 }, + { msm8974_hdmi_pll_write, 0x52, HDMI_UNI_PLL_SDM_CFG1 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG2 }, + { msm8974_hdmi_pll_write, 0xb0, HDMI_UNI_PLL_SDM_CFG3 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_SDM_CFG4 }, + { msm8974_hdmi_pll_write, 0x10, HDMI_UNI_PLL_LKDET_CFG0 }, + { msm8974_hdmi_pll_write, 0x1a, HDMI_UNI_PLL_LKDET_CFG1 }, + { msm8974_hdmi_pll_write, 0x05, HDMI_UNI_PLL_LKDET_CFG2 }, + { msm8974_hdmi_pll_write, 0x03, HDMI_UNI_PLL_POSTDIV1_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV2_CFG }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_POSTDIV3_CFG }, + { msm8974_hdmi_pll_write, 0x01, HDMI_UNI_PLL_CAL_CFG2 }, + { msm8974_hdmi_pll_write, 0x60, HDMI_UNI_PLL_CAL_CFG8 }, + { msm8974_hdmi_pll_write, 0x00, HDMI_UNI_PLL_CAL_CFG9 }, + { msm8974_hdmi_pll_write, 0xf4, HDMI_UNI_PLL_CAL_CFG10 }, + { msm8974_hdmi_pll_write, 0x02, HDMI_UNI_PLL_CAL_CFG11 }, + { msm8974_hdmi_phy_write, 0x1f, HDMI_PHY_PD_CTRL0 }, + { msm8974_hdmi_pll_write, 0x0f, HDMI_UNI_PLL_GLB_CFG }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_PD_CTRL1 }, + { msm8974_hdmi_phy_write, 0x10, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0xdb, HDMI_PHY_ANA_CFG0 }, + { msm8974_hdmi_phy_write, 0x43, HDMI_PHY_ANA_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_ANA_CFG2 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_ANA_CFG3 }, + { msm8974_hdmi_pll_write, 0x04, HDMI_UNI_PLL_VREG_CFG }, + { msm8974_hdmi_phy_write, 0xd0, HDMI_PHY_DCC_CFG0 }, + { msm8974_hdmi_phy_write, 0x1a, HDMI_PHY_DCC_CFG1 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG0 }, + { msm8974_hdmi_phy_write, 0x00, HDMI_PHY_TXCAL_CFG1 }, + { msm8974_hdmi_phy_write, 0x02, HDMI_PHY_TXCAL_CFG2 }, + { msm8974_hdmi_phy_write, 0x05, HDMI_PHY_TXCAL_CFG3 } + } + } +}; + +static void msm8974_hdmi_disable(struct clk_hw *hw) +{ + struct msm8974_hdmi *hdmi = hw_clk_to_msm8974_hdmi(hw); + + msm8974_hdmi_pll_write(hdmi, HDMI_UNI_PLL_GLB_CFG, 0); + udelay(5); + msm8974_hdmi_phy_write(hdmi, HDMI_PHY_GLB_CFG, 0); +} + +static int msm8974_hdmi_wait_for_ready(struct msm8974_hdmi *hdmi, + u32 (*read)(struct msm8974_hdmi *hdmi, + u32 reg), + u32 reg) +{ + int retry; + u32 val; + + for (retry = 20; retry > 0; retry--) { + val = read(hdmi, reg); + if (val & BIT(0)) + return 0; + + udelay(100); + } + + return -EINVAL; +} + +static int msm8974_hdmi_enable(struct clk_hw *hw) +{ + struct msm8974_hdmi *hdmi = hw_clk_to_msm8974_hdmi(hw); + int ret; + + /* Global enable */ + msm8974_hdmi_phy_write(hdmi, HDMI_PHY_GLB_CFG, 0x81); + + /* Power up power gen */ + msm8974_hdmi_phy_write(hdmi, HDMI_PHY_PD_CTRL0, 0x00); + udelay(350); + + /* PLL power up */ + msm8974_hdmi_pll_write(hdmi, HDMI_UNI_PLL_GLB_CFG, 0x01); + udelay(5); + + /* Power up PLL LDO */ + msm8974_hdmi_pll_write(hdmi, HDMI_UNI_PLL_GLB_CFG, 0x03); + udelay(350); + + /* PLL power up */ + msm8974_hdmi_pll_write(hdmi, HDMI_UNI_PLL_GLB_CFG, 0x0f); + udelay(350); + + /* Poll for PLL ready status */ + ret = msm8974_hdmi_wait_for_ready(hdmi, msm8974_hdmi_pll_read, + HDMI_UNI_PLL_STATUS); + if (ret) + goto error; + + udelay(350); + + /* Poll for PHY ready status */ + ret = msm8974_hdmi_wait_for_ready(hdmi, msm8974_hdmi_phy_read, + HDMI_PHY_STATUS); + if (ret) + goto error; + + return 0; + +error: + msm8974_hdmi_disable(hw); + return ret; +} + +static const struct msm8974_hdmi_rate *msm8974_hdmi_find_rate(unsigned long rt) +{ + int i; + + for (i = 1; i < ARRAY_SIZE(msm8974_hdmi_freqtbl); i++) { + if (rt > msm8974_hdmi_freqtbl[i].rate) + return &msm8974_hdmi_freqtbl[i - 1]; + } + + return &msm8974_hdmi_freqtbl[i - 1]; +} + +static unsigned long msm8974_hdmi_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return hw_clk_to_msm8974_hdmi(hw)->pixclk; +} + +static long msm8974_hdmi_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return msm8974_hdmi_find_rate(rate)->rate; +} + +static int msm8974_hdmi_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm8974_hdmi *hdmi = hw_clk_to_msm8974_hdmi(hw); + const struct msm8974_hdmi_rate *rateinfo = msm8974_hdmi_find_rate(rate); + int i; + + for (i = 0; i < MSM8974_HDMI_NUM_REGS; i++) { + struct msm8974_hdmi_reg reginfo = rateinfo->regs[i]; + + reginfo.write(hdmi, reginfo.reg, reginfo.val); + + if (reginfo.reg == HDMI_PHY_PD_CTRL0) + udelay(50); + else if (reginfo.reg == HDMI_PHY_TXCAL_CFG3) + udelay(200); + } + + hdmi->pixclk = rate; + + return 0; +} + +static const struct clk_ops msm8974_hdmi_ops = { + .enable = msm8974_hdmi_enable, + .disable = msm8974_hdmi_disable, + .recalc_rate = msm8974_hdmi_recalc_rate, + .round_rate = msm8974_hdmi_round_rate, + .set_rate = msm8974_hdmi_set_rate, +}; + +static const char * const msm8974_hdmi_pll_parents[] = { + "pxo", +}; + +static struct clk_init_data msm8974_hdmi_pll_init = { + .name = "hdmi_pll", + .ops = &msm8974_hdmi_ops, + .parent_names = msm8974_hdmi_pll_parents, + .num_parents = ARRAY_SIZE(msm8974_hdmi_pll_parents), + .flags = CLK_IGNORE_UNUSED, +}; + +int msm_hdmi_pll_8974_init(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct msm8974_hdmi *hdmi; + struct clk *clk; + int i; + + /* sanity check */ + for (i = 0; i < (ARRAY_SIZE(msm8974_hdmi_freqtbl) - 1); i++) { + if (WARN_ON(msm8974_hdmi_freqtbl[i].rate < + msm8974_hdmi_freqtbl[i + 1].rate)) + return -EINVAL; + } + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + hdmi->mmio = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL"); + if (IS_ERR(hdmi->mmio)) { + DRM_DEV_ERROR(dev, "failed to map pll base\n"); + return -ENOMEM; + } + + hdmi->pdev = pdev; + hdmi->clk_hw.init = &msm8974_hdmi_pll_init; + + clk = devm_clk_register(dev, &hdmi->clk_hw); + if (IS_ERR(clk)) { + DRM_DEV_ERROR(dev, "failed to register pll clock\n"); + return -EINVAL; + } + + return 0; +}
pm8941 is missing the 5vs2 regulator node so let's add it since its needed to get the external display working. This regulator was already configured in the interrupts property on the parent node.
Note that this regulator is referred to as mvs2 in the downstream MSM kernel sources.
Signed-off-by: Brian Masney masneyb@onstation.org Reviewed-by: Linus Walleij linus.walleij@linaro.org --- Changes since v1: - None
arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index f198480c8ef4..c1f2012d1c8b 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -178,6 +178,16 @@ qcom,vs-soft-start-strength = <0>; regulator-initial-mode = <1>; }; + + pm8941_5vs2: 5vs2 { + regulator-enable-ramp-delay = <1000>; + regulator-pull-down; + regulator-over-current-protection; + qcom,ocp-max-retries = <10>; + qcom,ocp-retry-delay = <30>; + qcom,vs-soft-start-strength = <0>; + regulator-initial-mode = <1>; + }; }; }; };
On Sun 06 Oct 18:45 PDT 2019, Brian Masney wrote:
pm8941 is missing the 5vs2 regulator node so let's add it since its needed to get the external display working. This regulator was already configured in the interrupts property on the parent node.
Note that this regulator is referred to as mvs2 in the downstream MSM kernel sources.
Signed-off-by: Brian Masney masneyb@onstation.org Reviewed-by: Linus Walleij linus.walleij@linaro.org
Picked this patch for now, once the driver updates are landed I will take the last two dts patches.
Regards, Bjorn
Changes since v1:
- None
arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index f198480c8ef4..c1f2012d1c8b 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -178,6 +178,16 @@ qcom,vs-soft-start-strength = <0>; regulator-initial-mode = <1>; };
pm8941_5vs2: 5vs2 {regulator-enable-ramp-delay = <1000>;regulator-pull-down;regulator-over-current-protection;qcom,ocp-max-retries = <10>;qcom,ocp-retry-delay = <30>;qcom,vs-soft-start-strength = <0>;regulator-initial-mode = <1>;};};
2.21.0
Add HDMI tx and phy nodes to support an external display that can be connected over the SlimPort. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney masneyb@onstation.org Reviewed-by: Linus Walleij linus.walleij@linaro.org --- Changes since v1: - Add hdmi_pll to hdmi-phy node - add power-domain to hdmi-phy per binding specification - Remove FIXME comment regarding the hpd-gdsc-supply. I saw a recent post on linux-arm-msm that this is present for running the upstream MSM display driver on the downstream kernel.
arch/arm/boot/dts/qcom-msm8974.dtsi | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7fc23e422cc5..af02eace14e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1258,6 +1258,13 @@
port@0 { reg = <0>; + mdp5_intf3_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + + port@1 { + reg = <1>; mdp5_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; @@ -1335,6 +1342,77 @@ clocks = <&mmcc MDSS_AHB_CLK>; clock-names = "iface"; }; + + hdmi: hdmi-tx@fd922100 { + status = "disabled"; + + compatible = "qcom,hdmi-tx-8974"; + reg = <0xfd922100 0x35c>, + <0xfc4b8000 0x60f0>; + reg-names = "core_physical", + "qfprom_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; + + hpd-5v-supply = <&pm8941_5vs2>; + core-vdda-supply = <&pm8941_l12>; + core-vcc-supply = <&pm8941_s3>; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@fd922500 { + status = "disabled"; + + compatible = "qcom,hdmi-phy-8974"; + reg = <0xfd922500 0x7c>, + <0xfd922700 0xd4>; + reg-names = "hdmi_phy", + "hdmi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>; + clock-names = "iface", + "alt_iface"; + + core-vdda-supply = <&pm8941_l12>; + vddio-supply = <&pm8941_s3>; + + power-domains = <&mmcc MDSS_GDSC>; + + #phy-cells = <0>; + }; }; };
Quoting Brian Masney (2019-10-06 18:45:08)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7fc23e422cc5..af02eace14e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1335,6 +1342,77 @@ clocks = <&mmcc MDSS_AHB_CLK>; clock-names = "iface"; };
hdmi: hdmi-tx@fd922100 {status = "disabled";compatible = "qcom,hdmi-tx-8974";reg = <0xfd922100 0x35c>,<0xfc4b8000 0x60f0>;reg-names = "core_physical","qfprom_physical";
Is this the qfprom "uncorrected" physical address? If so, why can't this node use an nvmem to read whatever it needs out of the qfprom?
interrupt-parent = <&mdss>;interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&mmcc MDSS_GDSC>;
On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote:
Quoting Brian Masney (2019-10-06 18:45:08)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7fc23e422cc5..af02eace14e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1335,6 +1342,77 @@ clocks = <&mmcc MDSS_AHB_CLK>; clock-names = "iface"; };
hdmi: hdmi-tx@fd922100 {status = "disabled";compatible = "qcom,hdmi-tx-8974";reg = <0xfd922100 0x35c>,<0xfc4b8000 0x60f0>;reg-names = "core_physical","qfprom_physical";Is this the qfprom "uncorrected" physical address? If so, why can't this node use an nvmem to read whatever it needs out of the qfprom?
The MSM HDMI code is configured to look for this reg-name here:
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/msm/hdmi/hdmi...
There is a qcom,qfprom configured for this board in DTS, however its at a different address range, so maybe there are multiple qfproms?
https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/qcom-msm897...
msm8996.dtsi has the same style of configuration:
https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8... https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8...
Brian
Quoting Brian Masney (2019-10-08 23:05:20)
On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote:
Quoting Brian Masney (2019-10-06 18:45:08)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7fc23e422cc5..af02eace14e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1335,6 +1342,77 @@ clocks = <&mmcc MDSS_AHB_CLK>; clock-names = "iface"; };
hdmi: hdmi-tx@fd922100 {status = "disabled";compatible = "qcom,hdmi-tx-8974";reg = <0xfd922100 0x35c>,<0xfc4b8000 0x60f0>;reg-names = "core_physical","qfprom_physical";Is this the qfprom "uncorrected" physical address? If so, why can't this node use an nvmem to read whatever it needs out of the qfprom?
The MSM HDMI code is configured to look for this reg-name here:
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/msm/hdmi/hdmi...
There is a qcom,qfprom configured for this board in DTS, however its at a different address range, so maybe there are multiple qfproms?
https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/qcom-msm897...
msm8996.dtsi has the same style of configuration:
https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8... https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8...
There's only one qfprom and there's the address space that's "uncorrected" which is not supposed to be used and there's the space that is "corrected" and is supposed to be used. It looks like this is poking the uncorrected space and it should probably stop doing that and use the nvmem provider instead. Maybe someone with docs for this chip and 8996 can help confirm this.
On Wed, Oct 09, 2019 at 08:39:26AM -0700, Stephen Boyd wrote:
Quoting Brian Masney (2019-10-08 23:05:20)
On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote:
Quoting Brian Masney (2019-10-06 18:45:08)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7fc23e422cc5..af02eace14e2 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1335,6 +1342,77 @@ clocks = <&mmcc MDSS_AHB_CLK>; clock-names = "iface"; };
hdmi: hdmi-tx@fd922100 {status = "disabled";compatible = "qcom,hdmi-tx-8974";reg = <0xfd922100 0x35c>,<0xfc4b8000 0x60f0>;reg-names = "core_physical","qfprom_physical";Is this the qfprom "uncorrected" physical address? If so, why can't this node use an nvmem to read whatever it needs out of the qfprom?
The MSM HDMI code is configured to look for this reg-name here:
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/msm/hdmi/hdmi...
There is a qcom,qfprom configured for this board in DTS, however its at a different address range, so maybe there are multiple qfproms?
https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/qcom-msm897...
msm8996.dtsi has the same style of configuration:
https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8... https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/msm8...
There's only one qfprom and there's the address space that's "uncorrected" which is not supposed to be used and there's the space that is "corrected" and is supposed to be used. It looks like this is poking the uncorrected space and it should probably stop doing that and use the nvmem provider instead. Maybe someone with docs for this chip and 8996 can help confirm this.
Do you know of any publicly-available documentation that describes the "uncorrected" and "corrected" addresses? I got that qfprom address for the HDMI from here:
https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/arch/arm/boot/dts/ms...
I assume the downstream kernel probably doesn't have the corrected address anywhere else?
Brian
Add HDMI nodes and other supporting infrastructure in order to support the external display. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney masneyb@onstation.org Reviewed-by: Linus Walleij linus.walleij@linaro.org --- Changes since v1: - Regulators always on as a temporary haack. - Hot plug detect pin for the HDMI bridge needs to be low.
.../qcom-msm8974-lge-nexus5-hammerhead.dts | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index b607c9ff9e12..380a805cd1f0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -235,6 +235,36 @@ pinctrl-names = "default"; pinctrl-0 = <&wlan_regulator_pin>; }; + + anx_avdd33: avdd33 { + compatible = "regulator-fixed"; + + regulator-name = "avdd-3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; // FIXME + + gpio = <&pm8941_gpios 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&anx_avdd33_pin>; + }; + + anx_vdd10: vdd10 { + compatible = "regulator-fixed"; + + regulator-name = "vdd-1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; // FIXME + + gpio = <&pm8941_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&anx_vdd10_pin>; + }; };
&soc { @@ -371,6 +401,40 @@ function = "gpio"; }; }; + + hdmi_pin: hdmi { + cec { + pins = "gpio31"; + function = "hdmi_cec"; + }; + + ddc { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + }; + + hpd { + pins = "gpio34"; + function = "hdmi_hpd"; + }; + }; + + anx_msm_pin: anx { + irq { + pins = "gpio28"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + input-enable; + }; + + reset { + pins = "gpio68"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + }; };
vibrator@fd8c3450 { @@ -471,6 +535,28 @@ default-brightness = <200>; }; }; + + anx7808@72 { + compatible = "analogix,anx7808"; + reg = <0x72>; + interrupts-extended = <&msmgpio 28 IRQ_TYPE_EDGE_RISING>; + + hpd-gpios = <&pm8941_gpios 13 GPIO_ACTIVE_LOW>; + pd-gpios = <&pm8941_gpios 14 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 68 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&anx_msm_pin>, <&anx_pin>; + + dvdd10-supply = <&anx_vdd10>; + avdd33-supply = <&anx_avdd33>; + + port { + anx7808_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; };
i2c@f9968000 { @@ -664,6 +750,29 @@
vddio-supply = <&pm8941_l12>; }; + + hdmi-tx@fd922100 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + + qcom,hdmi-tx-ddc-clk = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-ddc-data = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-hpd = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + + ports { + port@1 { + hdmi_out: endpoint { + remote-endpoint = <&anx7808_in>; + }; + }; + }; + }; + + hdmi-phy@fd922500 { + status = "ok"; + }; }; };
@@ -700,6 +809,39 @@ output-high; line-name = "otg-gpio"; }; + + anx_pin: anx { + cbldet { + pins = "gpio13"; + function = "normal"; + input-enable; + bias-pull-down; + power-source = <PM8941_GPIO_S3>; + }; + + pd { + pins = "gpio14"; + function = "normal"; + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; + }; + + anx_avdd33_pin: anxvdd3 { + pins = "gpio26"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; + + anx_vdd10_pin: anxvdd1 { + pins = "gpio8"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; }; }; };
Quoting Brian Masney (2019-10-06 18:45:09)
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index b607c9ff9e12..380a805cd1f0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -371,6 +401,40 @@ function = "gpio"; }; };
hdmi_pin: hdmi {cec {pins = "gpio31";function = "hdmi_cec";};ddc {pins = "gpio32", "gpio33";function = "hdmi_ddc";};hpd {pins = "gpio34";function = "hdmi_hpd";};};anx_msm_pin: anx {irq {pins = "gpio28";function = "gpio";
Is function = "gpio" necessary anymore? I thought we would turn gpios into gpio function when it's requested as a gpio by some consumer.
drive-strength = <8>;bias-pull-up;input-enable;};reset {pins = "gpio68";function = "gpio";drive-strength = <8>;bias-pull-up;};}; }; vibrator@fd8c3450 {
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