DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent fparent@baylibre.com --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b923991..caf4c88708f4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -57,6 +57,9 @@ properties: Output port node. This port should be connected to the input port of an attached HDMI or LVDS encoder chip.
+ power-domains: + maxItems: 1 + required: - compatible - reg @@ -64,6 +67,7 @@ required: - clocks - clock-names - port + - power-domains
additionalProperties: false
@@ -71,11 +75,13 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/power/mt8183-power.h>
dpi0: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>;
DPI for MT8365 is compatible with MT8192 but requires an additional clock. Modify the documentation to requires this clock only on MT8365 SoCs.
Signed-off-by: Fabien Parent fparent@baylibre.com --- .../display/mediatek/mediatek,dpi.yaml | 44 ++++++++++++++++--- 1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index caf4c88708f4..c9c9f4d5ebe7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -17,13 +17,18 @@ description: |
properties: compatible: - enum: - - mediatek,mt2701-dpi - - mediatek,mt7623-dpi - - mediatek,mt8173-dpi - - mediatek,mt8183-dpi - - mediatek,mt8186-dpi - - mediatek,mt8192-dpi + oneOf: + - enum: + - mediatek,mt2701-dpi + - mediatek,mt7623-dpi + - mediatek,mt8173-dpi + - mediatek,mt8183-dpi + - mediatek,mt8186-dpi + - mediatek,mt8192-dpi + - items: + - enum: + - mediatek,mt8365-dpi + - const: mediatek,mt8192-dpi
reg: maxItems: 1 @@ -32,16 +37,20 @@ properties: maxItems: 1
clocks: + minItems: 3 items: - description: Pixel Clock - description: Engine Clock - description: DPI PLL + - description: DPI Clock
clock-names: + minItems: 3 items: - const: pixel - const: engine - const: pll + - const: dpi
pinctrl-0: true pinctrl-1: true @@ -71,6 +80,27 @@ required:
additionalProperties: false
+allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-dpi + + then: + properties: + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h>
On 30/05/2022 22:14, Fabien Parent wrote:
DPI for MT8365 is compatible with MT8192 but requires an additional clock. Modify the documentation to requires this clock only on MT8365 SoCs.
Signed-off-by: Fabien Parent fparent@baylibre.com
.../display/mediatek/mediatek,dpi.yaml | 44 ++++++++++++++++--- 1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index caf4c88708f4..c9c9f4d5ebe7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -17,13 +17,18 @@ description: |
properties: compatible:
- enum:
- mediatek,mt2701-dpi- mediatek,mt7623-dpi- mediatek,mt8173-dpi- mediatek,mt8183-dpi- mediatek,mt8186-dpi- mediatek,mt8192-dpi
oneOf:
- enum:- mediatek,mt2701-dpi- mediatek,mt7623-dpi- mediatek,mt8173-dpi- mediatek,mt8183-dpi- mediatek,mt8186-dpi- mediatek,mt8192-dpi- items:- enum:- mediatek,mt8365-dpi- const: mediatek,mt8192-dpireg: maxItems: 1
@@ -32,16 +37,20 @@ properties: maxItems: 1
clocks:
minItems: 3 items:
- description: Pixel Clock
- description: Engine Clock
- description: DPI PLL
- description: DPI Clockclock-names:
minItems: 3 items:
- const: pixel
- const: engine
- const: pll
- const: dpipinctrl-0: true pinctrl-1: true
@@ -71,6 +80,27 @@ required:
additionalProperties: false
+allOf:
- if:
properties:compatible:contains:const: mediatek,mt8365-dpi- then:
properties:clocks:maxItems: 4clock-names:maxItems: 4
These should be minItems instead.
- else:
properties:clocks:maxItems: 3clock-names:maxItems: 3examples:
- | #include <dt-bindings/interrupt-controller/arm-gic.h>
Best regards, Krzysztof
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
DPI for MT8365 is compatible with MT8192 but requires an additional clock. Modify the documentation to requires this clock only on MT8365 SoCs.
Signed-off-by: Fabien Parent fparent@baylibre.com
.../display/mediatek/mediatek,dpi.yaml | 44 ++++++++++++++++-
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l index caf4c88708f4..c9c9f4d5ebe7 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l @@ -17,13 +17,18 @@ description: |
properties: compatible:
- enum:
- mediatek,mt2701-dpi- mediatek,mt7623-dpi- mediatek,mt8173-dpi- mediatek,mt8183-dpi- mediatek,mt8186-dpi- mediatek,mt8192-dpi
oneOf:
- enum:- mediatek,mt2701-dpi- mediatek,mt7623-dpi- mediatek,mt8173-dpi- mediatek,mt8183-dpi- mediatek,mt8186-dpi- mediatek,mt8192-dpi- items:- enum:- mediatek,mt8365-dpi- const: mediatek,mt8192-dpireg: maxItems: 1
@@ -32,16 +37,20 @@ properties: maxItems: 1
clocks:
- minItems: 3 items:
- description: Pixel Clock
- description: Engine Clock
- description: DPI PLL
- description: DPI Clock
Why MT8365 has this additional clock? What is the new hardware block (compared with other SoC) need this clock? Why this is different than other SoC?
Is this case the same as [1]? If so, I think you should not add this clock.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220613064841.104...
Regards, CK
clock-names:
minItems: 3 items:
- const: pixel
- const: engine
- const: pll
- const: dpipinctrl-0: true pinctrl-1: true
@@ -71,6 +80,27 @@ required:
additionalProperties: false
+allOf:
- if:
properties:compatible:contains:const: mediatek,mt8365-dpi- then:
properties:clocks:maxItems: 4clock-names:maxItems: 4- else:
properties:clocks:maxItems: 3clock-names:maxItems: 3examples:
- | #include <dt-bindings/interrupt-controller/arm-gic.h>
Add MT8365 binding documentation for all the display components that are compatible with the compatible string from other SoCs.
Signed-off-by: Fabien Parent fparent@baylibre.com --- .../bindings/display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 1 + .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,dsi.yaml | 17 +++++++++++------ .../display/mediatek/mediatek,gamma.yaml | 1 + .../display/mediatek/mediatek,mutex.yaml | 1 + .../bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../display/mediatek/mediatek,rdma.yaml | 1 + 9 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index d4d585485e7b..d47bc72f09c0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal + - mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aal
reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a56..fc999e614718 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -32,6 +32,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ccorr + - mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorr
reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index d2f89ee7996f..9d081da433e8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt8186-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color + - mediatek,mt8365-disp-color - const: mediatek,mt8173-disp-color reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 8ad8187c02d1..a7706cd65675 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8186-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither + - mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-dither
reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index fa5bdf28668a..d17ea215960c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -22,12 +22,17 @@ allOf:
properties: compatible: - enum: - - mediatek,mt2701-dsi - - mediatek,mt7623-dsi - - mediatek,mt8167-dsi - - mediatek,mt8173-dsi - - mediatek,mt8183-dsi + oneOf: + - enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + - items: + - enum: + - mediatek,mt8365-dsi + - const: mediatek,mt8183-dsi
reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea7542..f54859cfc97b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma + - mediatek,mt8365-disp-gamma - const: mediatek,mt8183-disp-gamma
reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index 3fdad71210b4..f4a12dfae77b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex + - mediatek,mt8365-disp-mutex
reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index a2a27d0ca038..20e4ca4fc915 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -41,6 +41,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ovl + - mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovl
reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index 0882ae86e6c4..3bc914785976 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -40,6 +40,7 @@ properties: - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma + - mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdma
reg:
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Add MT8365 binding documentation for all the display components that are compatible with the compatible string from other SoCs.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Fabien Parent fparent@baylibre.com
.../bindings/display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 1 + .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,dsi.yaml | 17 +++++++++++--
.../display/mediatek/mediatek,gamma.yaml | 1 + .../display/mediatek/mediatek,mutex.yaml | 1 + .../bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../display/mediatek/mediatek,rdma.yaml | 1 + 9 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam l index d4d585485e7b..d47bc72f09c0 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam l @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal
- mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aalreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y aml index 63fb02014a56..fc999e614718 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.y aml @@ -32,6 +32,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ccorr
- mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorrreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y aml index d2f89ee7996f..9d081da433e8 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y aml @@ -39,6 +39,7 @@ properties: - mediatek,mt8186-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color
- mediatek,mt8365-disp-color - const: mediatek,mt8173-disp-colordiff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. yaml index 8ad8187c02d1..a7706cd65675 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither. yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8186-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither
- mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-ditherreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l index fa5bdf28668a..d17ea215960c 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam l @@ -22,12 +22,17 @@ allOf:
properties: compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi
oneOf:
- enum:- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- items:- enum:- mediatek,mt8365-dsi- const: mediatek,mt8183-dsireg: maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y aml index a89ea0ea7542..f54859cfc97b 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y aml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma
- mediatek,mt8365-disp-gamma - const: mediatek,mt8183-disp-gammareg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.y aml index 3fdad71210b4..f4a12dfae77b 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.y aml @@ -32,6 +32,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex
- mediatek,mt8365-disp-mutexreg: maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam l index a2a27d0ca038..20e4ca4fc915 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam l @@ -41,6 +41,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ovl
- mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovlreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya ml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya ml index 0882ae86e6c4..3bc914785976 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya ml @@ -40,6 +40,7 @@ properties: - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma
- mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdmareg:
On 30/05/2022 22:14, Fabien Parent wrote:
Add MT8365 binding documentation for all the display components that are compatible with the compatible string from other SoCs.
Signed-off-by: Fabien Parent fparent@baylibre.com
Reviewed-by: Matthias Brugger matthias.bgg@gmail.com
.../bindings/display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 1 + .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,dsi.yaml | 17 +++++++++++------ .../display/mediatek/mediatek,gamma.yaml | 1 + .../display/mediatek/mediatek,mutex.yaml | 1 + .../bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../display/mediatek/mediatek,rdma.yaml | 1 + 9 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index d4d585485e7b..d47bc72f09c0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal
- mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aalreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a56..fc999e614718 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -32,6 +32,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ccorr
- mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorrreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index d2f89ee7996f..9d081da433e8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt8186-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color
- mediatek,mt8365-disp-color - const: mediatek,mt8173-disp-colordiff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 8ad8187c02d1..a7706cd65675 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8186-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither
- mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-ditherreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index fa5bdf28668a..d17ea215960c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -22,12 +22,17 @@ allOf:
properties: compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi
oneOf:
- enum:- mediatek,mt2701-dsi- mediatek,mt7623-dsi- mediatek,mt8167-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- items:- enum:- mediatek,mt8365-dsi- const: mediatek,mt8183-dsireg: maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea7542..f54859cfc97b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8186-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma
- mediatek,mt8365-disp-gamma - const: mediatek,mt8183-disp-gammareg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml index 3fdad71210b4..f4a12dfae77b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex
- mediatek,mt8365-disp-mutexreg: maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index a2a27d0ca038..20e4ca4fc915 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -41,6 +41,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ovl
- mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovlreg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index 0882ae86e6c4..3bc914785976 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -40,6 +40,7 @@ properties: - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma
- mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdmareg:
Add mutex support for MT8365 SoC.
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/soc/mediatek/mtk-mutex.c | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 981d56967e7a..b8d5c4a62542 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -110,6 +110,20 @@ #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 #define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8365_MUTEX_MOD_DISP_OVL0 7 +#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 +#define MT8365_MUTEX_MOD_DISP_RDMA0 9 +#define MT8365_MUTEX_MOD_DISP_RDMA1 10 +#define MT8365_MUTEX_MOD_DISP_WDMA0 11 +#define MT8365_MUTEX_MOD_DISP_COLOR0 12 +#define MT8365_MUTEX_MOD_DISP_CCORR 13 +#define MT8365_MUTEX_MOD_DISP_AAL 14 +#define MT8365_MUTEX_MOD_DISP_GAMMA 15 +#define MT8365_MUTEX_MOD_DISP_DITHER 16 +#define MT8365_MUTEX_MOD_DISP_DSI0 17 +#define MT8365_MUTEX_MOD_DISP_PWM0 20 +#define MT8365_MUTEX_MOD_DISP_DPI0 22 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -315,6 +329,22 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, };
+static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, + [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8365_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0, + [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -423,6 +453,14 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, };
+static const struct mtk_mutex_data mt8365_mutex_driver_data = { + .mutex_mod = mt8365_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, + .no_clk = true, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -665,6 +703,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8192_mutex_driver_data}, { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data}, + { .compatible = "mediatek,mt8365-disp-mutex", + .data = &mt8365_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Add mutex support for MT8365 SoC.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/soc/mediatek/mtk-mutex.c | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 981d56967e7a..b8d5c4a62542 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -110,6 +110,20 @@ #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 #define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8365_MUTEX_MOD_DISP_OVL0 7 +#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 +#define MT8365_MUTEX_MOD_DISP_RDMA0 9 +#define MT8365_MUTEX_MOD_DISP_RDMA1 10 +#define MT8365_MUTEX_MOD_DISP_WDMA0 11 +#define MT8365_MUTEX_MOD_DISP_COLOR0 12 +#define MT8365_MUTEX_MOD_DISP_CCORR 13 +#define MT8365_MUTEX_MOD_DISP_AAL 14 +#define MT8365_MUTEX_MOD_DISP_GAMMA 15 +#define MT8365_MUTEX_MOD_DISP_DITHER 16 +#define MT8365_MUTEX_MOD_DISP_DSI0 17 +#define MT8365_MUTEX_MOD_DISP_PWM0 20 +#define MT8365_MUTEX_MOD_DISP_DPI0 22
#define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -315,6 +329,22 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, };
+static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
- [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
- [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8365_MUTEX_MOD_DISP_DITHER,
- [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
- [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
- [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
- [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
- [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
- [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
+};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -423,6 +453,14 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, };
+static const struct mtk_mutex_data mt8365_mutex_driver_data = {
- .mutex_mod = mt8365_mutex_mod,
- .mutex_sof = mt8183_mutex_sof,
- .mutex_mod_reg = MT8183_MUTEX0_MOD0,
- .mutex_sof_reg = MT8183_MUTEX0_SOF0,
- .no_clk = true,
+};
struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -665,6 +703,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8192_mutex_driver_data}, { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data},
- { .compatible = "mediatek,mt8365-disp-mutex",
.data = &mt8365_mutex_driver_data},}; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
On 17/06/2022 07:50, CK Hu wrote:
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Add mutex support for MT8365 SoC.
Reviewed-by: CK Hu ck.hu@mediatek.com
Applied thanks!
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/soc/mediatek/mtk-mutex.c | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 981d56967e7a..b8d5c4a62542 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -110,6 +110,20 @@ #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 #define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8365_MUTEX_MOD_DISP_OVL0 7 +#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 +#define MT8365_MUTEX_MOD_DISP_RDMA0 9 +#define MT8365_MUTEX_MOD_DISP_RDMA1 10 +#define MT8365_MUTEX_MOD_DISP_WDMA0 11 +#define MT8365_MUTEX_MOD_DISP_COLOR0 12 +#define MT8365_MUTEX_MOD_DISP_CCORR 13 +#define MT8365_MUTEX_MOD_DISP_AAL 14 +#define MT8365_MUTEX_MOD_DISP_GAMMA 15 +#define MT8365_MUTEX_MOD_DISP_DITHER 16 +#define MT8365_MUTEX_MOD_DISP_DSI0 17 +#define MT8365_MUTEX_MOD_DISP_PWM0 20 +#define MT8365_MUTEX_MOD_DISP_DPI0 22
- #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -315,6 +329,22 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, };
+static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
- [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
- [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8365_MUTEX_MOD_DISP_DITHER,
- [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
- [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
- [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
- [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
- [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
- [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
+};
- static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -423,6 +453,14 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, };
+static const struct mtk_mutex_data mt8365_mutex_driver_data = {
- .mutex_mod = mt8365_mutex_mod,
- .mutex_sof = mt8183_mutex_sof,
- .mutex_mod_reg = MT8183_MUTEX0_MOD0,
- .mutex_sof_reg = MT8183_MUTEX0_SOF0,
- .no_clk = true,
+};
- struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -665,6 +703,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8192_mutex_driver_data}, { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data},
- { .compatible = "mediatek,mt8365-disp-mutex",
.data = &mt8365_mutex_driver_data},
Right now only the DSI path connections are described in the mt8365 mmsys driver. The external path will be DPI/HDMI. This commit adds the connections for DPI/HDMI.
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h index 24129a6c25f8..7abaf048d91e 100644 --- a/drivers/soc/mediatek/mt8365-mmsys.h +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -10,6 +10,9 @@ #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0 +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8 +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
#define MT8365_RDMA0_SOUT_COLOR0 0x1 #define MT8365_DITHER_MOUT_EN_DSI0 0x1 @@ -18,6 +21,10 @@ #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) +#define MT8365_RDMA1_SOUT_DPI0 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0 +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { { @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00, + MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, + MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1 + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL, + MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0 + }, };
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Right now only the DSI path connections are described in the mt8365 mmsys driver. The external path will be DPI/HDMI. This commit adds the connections for DPI/HDMI.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h index 24129a6c25f8..7abaf048d91e 100644 --- a/drivers/soc/mediatek/mt8365-mmsys.h +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -10,6 +10,9 @@ #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0 +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8 +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
#define MT8365_RDMA0_SOUT_COLOR0 0x1 #define MT8365_DITHER_MOUT_EN_DSI0 0x1 @@ -18,6 +21,10 @@ #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) +#define MT8365_RDMA1_SOUT_DPI0 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0 +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { { @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 },
- {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
- },
- {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1- },
- {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0- },
};
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
On 17/06/2022 07:53, CK Hu wrote:
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Right now only the DSI path connections are described in the mt8365 mmsys driver. The external path will be DPI/HDMI. This commit adds the connections for DPI/HDMI.
Reviewed-by: CK Hu ck.hu@mediatek.com
Applied, thanks!
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/soc/mediatek/mt8365-mmsys.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h index 24129a6c25f8..7abaf048d91e 100644 --- a/drivers/soc/mediatek/mt8365-mmsys.h +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -10,6 +10,9 @@ #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 +#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL 0xfd0 +#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0xfd8 +#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
#define MT8365_RDMA0_SOUT_COLOR0 0x1 #define MT8365_DITHER_MOUT_EN_DSI0 0x1 @@ -18,6 +21,10 @@ #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 #define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 #define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) +#define MT8365_RDMA1_SOUT_DPI0 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0 +#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK 0x1 +#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { { @@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 },
- {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1},
{
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0}, };
#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
MT8365 requires an additional clock for DPI. Add support for that additional clock.
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e61cd67b978f..7872db60840e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -72,6 +72,7 @@ struct mtk_dpi { struct device *dev; struct clk *engine_clk; struct clk *pixel_clk; + struct clk *dpi_clk; struct clk *tvd_clk; int irq; struct drm_display_mode mode; @@ -412,6 +413,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_clk); }
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -421,10 +423,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
+ ret = clk_prepare_enable(dpi->dpi_clk); + if (ret) { + dev_err(dpi->dev, "failed to enable dpi clock: %d\n", ret); + goto err_refcount; + } + ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; }
ret = clk_prepare_enable(dpi->pixel_clk); @@ -441,6 +449,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->dpi_clk); err_refcount: dpi->refcount--; return ret; @@ -893,6 +903,12 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; }
+ dpi->dpi_clk = devm_clk_get_optional(dev, "dpi"); + if (IS_ERR(dpi->dpi_clk)) { + return dev_err_probe(dev, ret, "Failed to get dpi clock: %pe\n", + dpi->dpi_clk); + } + dpi->irq = platform_get_irq(pdev, 0); if (dpi->irq <= 0) return -EINVAL;
Add DRM support for MT8365 SoC.
Signed-off-by: Fabien Parent fparent@baylibre.com --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6abe6bcacbdc..0a30ec75b1e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -195,6 +195,22 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt8365_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8365_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -253,6 +269,13 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), };
+static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { + .main_path = mt8365_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main), + .ext_path = mt8365_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -490,6 +513,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8192-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8365-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", @@ -564,6 +589,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data}, + { .compatible = "mediatek,mt8365-mmsys", + .data = &mt8365_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
Add DRM support for MT8365 SoC.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Fabien Parent fparent@baylibre.com
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6abe6bcacbdc..0a30ec75b1e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -195,6 +195,22 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt8365_mtk_ddp_main[] = {
- DDP_COMPONENT_OVL0,
- DDP_COMPONENT_RDMA0,
- DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_CCORR,
- DDP_COMPONENT_AAL0,
- DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DSI0,
+};
+static const enum mtk_ddp_comp_id mt8365_mtk_ddp_ext[] = {
- DDP_COMPONENT_RDMA1,
- DDP_COMPONENT_DPI0,
+};
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -253,6 +269,13 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), };
+static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
- .main_path = mt8365_mtk_ddp_main,
- .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main),
- .ext_path = mt8365_mtk_ddp_ext,
- .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext),
+};
static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -490,6 +513,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8192-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
- { .compatible = "mediatek,mt8365-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },@@ -564,6 +589,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data},
- { .compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data},}; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
On Mon, 30 May 2022 22:14:30 +0200, Fabien Parent wrote:
DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent fparent@baylibre.com
.../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.example.dts:29.35-36 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hi, Fabien:
On Mon, 2022-05-30 at 22:14 +0200, Fabien Parent wrote:
DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent fparent@baylibre.com
.../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l index 77ee1b923991..caf4c88708f4 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l @@ -57,6 +57,9 @@ properties: Output port node. This port should be connected to the input port of an attached HDMI or LVDS encoder chip.
- power-domains:
- maxItems: 1
required:
- compatible
- reg
@@ -64,6 +67,7 @@ required:
- clocks
- clock-names
- port
- power-domains
additionalProperties: false
@@ -71,11 +75,13 @@ examples:
- | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h>
- #include <dt-bindings/power/mt8183-power.h>
Why do you include mt8183 power header file for mt8173 dpi node?
Regards, CK
dpi0: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>;
dri-devel@lists.freedesktop.org
-
CK Hu -
Fabien Parent -
Krzysztof Kozlowski -
Matthias Brugger -
Rob Herring