On 2 March 2016 at 04:58, Timothy Pearson tpearson@raptorengineeringinc.com wrote:

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On 02/26/2016 03:29 PM, Timothy Pearson wrote:

...

During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width.

Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05.

Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com

drivers/gpu/drm/ast/ast_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 9759009..b1480ac 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -227,7 +227,7 @@ static int ast_get_dram_info(struct drm_device *dev) } while (ast_read32(ast, 0x10000) != 0x01); data = ast_read32(ast, 0x10004);

• if (data & 0x400)
  

• if (data & 0x40)
          ast->dram_bus_width = 16;
  else
          ast->dram_bus_width = 32;
  

Just wanted to give this a bump since I have not received any feedback on it.

Thanks,

I've confirmed with the userspace AST driver this is correct, I'll put this in drm-fixes now.

Dave.