That new macro is needed by the imx_drm staging driver for supporting the QVGA display of the eukrea-cpuimx51 board.
Signed-off-by: Denis Carikli denis@eukrea.com Acked-by: Mauro Carvalho Chehab m.chehab@samsung.com Acked-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Acked-by: Philipp Zabel p.zabel@pengutronix.de --- ChangeLog v9->v10: - Rebased on top of: "211e7f2 [media] DocBook media: drop the old incorrect packed RGB table" - Added Philipp Zabel's Ack.
ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly.
ChangeLog v7->v8: - Added Mauro Carvalho Chehab back to the list of Cc
ChangeLog v6->v7: - Shrinked even more the Cc list. ChangeLog v5->v6: - Remove people not concerned by this patch from the Cc list.
ChangeLog v3->v4: - Added Laurent Pinchart's Ack.
ChangeLog v2->v3: - Added some interested people in the Cc list. - Added Mauro Carvalho Chehab's Ack. - Added documentation. --- .../DocBook/media/v4l/pixfmt-packed-rgb.xml | 39 ++++++++++++++++++++ include/uapi/linux/videodev2.h | 1 + 2 files changed, 40 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml index e1c4f8b..88a7fe1 100644 --- a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml +++ b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml @@ -279,6 +279,45 @@ colorspace <constant>V4L2_COLORSPACE_SRGB</constant>.</para> <entry></entry> <entry></entry> </row> + <row id="V4L2-PIX-FMT-RGB666"> + <entry><constant>V4L2_PIX_FMT_RGB666</constant></entry> + <entry>'RGBH'</entry> + <entry></entry> + <entry>r<subscript>5</subscript></entry> + <entry>r<subscript>4</subscript></entry> + <entry>r<subscript>3</subscript></entry> + <entry>r<subscript>2</subscript></entry> + <entry>r<subscript>1</subscript></entry> + <entry>r<subscript>0</subscript></entry> + <entry>g<subscript>5</subscript></entry> + <entry>g<subscript>4</subscript></entry> + <entry></entry> + <entry>g<subscript>3</subscript></entry> + <entry>g<subscript>2</subscript></entry> + <entry>g<subscript>1</subscript></entry> + <entry>g<subscript>0</subscript></entry> + <entry>b<subscript>5</subscript></entry> + <entry>b<subscript>4</subscript></entry> + <entry>b<subscript>3</subscript></entry> + <entry>b<subscript>2</subscript></entry> + <entry></entry> + <entry>b<subscript>1</subscript></entry> + <entry>b<subscript>0</subscript></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + <entry></entry> + </row> <row id="V4L2-PIX-FMT-BGR24"> <entry><constant>V4L2_PIX_FMT_BGR24</constant></entry> <entry>'BGR3'</entry> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 4dc7052..efcbc15 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -299,6 +299,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */ #define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */ #define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */ +#define V4L2_PIX_FMT_RGB666 v4l2_fourcc('R', 'G', 'B', 'H') /* 18 RGB-6-6-6 */ #define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */ #define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */ #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */
Signed-off-by: Denis Carikli denis@eukrea.com Acked-by: Philipp Zabel p.zabel@pengutronix.de --- ChangeLog v8->v9: - Rebased. - Added Philipp Zabel's ack. - Shortened the patch title.
ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly. - Rebased.
ChangeLog v7->v8: - Shrinked even more the Cc list.
ChangeLog v6->v7: - Shrinked even more the Cc list.
ChangeLog v5->v6: - Remove people not concerned by this patch from the Cc list.
ChangeLog v3->v5: - Use the correct RGB order.
ChangeLog v2->v3: - Added some interested people in the Cc list. - Removed the commit message long desciption that was just a copy of the short description. - Rebased the patch. - Fixed a copy-paste error in the ipu_dc_map_clear parameter. --- .../bindings/staging/imx-drm/fsl-imx-drm.txt | 3 ++- drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 9 +++++++++ drivers/staging/imx-drm/parallel-display.c | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt index 3be5ce7..83137ef 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt @@ -60,7 +60,8 @@ Required properties: - compatible: Should be "fsl,imx-parallel-display" Optional properties: - interface_pix_fmt: How this display is connected to the - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" + display interface. Currently supported types: "rgb24", "rgb565", "bgr666", + "rgb666" - edid: verbatim EDID data block describing attached display. - ddc: phandle describing the i2c bus handling the display data channel diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c index d5de8bb..6f9abe8 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c @@ -92,6 +92,7 @@ enum ipu_dc_map { IPU_DC_MAP_GBR24, /* TVEv2 */ IPU_DC_MAP_BGR666, IPU_DC_MAP_BGR24, + IPU_DC_MAP_RGB666, };
struct ipu_dc { @@ -155,6 +156,8 @@ static int ipu_pixfmt_to_map(u32 fmt) return IPU_DC_MAP_BGR666; case V4L2_PIX_FMT_BGR24: return IPU_DC_MAP_BGR24; + case V4L2_PIX_FMT_RGB666: + return IPU_DC_MAP_RGB666; default: return -EINVAL; } @@ -404,6 +407,12 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */ ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
+ /* rgb666 */ + ipu_dc_map_clear(priv, IPU_DC_MAP_RGB666); + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 0, 5, 0xfc); /* blue */ + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 1, 11, 0xfc); /* green */ + ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 2, 17, 0xfc); /* red */ + return 0; }
diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c index c60b6c6..01b7ce5 100644 --- a/drivers/staging/imx-drm/parallel-display.c +++ b/drivers/staging/imx-drm/parallel-display.c @@ -219,6 +219,8 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data) imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565; else if (!strcmp(fmt, "bgr666")) imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666; + else if (!strcmp(fmt, "rgb666")) + imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB666; }
panel_node = of_parse_phandle(np, "fsl,panel", 0);
The current BGR666 is not consistent with the other color mapings like BGR24. BGR666 should be in the same byte order than BGR24.
Signed-off-by: Denis Carikli denis@eukrea.com Acked-by: Philipp Zabel p.zabel@pengutronix.de --- ChangeLog v9->v10: - Rebased. - Added Philipp Zabel's Ack. - Included Lothar Waßmann's suggestion about imx-ldb.c. - Shortened the patch title
ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly.
ChangeLog v7->v8: - Shrinked even more the Cc list.
ChangeLog v6->v7: - Shrinked even more the Cc list.
ChangeLog v5->v6: - Remove people not concerned by this patch from the Cc list. - Added a better explanation of the change.
ChangeLog v5: - New patch. --- arch/arm/boot/dts/imx51-apf51dev.dts | 2 +- arch/arm/boot/dts/imx53-m53evk.dts | 2 +- drivers/staging/imx-drm/imx-ldb.c | 4 ++-- drivers/staging/imx-drm/ipu-v3/ipu-dc.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index c5a9a24..7b3851d 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -18,7 +18,7 @@
display@di1 { compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; + interface-pix-fmt = "rgb666"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp1>;
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index f6d3ac3..4646ea9 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -23,7 +23,7 @@ soc { display1: display@di1 { compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "bgr666"; + interface-pix-fmt = "rgb666"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp1>;
diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c index 33d2b883..e6d7bc7 100644 --- a/drivers/staging/imx-drm/imx-ldb.c +++ b/drivers/staging/imx-drm/imx-ldb.c @@ -185,11 +185,11 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) switch (imx_ldb_ch->chno) { case 0: pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ? - V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; + V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_RGB666; break; case 1: pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ? - V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; + V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_RGB666; break; default: dev_err(ldb->dev, "unable to config di%d panel format\n", diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c index 6f9abe8..154d293 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-dc.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-dc.c @@ -397,9 +397,9 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
/* bgr666 */ ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666); - ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */ + ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 17, 0xfc); /* blue */ ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */ - ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */ + ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 5, 0xfc); /* red */
/* bgr24 */ ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
According to the datasheet, setting the di0_polarity_disp_clk field in the GENERAL di register sets the output clock polarity to active high.
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v9->v10: - New patch that is now needed by the "staging: imx-drm: Use de-active and pixelclk-active" patch. --- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 2 +- drivers/staging/imx-drm/ipuv3-crtc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 82a9eba..849b3e1 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) } }
- if (!sig->clk_pol) + if (sig->clk_pol) di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL); diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index a8d0178..db6bd64 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -158,7 +158,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, sig_cfg.Vsync_pol = 1;
sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 1; + sig_cfg.clk_pol = 0; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt;
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v9->v10: - New patch which was splitted out from: "staging: imx-drm: Use de-active and pixelclk-active display-timings.". - Fixes many issues in "staging: imx-drm: Use de-active and pixelclk-active display-timings.": - More clear meaning of the polarity settings. - The SET_CLK_POL and SET_DE_POL masks are not needed anymore. --- drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 8 +++++++- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 4 ++-- drivers/staging/imx-drm/ipuv3-crtc.c | 4 ++-- 3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h index c4d14ea..b95cba1 100644 --- a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h +++ b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h @@ -27,6 +27,12 @@ enum ipuv3_type {
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
+#define CLK_POL_ACTIVE_LOW 0 +#define CLK_POL_ACTIVE_HIGH 1 + +#define ENABLE_POL_NEGEDGE 0 +#define ENABLE_POL_POSEDGE 1 + /* * Bitfield of Display Interface signal polarities. */ @@ -37,7 +43,7 @@ struct ipu_di_signal_cfg { unsigned clksel_en:1; unsigned clkidle_en:1; unsigned data_pol:1; /* true = inverted */ - unsigned clk_pol:1; /* true = rising edge */ + unsigned clk_pol:1; unsigned enable_pol:1; unsigned Hsync_pol:1; /* true = active high */ unsigned Vsync_pol:1; diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 849b3e1..53646aa 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) } }
- if (sig->clk_pol) + if (sig->clk_pol == CLK_POL_ACTIVE_HIGH) di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL); @@ -606,7 +606,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) reg = ipu_di_read(di, DI_POL); reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
- if (sig->enable_pol) + if (sig->enable_pol == ENABLE_POL_POSEDGE) reg |= DI_POL_DRDY_POLARITY_15; if (sig->data_pol) reg |= DI_POL_DRDY_DATA_POLARITY; diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index db6bd64..8cfeb47 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -157,8 +157,8 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 0; + sig_cfg.enable_pol = ENABLE_POL_POSEDGE; + sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt;
The imx-drm driver can't use the de-active and pixelclk-active display-timings properties yet.
Instead the data-enable and the pixel data clock polarity are hardcoded in the imx-drm driver.
So theses properties are now set to keep the same behaviour when imx-drm will start using them.
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v9->v10: - New patch that was splitted out of: "staging imx-drm: Use de-active and pixelclk-active display-timings." --- arch/arm/boot/dts/imx51-babbage.dts | 2 ++ arch/arm/boot/dts/imx53-m53evk.dts | 2 ++ arch/arm/boot/dts/imx53-tx53-x03x.dts | 2 +- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++ 9 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 9e9deb2..4732a00 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -38,6 +38,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; };
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 4646ea9..d6e1046 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -40,6 +40,8 @@ vfront-porch = <9>; vsync-len = <3>; vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts index 0217dde3..4092a81 100644 --- a/arch/arm/boot/dts/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts @@ -93,7 +93,7 @@ hsync-active = <0>; vsync-active = <0>; de-active = <1>; - pixelclk-active = <1>; + pixelclk-active = <0>; };
ET0500 { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index c8e5ae0..43f48f2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -494,6 +494,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 2795dfc..59ecfd1 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -516,6 +516,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 99be301..e9419a2 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -349,6 +349,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 009abd6..230bbc6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -405,6 +405,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 3bec128..ed4c72f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -349,6 +349,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 7a88d9a..7d1c84c 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -463,6 +463,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; };
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v10->v11: - Since the imx-drm won't be able to retrive its regulators from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace. --- include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6) + struct drm_display_mode { /* Header */ struct list_head head; @@ -183,6 +190,7 @@ struct drm_display_mode { int vrefresh; /* in Hz */ int hsync; /* in kHz */ enum hdmi_picture_aspect picture_aspect_ratio; + unsigned int pol_flags; };
static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
Hi Denis,
Thanks for the patch.
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Regards Andrzej
struct drm_display_mode { /* Header */ struct list_head head; @@ -183,6 +190,7 @@ struct drm_display_mode { int vrefresh; /* in Hz */ int hsync; /* in kHz */ enum hdmi_picture_aspect picture_aspect_ratio;
- unsigned int pol_flags;
};
static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
Hello,
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
struct drm_display_mode { /* Header */ struct list_head head; @@ -183,6 +190,7 @@ struct drm_display_mode { int vrefresh; /* in Hz */ int hsync; /* in kHz */ enum hdmi_picture_aspect picture_aspect_ratio;
- unsigned int pol_flags;
};
static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
Hi,
Laurent Pinchart wrote:
Hello,
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
Lothar Waßmann
Hi Lothar,
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
The DRM_MODE_FLAG_POL_DE_(LOW|HIGH) do, by my impression of the proposed new DRM_MODE_FLAG_POL_DE_*EDGE flags is that they define sampling clock edges, not active levels.
Hi,
Laurent Pinchart wrote:
Hi Lothar,
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
The DRM_MODE_FLAG_POL_DE_(LOW|HIGH) do, by my impression of the proposed new DRM_MODE_FLAG_POL_DE_*EDGE flags is that they define sampling clock edges, not active levels.
The current naming of the flags gives the impression that they describe the sampling edges of a clock signal. But the DE signal in fact is not a clock signal but a level sensitive gating signal.
Lothar Waßmann
On Tue, Mar 18, 2014 at 08:50:30AM +0100, Lothar Waßmann wrote:
Hi,
Laurent Pinchart wrote:
Hi Lothar,
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
The DRM_MODE_FLAG_POL_DE_(LOW|HIGH) do, by my impression of the proposed new DRM_MODE_FLAG_POL_DE_*EDGE flags is that they define sampling clock edges, not active levels.
The current naming of the flags gives the impression that they describe the sampling edges of a clock signal. But the DE signal in fact is not a clock signal but a level sensitive gating signal.
+1
Hi Lothar,
On Tuesday 18 March 2014 08:50:30 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote:
We need a way to pass signal polarity informations between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes, and that I was told that the drm simple-panel driver already supported that, I then, instead, added what was lacking to make the eukrea displays work with the drm-simple-panel driver.
That required a way to get back the display polarity informations from the imx-drm driver without affecting userspace.
include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f764654..61a4fe1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -131,6 +131,13 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
The DRM_MODE_FLAG_POL_DE_(LOW|HIGH) do, by my impression of the proposed new DRM_MODE_FLAG_POL_DE_*EDGE flags is that they define sampling clock edges, not active levels.
The current naming of the flags gives the impression that they describe the sampling edges of a clock signal. But the DE signal in fact is not a clock signal but a level sensitive gating signal.
That's not my point. I *know* that DE is a data gating signal with a polarity already defined by the DRM_MODE_FLAG_POL_DE_(LOW|HIGH) flags. Like all other signals it gets generated on a clock edge and is sampled on a clock edge. The DRM_MODE_FLAG_POL_DE_*EDGE flags proposed above describe seem to describe just that, *not* the signal polarity. I thus want to know whether there are systems where the data signals and the DE signal need to be sampled on different edges of the pixel clock.
On Tue, Mar 18, 2014 at 01:41:54PM +0100, Laurent Pinchart wrote:
Hi Lothar,
That's not my point. I *know* that DE is a data gating signal with a polarity already defined by the DRM_MODE_FLAG_POL_DE_(LOW|HIGH) flags. Like all other signals it gets generated on a clock edge and is sampled on a clock edge. The DRM_MODE_FLAG_POL_DE_*EDGE flags proposed above describe seem to describe just that, *not* the signal polarity. I thus want to know whether there are systems where the data signals and the DE signal need to be sampled on different edges of the pixel clock.
That's not relevant to this patch series though. This patch series is about adding configuration which will allow iMX6 SoCs to be properly configured for their displays.
iMX has the ability to:
- define the polarity of the clock signal - define the polarity of the other signals
It does not have the ability to define which clock edge individual signals like vsync (frame clock), hsync (line clock), disable enable change on independently.
So, it doesn't make sense _here_ for the display enable to be defined by an edge - it's not something that can be changed here. What can only be changed is it's active level.
Of course, there may be some which can do this, and that's a separate problem that would need to be addressed when there's hardware that does support it.
The objection which Lothar is raising is that _this_ definition does not match the _hardware_ capabilities which it is intended to be used with, which is a very valid objection.
Hi Russell,
On Tuesday 18 March 2014 12:56:23 Russell King - ARM Linux wrote:
On Tue, Mar 18, 2014 at 01:41:54PM +0100, Laurent Pinchart wrote:
Hi Lothar,
That's not my point. I *know* that DE is a data gating signal with a polarity already defined by the DRM_MODE_FLAG_POL_DE_(LOW|HIGH) flags. Like all other signals it gets generated on a clock edge and is sampled on a clock edge. The DRM_MODE_FLAG_POL_DE_*EDGE flags proposed above describe seem to describe just that, *not* the signal polarity. I thus want to know whether there are systems where the data signals and the DE signal need to be sampled on different edges of the pixel clock.
That's not relevant to this patch series though. This patch series is about adding configuration which will allow iMX6 SoCs to be properly configured for their displays.
iMX has the ability to:
- define the polarity of the clock signal
- define the polarity of the other signals
It does not have the ability to define which clock edge individual signals like vsync (frame clock), hsync (line clock), disable enable change on independently.
So, it doesn't make sense _here_ for the display enable to be defined by an edge - it's not something that can be changed here. What can only be changed is it's active level.
Of course, there may be some which can do this, and that's a separate problem that would need to be addressed when there's hardware that does support it.
The objection which Lothar is raising is that _this_ definition does not match the _hardware_ capabilities which it is intended to be used with, which is a very valid objection.
Thank you for the clarification. That absolutely makes sense.
Hi,
Laurent Pinchart wrote:
Hi Lothar,
On Tuesday 18 March 2014 08:50:30 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 16:14:36 Lothar Waßmann wrote:
Laurent Pinchart wrote:
On Monday 17 March 2014 14:41:09 Andrzej Hajda wrote:
On 03/13/2014 06:17 PM, Denis Carikli wrote: > We need a way to pass signal polarity informations > between DRM panels, and the display drivers. > > To do that, a pol_flags field was added to drm_display_mode. > > Signed-off-by: Denis Carikli denis@eukrea.com > --- > ChangeLog v10->v11: > - Since the imx-drm won't be able to retrive its regulators > > from the device tree when using display-timings nodes, > and that I was told that the drm simple-panel driver > already supported that, I then, instead, added what was > lacking to make the eukrea displays work with the > drm-simple-panel driver. > > That required a way to get back the display polarity > informations from the imx-drm driver without affecting > userspace. > > --- > > include/drm/drm_crtc.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h > index f764654..61a4fe1 100644 > --- a/include/drm/drm_crtc.h > +++ b/include/drm/drm_crtc.h > @@ -131,6 +131,13 @@ enum drm_mode_status { > > #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF > > +#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1) > +#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2) > +#define DRM_MODE_FLAG_POL_PIXDATA_PRESERVE BIT(3) > +#define DRM_MODE_FLAG_POL_DE_NEGEDGE BIT(4) > +#define DRM_MODE_FLAG_POL_DE_POSEDGE BIT(5) > +#define DRM_MODE_FLAG_POL_DE_PRESERVE BIT(6)
Could you add some description to these flags. What are *_PRESERVE flags for? Are those flags 1:1 compatible with respective 'videomode:flags'? I guess DE flags should be rather DRM_MODE_FLAG_POL_DE_(LOW|HIGH), am I right?
Possibly nitpicking, I wouldn't call the clock edge on which data signals are generated/sampled "data polarity". This is clock polarity information.
Have you seen cases where pixel data and DE are geenrated or need to be sampled on different edges ?
DE is not a clock signal, but an 'Enable' signal whose value (high or low) defines the window in which the pixel data is valid. The flag defines whether data is valid during the HIGH or LOW period of DE.
The DRM_MODE_FLAG_POL_DE_(LOW|HIGH) do, by my impression of the proposed new DRM_MODE_FLAG_POL_DE_*EDGE flags is that they define sampling clock edges, not active levels.
The current naming of the flags gives the impression that they describe the sampling edges of a clock signal. But the DE signal in fact is not a clock signal but a level sensitive gating signal.
That's not my point. I *know* that DE is a data gating signal with a polarity already defined by the DRM_MODE_FLAG_POL_DE_(LOW|HIGH) flags. Like all other signals it gets generated on a clock edge and is sampled on a clock edge. The DRM_MODE_FLAG_POL_DE_*EDGE flags proposed above describe seem to describe just
The important word here is 'seem'.
Lothar Waßann
The previous hardware behaviour was kept if the flags are not set.
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v10->v11: - This patch was splitted-out and adapted from: "Prepare imx-drm for extra display-timings retrival." - The display-timings dt specific part was removed. - The flags names were changed to use the DRM ones from: "drm: drm_display_mode: add signal polarity flags" --- drivers/staging/imx-drm/imx-drm-core.c | 10 ++++++++++ drivers/staging/imx-drm/imx-drm.h | 6 ++++++ drivers/staging/imx-drm/imx-hdmi.c | 3 +++ drivers/staging/imx-drm/imx-ldb.c | 3 +++ drivers/staging/imx-drm/imx-tve.c | 3 +++ drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 6 ++++-- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 7 ++++++- drivers/staging/imx-drm/ipuv3-crtc.c | 21 +++++++++++++++++++-- 3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h index b95cba1..3abeea3 100644 --- a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h +++ b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h @@ -29,9 +29,11 @@ enum ipuv3_type {
#define CLK_POL_ACTIVE_LOW 0 #define CLK_POL_ACTIVE_HIGH 1 +#define CLK_POL_PRESERVE 2
#define ENABLE_POL_NEGEDGE 0 #define ENABLE_POL_POSEDGE 1 +#define ENABLE_POL_PRESERVE 2
/* * Bitfield of Display Interface signal polarities. @@ -43,10 +45,10 @@ struct ipu_di_signal_cfg { unsigned clksel_en:1; unsigned clkidle_en:1; unsigned data_pol:1; /* true = inverted */ - unsigned clk_pol:1; - unsigned enable_pol:1; unsigned Hsync_pol:1; /* true = active high */ unsigned Vsync_pol:1; + u8 clk_pol; + u8 enable_pol;
u16 width; u16 height; diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 53646aa..791080b 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -597,6 +597,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
if (sig->clk_pol == CLK_POL_ACTIVE_HIGH) di_gen |= DI_GEN_POLARITY_DISP_CLK; + else if (sig->clk_pol == CLK_POL_ACTIVE_LOW) + di_gen &= ~DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
@@ -604,10 +606,13 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) DI_SYNC_AS_GEN);
reg = ipu_di_read(di, DI_POL); - reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); + reg &= ~(DI_POL_DRDY_DATA_POLARITY);
if (sig->enable_pol == ENABLE_POL_POSEDGE) reg |= DI_POL_DRDY_POLARITY_15; + else if (sig->enable_pol == ENABLE_POL_NEGEDGE) + reg &= ~DI_POL_DRDY_POLARITY_15; + if (sig->data_pol) reg |= DI_POL_DRDY_DATA_POLARITY;
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index 8cfeb47..c75034e 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -157,8 +157,25 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = ENABLE_POL_POSEDGE; - sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW; + if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_POSEDGE) + sig_cfg.enable_pol = ENABLE_POL_POSEDGE; + else if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_NEGEDGE) + sig_cfg.enable_pol = ENABLE_POL_NEGEDGE; + else if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_PRESERVE) + sig_cfg.enable_pol = ENABLE_POL_PRESERVE; + else + sig_cfg.enable_pol = ENABLE_POL_POSEDGE; + + if (mode->private_flags & DRM_MODE_FLAG_POL_DE_POSEDGE) + sig_cfg.clk_pol = CLK_POL_ACTIVE_HIGH; + else if (mode->private_flags & DRM_MODE_FLAG_POL_DE_NEGEDGE) + sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW; + else if (mode->private_flags & DRM_MODE_FLAG_POL_DE_PRESERVE) + sig_cfg.clk_pol = CLK_POL_PRESERVE; + else + sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW; + + sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt;
Hi,
Denis Carikli wrote:
The previous hardware behaviour was kept if the flags are not set.
Signed-off-by: Denis Carikli denis@eukrea.com
ChangeLog v10->v11:
- This patch was splitted-out and adapted from: "Prepare imx-drm for extra display-timings retrival."
- The display-timings dt specific part was removed.
- The flags names were changed to use the DRM ones from: "drm: drm_display_mode: add signal polarity flags"
drivers/staging/imx-drm/imx-drm-core.c | 10 ++++++++++ drivers/staging/imx-drm/imx-drm.h | 6 ++++++ drivers/staging/imx-drm/imx-hdmi.c | 3 +++ drivers/staging/imx-drm/imx-ldb.c | 3 +++ drivers/staging/imx-drm/imx-tve.c | 3 +++ drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 6 ++++-- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 7 ++++++- drivers/staging/imx-drm/ipuv3-crtc.c | 21 +++++++++++++++++++-- 3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h index b95cba1..3abeea3 100644 --- a/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h +++ b/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h @@ -29,9 +29,11 @@ enum ipuv3_type {
#define CLK_POL_ACTIVE_LOW 0 #define CLK_POL_ACTIVE_HIGH 1 +#define CLK_POL_PRESERVE 2
#define ENABLE_POL_NEGEDGE 0 #define ENABLE_POL_POSEDGE 1 +#define ENABLE_POL_PRESERVE 2
/*
- Bitfield of Display Interface signal polarities.
@@ -43,10 +45,10 @@ struct ipu_di_signal_cfg { unsigned clksel_en:1; unsigned clkidle_en:1; unsigned data_pol:1; /* true = inverted */
- unsigned clk_pol:1;
- unsigned enable_pol:1; unsigned Hsync_pol:1; /* true = active high */ unsigned Vsync_pol:1;
u8 clk_pol;
u8 enable_pol;
u16 width; u16 height;
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 53646aa..791080b 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -597,6 +597,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
if (sig->clk_pol == CLK_POL_ACTIVE_HIGH) di_gen |= DI_GEN_POLARITY_DISP_CLK;
else if (sig->clk_pol == CLK_POL_ACTIVE_LOW)
di_gen &= ~DI_GEN_POLARITY_DISP_CLK;ipu_di_write(di, di_gen, DI_GENERAL);
@@ -604,10 +606,13 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) DI_SYNC_AS_GEN);
reg = ipu_di_read(di, DI_POL);
- reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
reg &= ~(DI_POL_DRDY_DATA_POLARITY);
if (sig->enable_pol == ENABLE_POL_POSEDGE) reg |= DI_POL_DRDY_POLARITY_15;
else if (sig->enable_pol == ENABLE_POL_NEGEDGE)
reg &= ~DI_POL_DRDY_POLARITY_15;if (sig->data_pol) reg |= DI_POL_DRDY_DATA_POLARITY;
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index 8cfeb47..c75034e 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -157,8 +157,25 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = ENABLE_POL_POSEDGE;
- sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW;
- if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_POSEDGE)
sig_cfg.enable_pol = ENABLE_POL_POSEDGE;- else if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_NEGEDGE)
sig_cfg.enable_pol = ENABLE_POL_NEGEDGE;- else if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_PRESERVE)
sig_cfg.enable_pol = ENABLE_POL_PRESERVE;- else
sig_cfg.enable_pol = ENABLE_POL_POSEDGE;- if (mode->private_flags & DRM_MODE_FLAG_POL_DE_POSEDGE)
sig_cfg.clk_pol = CLK_POL_ACTIVE_HIGH;- else if (mode->private_flags & DRM_MODE_FLAG_POL_DE_NEGEDGE)
sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW;- else if (mode->private_flags & DRM_MODE_FLAG_POL_DE_PRESERVE)
sig_cfg.clk_pol = CLK_POL_PRESERVE;- else
sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW;
This is completely messed up. POL_PIXDATA should obviously define the clock edge at which the pixel data is sampled and thus should determine the value of sig_cfg.clk_pol and POL_DE should determine the value of sig_cfg.enable_pol.
Lothar Waßmann
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v10->v11: - New patch. --- .../bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt | 7 ++ .../bindings/panel/eukrea,mbimxsd51-dvi-svga.txt | 7 ++ .../bindings/panel/eukrea,mbimxsd51-dvi-vga.txt | 7 ++ drivers/gpu/drm/panel/panel-simple.c | 81 ++++++++++++++++++++ 4 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt create mode 100644 Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt create mode 100644 Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt
diff --git a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt new file mode 100644 index 0000000..03679d0 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt @@ -0,0 +1,7 @@ +Eukrea CMO-QVGA (320x240 pixels) TFT LCD panel + +Required properties: +- compatible: should be "eukrea,mbimxsd51-cmo-qvga" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt new file mode 100644 index 0000000..f408c9a --- /dev/null +++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt @@ -0,0 +1,7 @@ +Eukrea DVI-SVGA (800x600 pixels) DVI output. + +Required properties: +- compatible: should be "eukrea,mbimxsd51-dvi-svga" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt new file mode 100644 index 0000000..8ea90da --- /dev/null +++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt @@ -0,0 +1,7 @@ +Eukrea DVI-VGA (640x480 pixels) DVI output. + +Required properties: +- compatible: should be "eukrea,mbimxsd51-dvi-vga" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 0231945..96918bb 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -361,6 +361,78 @@ static const struct panel_desc chunghwa_claa101wb01 = { }, };
+static const struct drm_display_mode eukrea_mbimxsd51_cmoqvga_mode = { + .clock = 6500, + .hdisplay = 320, + .hsync_start = 320 + 38, + .hsync_end = 320 + 38 + 20, + .htotal = 320 + 38 + 20 + 30, + .vdisplay = 240, + .vsync_start = 240 + 15, + .vsync_end = 240 + 15 + 4, + .vtotal = 240 + 15 + 4 + 3, + .vrefresh = 60, + .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE | + DRM_MODE_FLAG_POL_DE_NEGEDGE, +}; + +static const struct panel_desc eukrea_mbimxsd51_cmoqvga = { + .modes = &eukrea_mbimxsd51_cmoqvga_mode, + .num_modes = 1, + .size = { + .width = 73, + .height = 56, + }, +}; + +static const struct drm_display_mode eukrea_mbimxsd51_dvisvga_mode = { + .clock = 44333, + .hdisplay = 800, + .hsync_start = 800 + 112, + .hsync_end = 800 + 112 + 32, + .htotal = 800 + 112 + 32 + 80, + .vdisplay = 600, + .vsync_start = 600 + 3, + .vsync_end = 600 + 3 + 17, + .vtotal = 600 + 3 + 17 + 4, + .vrefresh = 60, + .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_POSEDGE | + DRM_MODE_FLAG_POL_DE_POSEDGE, +}; + +static const struct panel_desc eukrea_mbimxsd51_dvisvga = { + .modes = &eukrea_mbimxsd51_dvisvga_mode, + .num_modes = 1, + .size = { + .width = 0, + .height = 0, + }, +}; + +static const struct drm_display_mode eukrea_mbimxsd51_dvivga_mode = { + .clock = 23750, + .hdisplay = 640, + .hsync_start = 640 + 80, + .hsync_end = 640 + 80 + 16, + .htotal = 640 + 80 + 16 + 64, + .vdisplay = 480, + .vsync_start = 480 + 3, + .vsync_end = 480 + 3 + 13, + .vtotal = 480 + 3 + 13 + 4, + .vrefresh = 60, + .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_POSEDGE | + DRM_MODE_FLAG_POL_DE_POSEDGE, +}; + +static const struct panel_desc eukrea_mbimxsd51_dvivga = { + .modes = &eukrea_mbimxsd51_dvivga_mode, + .num_modes = 1, + .size = { + .width = 0, + .height = 0, + }, +}; + static const struct drm_display_mode lg_lp129qe_mode = { .clock = 285250, .hdisplay = 2560, @@ -413,6 +485,15 @@ static const struct of_device_id platform_of_match[] = { .compatible = "chunghwa,claa101wa01a", .data = &chunghwa_claa101wa01a }, { + .compatible = "eukrea,mbimxsd51-cmo-qvga", + .data = &eukrea_mbimxsd51_cmoqvga, + }, { + .compatible = "eukrea,mbimxsd51-dvi-svga", + .data = &eukrea_mbimxsd51_dvisvga, + }, { + .compatible = "eukrea,mbimxsd51-dvi-vga", + .data = &eukrea_mbimxsd51_dvivga, + }, { .compatible = "chunghwa,claa101wb01", .data = &chunghwa_claa101wb01 }, {
The CMO-QVGA, DVI-SVGA and DVI-VGA are added.
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v10->v11: - Now uses the drm-panel instead of the display-timings. This is to get regulator support, which is lacking in the imx-drm driver when using the display-timings.
ChangeLog v9->v10: - Rebased - Now enables the cmo-qvga regulator at boot.
ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly. - updated pixelclk-active after the following patch: "imx-drm: Match ipu_di_signal_cfg's clk_pol with its description."
ChangeLog v7->v8: - Rebased the patch: added the now required imx-drm node. - Adapted the svga clock-frequency value in order to still be able to display an image after the following commit: "imx-drm: ipu-v3: more inteligent DI clock selection"
ChangeLog v6->v7: - Shrinked even more the Cc list. - Since the pingrp headers were removed, the references to it where replaced by the actual pins. - Added the targets to arch/arm/boot/dts/Makefile
ChangeLog v5->v6: - Reordered the Cc list.
ChangeLog v3->v5: - Updated to new GPIO defines. - Updated to new licenses checkpatch requirements. - one whitespace cleanup.
ChangeLog v2->v3: - Splitted out from the patch that added support for the cpuimx51/mbimxsd51 boards. - This patch now only adds display support. - Added some interested people in the Cc list, and removed some people that might be annoyed by the receiving of that patch which is unrelated to their subsystem. - rebased and reworked the dts displays addition. - Also rebased and reworked the fsl,pins usage. --- arch/arm/boot/dts/Makefile | 3 ++ .../imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts | 41 ++++++++++++++++ .../imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts | 28 +++++++++++ .../imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts | 28 +++++++++++ .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 49 ++++++++++++++++++++ 5 files changed, 149 insertions(+) create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts create mode 100644 arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cf6c523..1f18800 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -178,6 +178,9 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx51-apf51dev.dtb \ imx51-babbage.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dtb \ + imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dtb \ + imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dtb \ imx53-ard.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts new file mode 100644 index 0000000..7c280f8 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the CMO-QVGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-cmo-qvga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-cmo-qvga", "simple-panel"; + power-supply = <®_lcd_3v3>; + }; + + reg_lcd_3v3: lcd-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts new file mode 100644 index 0000000..323ebf4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the DVI-SVGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-dvi-svga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-dvi-svga", "simple-panel"; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts new file mode 100644 index 0000000..f065500 --- /dev/null +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2013 Eukréa Electromatique denis@eukrea.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx51-eukrea-mbimxsd51-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD51 with the DVI-VGA Display"; + compatible = "eukrea,mbimxsd51-baseboard-dvi-vga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51"; + + panel: panel { + compatible = "eukrea,mbimxsd51-dvi-vga", "simple-panel"; + }; +}; + +&display { + status = "okay"; + fsl,panel = <&panel>; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 5cec4f3..dbd1832 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -24,6 +24,20 @@ model = "Eukrea CPUIMX51"; compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
+ display: display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp1>; + status = "disabled"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + }; + gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -146,6 +160,37 @@ >; };
+ pinctrl_ipu_disp1: ipudisp1grp { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 + >; + }; + pinctrl_reg_lcd_3v3: reg_lcd_3v3 { fsl,pins = < MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 @@ -154,6 +199,10 @@ }; };
+&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + &ssi2 { codec-handle = <&tlv320aic23>; fsl,mode = "i2s-slave";
Signed-off-by: Denis Carikli denis@eukrea.com --- ChangeLog v9->v11: - Now uses the drm-panel instead of the display-timings.
ChangeLog v8->v9: - Removed the Cc. They are now set in git-send-email directly. - The backlight is now on at boot.
ChangeLog v6->v7: - Shrinked even more the Cc list.
ChangeLog v5->v6: - Reordered the Cc list.
ChangeLog v3->v5: - Updated to the new GPIO defines.
ChangeLog v2->v3: - Splitted out from the patch that added support for the cpuimx51/mbimxsd51 boards. - This patch now only adds backlight support. - Added some interested people in the Cc list, and removed some people that might be annoyed by the receiving of that patch which is unrelated to their subsystem. --- .../imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts index 7c280f8..4a3f805 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts @@ -17,9 +17,19 @@ model = "Eukrea MBIMXSD51 with the CMO-QVGA Display"; compatible = "eukrea,mbimxsd51-baseboard-cmo-qvga", "eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51";
+ backlight: backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_1>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + default-brightness-level = <1>; + default-on; + }; + panel: panel { compatible = "eukrea,mbimxsd51-cmo-qvga", "simple-panel"; power-supply = <®_lcd_3v3>; + backlight = <&backlight>; };
reg_lcd_3v3: lcd-en {
The DRM_PANEL_SIMPLE is needed by the eukrea mbimxsd51's displays.
Signed-off-by: Denis Carikli denis@eukrea.com --- - New patch, splitting it would be overkill. --- arch/arm/configs/imx_v6_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 09e9743..0316926 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -183,6 +183,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=y CONFIG_SOC_CAMERA_OV2640=y CONFIG_DRM=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y @@ -245,6 +246,7 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3_CORE=y CONFIG_DRM_IMX_IPUV3=y +CONFIG_DRM_IMX_HDMI=y CONFIG_COMMON_CLK_DEBUG=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y
dri-devel@lists.freedesktop.org
-
Andrzej Hajda -
Denis Carikli -
Laurent Pinchart -
Lothar Waßmann -
Russell King - ARM Linux