Document new DVFS OPP table and voltage regulator properties of the SDHCI controller.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 96c0b1440c9c..1beb0416ae5f 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -31,6 +31,16 @@ Required properties:

Optional properties: - power-gpios : Specify GPIOs for power control +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled.

Example:

@@ -45,6 +55,8 @@ sdhci@c8000200 { wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <8>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; };

Optional properties for Tegra210, Tegra186 and Tegra194:

Document new DVFS OPP table and voltage regulator properties of the PWM controller.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index 74c41e34c3b6..d4d1c44a2c04 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -32,6 +32,17 @@ The PWM node will have following optional properties. pinctrl-names: Pin state names. Must be "default" and "sleep". pinctrl-0: phandle for the default/active state of pin configurations. pinctrl-1: phandle for the sleep state of pin configurations. +core-supply: phandle for voltage regulator of the SoC "core" power domain. + +operating-points-v2: see ../bindings/opp/opp.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled.

Example:

@@ -42,6 +53,8 @@ Example: clocks = <&tegra_car 17>; resets = <&tegra_car 17>; reset-names = "pwm"; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; };

Document new DVFS OPP table and voltage regulator properties of the video decoder engine.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../devicetree/bindings/media/nvidia,tegra-vde.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt index 602169b8aa19..9854fa9d3cd3 100644 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt @@ -36,6 +36,16 @@ Optional properties: - reset-names : Must include the following entries: - mc - iommus: Must contain phandle to the IOMMU device node. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- core-supply: Phandle to voltage regulator of the SoC "core" power domain. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled.

Example:

@@ -61,4 +71,6 @@ video-codec@6001a000 { reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; };

Document new OPP table and NVIDIA Tegra-specific voltage regulator properties.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index a5c5db6a0b2d..f02a98201062 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -90,6 +90,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- operating-points-v2: See ../bindings/opp/opp.txt for details.

i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -110,6 +111,9 @@ i.mx specific properties The range is from 0x0 to 0xf, the default value is 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.

+Tegra specific properties +- core-supply: phandle of voltage regulator of the SoC "core" power domain + Example:

usb@f7ed0000 {

Document new DVFS OPP table and voltage regulator properties of the Tegra EHCI controller.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index f60785f73d3d..e4070ae21fd9 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt @@ -21,3 +21,5 @@ Required properties : Optional properties: - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 USB ports, which need reset twice due to hardware issues. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - core-supply: Phandle of voltage regulator of the SoC "core" power domain.

Introduce sync state API that will be used by Tegra device drivers. This new API is primarily needed for syncing state of SoC devices that are left ON after bootloader or permanently enabled. All these devices belong to a shared CORE voltage domain, and thus, we needed to bring all the devices into expected state before the voltage scaling could be performed.

All drivers of DVFS-critical devices shall sync theirs the state before Tegra's voltage regulator coupler will be allowed to perform a system-wide voltage scaling.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/common.c | 152 ++++++++++++++++++++++++++++++++++++- include/soc/tegra/common.h | 22 ++++++ 2 files changed, 170 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 3dc54f59cafe..f9b2b6f57887 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -3,13 +3,52 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */

+#define dev_fmt(fmt) "%s: " fmt, __func__ +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/export.h> +#include <linux/init.h> +#include <linux/mutex.h> #include <linux/of.h> +#include <linux/of_device.h>

#include <soc/tegra/common.h>

+#define terga_soc_for_each_device(__dev) \ + for ((__dev) = tegra_soc_devices; (__dev) && (__dev)->compatible; \ + (__dev)++) + +struct tegra_soc_device { + const char *compatible; + const bool dvfs_critical; + unsigned int sync_count; +}; + +static DEFINE_MUTEX(tegra_soc_lock); +static struct tegra_soc_device *tegra_soc_devices; + +/* + * DVFS-critical devices are either active at a boot time or permanently + * active, like EMC for example. System-wide DVFS should be deferred until + * drivers of the critical devices synced theirs state. + */ + +static struct tegra_soc_device tegra20_soc_devices[] = { + { .compatible = "nvidia,tegra20-dc", .dvfs_critical = true, }, + { .compatible = "nvidia,tegra20-emc", .dvfs_critical = true, }, + { } +}; + +static struct tegra_soc_device tegra30_soc_devices[] = { + { .compatible = "nvidia,tegra30-dc", .dvfs_critical = true, }, + { .compatible = "nvidia,tegra30-emc", .dvfs_critical = true, }, + { .compatible = "nvidia,tegra30-pwm", .dvfs_critical = true, }, + { } +}; + static const struct of_device_id tegra_machine_match[] = { - { .compatible = "nvidia,tegra20", }, - { .compatible = "nvidia,tegra30", }, + { .compatible = "nvidia,tegra20", .data = tegra20_soc_devices, }, + { .compatible = "nvidia,tegra30", .data = tegra30_soc_devices, }, { .compatible = "nvidia,tegra114", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra132", }, @@ -17,7 +56,7 @@ static const struct of_device_id tegra_machine_match[] = { { } };

-bool soc_is_tegra(void) +static const struct of_device_id *tegra_soc_of_match(void) { const struct of_device_id *match; struct device_node *root; @@ -29,5 +68,110 @@ bool soc_is_tegra(void) match = of_match_node(tegra_machine_match, root); of_node_put(root);

- return match != NULL; + return match; +} + +bool soc_is_tegra(void) +{ + return tegra_soc_of_match() != NULL; +} + +void tegra_soc_device_sync_state(struct device *dev) +{ + struct tegra_soc_device *soc_dev; + + mutex_lock(&tegra_soc_lock); + terga_soc_for_each_device(soc_dev) { + if (!of_device_is_compatible(dev->of_node, soc_dev->compatible)) + continue; + + if (!soc_dev->sync_count) { + dev_err(dev, "already synced\n"); + break; + } + + /* + * All DVFS-capable devices should have the CORE regulator + * phandle. Older device-trees don't have it, hence state + * won't be synced for the older DTBs, allowing them to work + * properly. + */ + if (soc_dev->dvfs_critical && + !device_property_present(dev, "core-supply")) { + dev_dbg(dev, "doesn't have core supply\n"); + break; + } + + soc_dev->sync_count--; + dev_dbg(dev, "sync_count=%u\n", soc_dev->sync_count); + break; + } + mutex_unlock(&tegra_soc_lock); +} +EXPORT_SYMBOL_GPL(tegra_soc_device_sync_state); + +bool tegra_soc_dvfs_state_synced(void) +{ + struct tegra_soc_device *soc_dev; + bool synced_state = true; + + /* + * CORE voltage scaling is limited until drivers of the critical + * devices synced theirs state. + */ + mutex_lock(&tegra_soc_lock); + terga_soc_for_each_device(soc_dev) { + if (!soc_dev->sync_count || !soc_dev->dvfs_critical) + continue; + + pr_debug_ratelimited("%s: sync_count=%u\n", + soc_dev->compatible, soc_dev->sync_count); + + synced_state = false; + break; + } + mutex_unlock(&tegra_soc_lock); + + return synced_state; +} + +static int __init tegra_soc_devices_init(void) +{ + struct device_node *np, *prev_np = NULL; + struct tegra_soc_device *soc_dev; + const struct of_device_id *match; + + if (!soc_is_tegra()) + return 0; + + match = tegra_soc_of_match(); + tegra_soc_devices = (void *)match->data; + + /* + * If device node is disabled in a device-tree, then we shouldn't + * care about this device. Even if device is active during boot, + * its clock will be disabled by CCF as unused. + */ + terga_soc_for_each_device(soc_dev) { + do { + /* + * Devices like display controller have multiple + * instances with the same compatible. Hence we need + * to walk up the whole tree in order to account those + * multiple instances. + */ + np = of_find_compatible_node(prev_np, NULL, + soc_dev->compatible); + of_node_put(prev_np); + prev_np = np; + + if (of_device_is_available(np)) { + pr_debug("added %s\n", soc_dev->compatible); + soc_dev->sync_count++; + } + } while (np); + } + + return 0; } +postcore_initcall_sync(tegra_soc_devices_init); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..d3ddb96d0fe2 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,28 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__

+#include <linux/types.h> + +struct device; + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +void tegra_soc_device_sync_state(struct device *dev); +bool tegra_soc_dvfs_state_synced(void); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} + +static inline void tegra_soc_device_sync_state(struct device *dev) +{ +} + +static inline tegra_soc_dvfs_state_synced(void) +{ + return false; +} +#endif

#endif /* __SOC_TEGRA_COMMON_H__ */

Downscale of the CORE voltage isn't allowed because some hardware units, which are supplied by the CORE regulator, usually left ON at a boot time. The new sync state API resolves this problem for us. All drivers of the devices that are known to be ON at a boot time now should sync theirs state. Once everything is synced, the voltage of the CORE domain could be scaled without any limitations.

Make Tegra20/30 regulator couplers to use the new sync state API.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..8782e399a58c 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -16,6 +16,8 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h>

+#include <soc/tegra/common.h> + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err;

+ /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Host1x bus for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_dvfs_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV;

@@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV;

- pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);

return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 7f21f31de09d..f7a5260edffe 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -16,6 +16,7 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h>

+#include <soc/tegra/common.h> #include <soc/tegra/fuse.h>

struct tegra_regulator_coupler { @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err;

+ /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Host1x bus for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_dvfs_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV;

@@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV;

- pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);

return tegra->core_min_uV; } @@ -143,6 +159,10 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (core_min_uV < 0) return core_min_uV;

+ err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV); + if (err) + return err; + err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV, PM_SUSPEND_ON); if (err)

Add option which allows regulator_check_consumers() to skip accounting of a disabled consumer regulators.

This new option is needed for the NVIDIA Tegra voltage couplers in order to properly calculate a lowest possible voltage for the CORE regulator. The requirements of a disabled consumer regulators should not be accounted by the Tegra voltage balancers because disabled state means that hardware is inactive. In particular disabled state shouldn't be accounted for the consumers which belong to the CORE voltage domain, meanwhile CPU domain should continue to account the disabled state.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/regulator/core.c | 12 ++++++++---- drivers/soc/samsung/exynos-regulator-coupler.c | 2 +- drivers/soc/tegra/regulators-tegra20.c | 6 +++--- drivers/soc/tegra/regulators-tegra30.c | 6 +++--- include/linux/regulator/coupler.h | 6 ++++-- 5 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index f258ded39ce0..015dcd8408d9 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -462,7 +462,8 @@ static int regulator_check_states(suspend_state_t state) */ int regulator_check_consumers(struct regulator_dev *rdev, int *min_uV, int *max_uV, - suspend_state_t state) + suspend_state_t state, + bool skip_disabled_regulators) { struct regulator *regulator; struct regulator_voltage *voltage; @@ -476,6 +477,9 @@ int regulator_check_consumers(struct regulator_dev *rdev, if (!voltage->min_uV && !voltage->max_uV) continue;

+ if (skip_disabled_regulators && !regulator->enable_count) + continue; + if (*max_uV > voltage->max_uV) *max_uV = voltage->max_uV; if (*min_uV < voltage->min_uV) @@ -3662,7 +3666,7 @@ static int regulator_get_optimal_voltage(struct regulator_dev *rdev,

ret = regulator_check_consumers(rdev, &desired_min_uV, - &desired_max_uV, state); + &desired_max_uV, state, false); if (ret < 0) return ret;

@@ -3681,7 +3685,7 @@ static int regulator_get_optimal_voltage(struct regulator_dev *rdev,

ret = regulator_check_consumers(c_rdevs[i], &tmp_min, - &tmp_max, state); + &tmp_max, state, false); if (ret < 0) return ret;

@@ -4119,7 +4123,7 @@ int regulator_sync_voltage(struct regulator *regulator) if (ret < 0) goto out;

- ret = regulator_check_consumers(rdev, &min_uV, &max_uV, 0); + ret = regulator_check_consumers(rdev, &min_uV, &max_uV, 0, false); if (ret < 0) goto out;

diff --git a/drivers/soc/samsung/exynos-regulator-coupler.c b/drivers/soc/samsung/exynos-regulator-coupler.c index 61a156b44a48..9bd99a93e3e0 100644 --- a/drivers/soc/samsung/exynos-regulator-coupler.c +++ b/drivers/soc/samsung/exynos-regulator-coupler.c @@ -41,7 +41,7 @@ static int regulator_get_optimal_voltage(struct regulator_dev *rdev,

ret = regulator_check_consumers(c_rdevs[i], &tmp_min, - &tmp_max, state); + &tmp_max, state, false); if (ret < 0) return ret;

diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 8782e399a58c..8c31acb5fdc6 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -136,7 +136,7 @@ static int tegra20_core_rtc_update(struct tegra_regulator_coupler *tegra, return err;

err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV, - PM_SUSPEND_ON); + PM_SUSPEND_ON, true); if (err) return err;

@@ -246,12 +246,12 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, return err;

err = regulator_check_consumers(cpu_rdev, &cpu_min_uV, &cpu_max_uV, - PM_SUSPEND_ON); + PM_SUSPEND_ON, false); if (err) return err;

err = regulator_check_consumers(cpu_rdev, &cpu_min_uV_consumers, - &cpu_max_uV, PM_SUSPEND_ON); + &cpu_max_uV, PM_SUSPEND_ON, false); if (err) return err;

diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index fcf824f73131..d92aafa736bc 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -164,7 +164,7 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, return err;

err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV, - PM_SUSPEND_ON); + PM_SUSPEND_ON, true); if (err) return err;

@@ -175,12 +175,12 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, cpu_min_uV = core_min_uV - max_spread;

err = regulator_check_consumers(cpu_rdev, &cpu_min_uV, &cpu_max_uV, - PM_SUSPEND_ON); + PM_SUSPEND_ON, false); if (err) return err;

err = regulator_check_consumers(cpu_rdev, &cpu_min_uV_consumers, - &cpu_max_uV, PM_SUSPEND_ON); + &cpu_max_uV, PM_SUSPEND_ON, false); if (err) return err;

diff --git a/include/linux/regulator/coupler.h b/include/linux/regulator/coupler.h index 5f86824bd117..4e076567b823 100644 --- a/include/linux/regulator/coupler.h +++ b/include/linux/regulator/coupler.h @@ -55,7 +55,8 @@ int regulator_coupler_register(struct regulator_coupler *coupler); const char *rdev_get_name(struct regulator_dev *rdev); int regulator_check_consumers(struct regulator_dev *rdev, int *min_uV, int *max_uV, - suspend_state_t state); + suspend_state_t state, + bool skip_disabled_regulators); int regulator_check_voltage(struct regulator_dev *rdev, int *min_uV, int *max_uV); int regulator_get_voltage_rdev(struct regulator_dev *rdev); @@ -75,7 +76,8 @@ static inline const char *rdev_get_name(struct regulator_dev *rdev) } static inline int regulator_check_consumers(struct regulator_dev *rdev, int *min_uV, int *max_uV, - suspend_state_t state) + suspend_state_t state, + bool skip_disabled_regulators)) { return -EINVAL; }

The device-tree compatibles are swapped in the code, correct them.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/tegra/gr2d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c index 1a0d3ba6e525..f30aa86e4c9f 100644 --- a/drivers/gpu/drm/tegra/gr2d.c +++ b/drivers/gpu/drm/tegra/gr2d.c @@ -162,8 +162,8 @@ static const struct gr2d_soc tegra30_gr2d_soc = { };

static const struct of_device_id gr2d_match[] = { - { .compatible = "nvidia,tegra30-gr2d", .data = &tegra20_gr2d_soc }, - { .compatible = "nvidia,tegra20-gr2d", .data = &tegra30_gr2d_soc }, + { .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc }, + { .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc }, { }, }; MODULE_DEVICE_TABLE(of, gr2d_match);

Add OPP and SoC core voltage scaling support to the GR3D driver. This is required for enabling system-wide DVFS on Tegra SoCs.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/tegra/gr3d.c | 136 +++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+)

diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c index b0b8154e8104..0c6efc55f9bc 100644 --- a/drivers/gpu/drm/tegra/gr3d.c +++ b/drivers/gpu/drm/tegra/gr3d.c @@ -11,7 +11,9 @@ #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/reset.h> +#include <linux/pm_opp.h>

+#include <soc/tegra/fuse.h> #include <soc/tegra/pmc.h>

#include "drm.h" @@ -278,6 +280,135 @@ static const u32 gr3d_addr_regs[] = { GR3D_GLOBAL_SAMP23SURFADDR(15), };

+static int gr3d_init_opp_state(struct device *dev, struct gr3d *gr3d) +{ + struct dev_pm_opp *opp; + unsigned long rate; + int err; + + /* + * If voltage regulator presents, then we could select the fastest + * clock rate, but driver doesn't support power management and + * frequency scaling yet, hence the top freq OPP will vote for a + * very high voltage that will produce lot's of heat. Let's select + * OPP for the current/default rate for now. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + rate = clk_get_rate(gr3d->clk); + + /* find suitable OPP for the clock rate supportable by SoC speedo ID */ + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + + /* + * dev_pm_opp_set_rate() doesn't search for a floor clock rate and it + * will error out if default clock rate is too high, i.e. unsupported + * by a SoC hardware version. Hence will find floor rate by ourselves. + */ + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dev, &rate); + + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP for %ld Hz: %d\n", + rate, err); + return err; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. We need to do this because GR2D + * currently doesn't support power management and clock is permanently + * enabled. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +static void gr3d_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_gr3d_init_opp_table(struct device *dev, struct gr3d *gr3d) +{ + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + if (gr3d->soc->version == 0x20) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + err = gr3d_init_opp_state(dev, gr3d); + if (err) + goto remove_table; + } + + err = devm_add_action(dev, gr3d_deinit_opp_table, dev); + if (err) + goto remove_table; + + dev_info(dev, "OPP HW ver. 0x%x\n", hw_version); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int gr3d_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -302,6 +433,11 @@ static int gr3d_probe(struct platform_device *pdev) return PTR_ERR(gr3d->clk); }

+ err = devm_gr3d_init_opp_table(&pdev->dev, gr3d); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to initialize OPP\n"); + gr3d->rst = devm_reset_control_get(&pdev->dev, "3d"); if (IS_ERR(gr3d->rst)) { dev_err(&pdev->dev, "cannot get reset\n");

Add initial OPP and SoC core voltage scaling support to the Host1x driver. This is required for enabling system-wide DVFS on older Tegra SoCs.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/host1x/Kconfig | 1 + drivers/gpu/host1x/dev.c | 87 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+)

diff --git a/drivers/gpu/host1x/Kconfig b/drivers/gpu/host1x/Kconfig index 6dab94adf25e..fba4207c35a4 100644 --- a/drivers/gpu/host1x/Kconfig +++ b/drivers/gpu/host1x/Kconfig @@ -3,6 +3,7 @@ config TEGRA_HOST1X tristate "NVIDIA Tegra host1x driver" depends on ARCH_TEGRA || (ARM && COMPILE_TEST) select IOMMU_IOVA + select PM_OPP help Driver for the NVIDIA Tegra host1x hardware.

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index d0ebb70e2fdd..06e65dc1ab19 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -13,6 +13,9 @@ #include <linux/of_device.h> #include <linux/of.h> #include <linux/slab.h> +#include <linux/pm_opp.h> + +#include <soc/tegra/fuse.h>

#define CREATE_TRACE_POINTS #include <trace/events/host1x.h> @@ -341,6 +344,85 @@ static void host1x_iommu_exit(struct host1x *host) } }

+static void host1x_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_host1x_init_opp_table(struct host1x *host) +{ + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + if (device_property_present(host->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(host->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(host->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(host->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(host->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(host->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + */ + if (device_property_present(host->dev, "operating-points-v2")) { + err = dev_pm_opp_of_add_table(host->dev); + if (err) { + dev_err(host->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + } + + /* first dummy rate-set initializes voltage vote */ + err = dev_pm_opp_set_rate(host->dev, clk_get_rate(host->clk)); + if (err) { + dev_err(host->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + err = devm_add_action(host->dev, host1x_deinit_opp_table, host->dev); + if (err) + goto remove_table; + + dev_info(host->dev, "OPP HW ver. 0x%x\n", hw_version); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(host->dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int host1x_probe(struct platform_device *pdev) { struct host1x *host; @@ -424,6 +506,11 @@ static int host1x_probe(struct platform_device *pdev) return err; }

+ err = devm_host1x_init_opp_table(host); + if (err < 0) + return dev_err_probe(&pdev->dev, err, + "failed to initialize OPP\n"); + err = host1x_iommu_init(host); if (err < 0) { dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);

Add initial OPP and SoC core voltage scaling support to the video decoder driver. This is required for enabling system-wide DVFS on older Tegra SoCs.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/staging/media/tegra-vde/Kconfig | 1 + drivers/staging/media/tegra-vde/vde.c | 127 ++++++++++++++++++++++++ drivers/staging/media/tegra-vde/vde.h | 1 + 3 files changed, 129 insertions(+)

diff --git a/drivers/staging/media/tegra-vde/Kconfig b/drivers/staging/media/tegra-vde/Kconfig index 0dc78afd09e0..0ebfe5b07a30 100644 --- a/drivers/staging/media/tegra-vde/Kconfig +++ b/drivers/staging/media/tegra-vde/Kconfig @@ -4,6 +4,7 @@ config TEGRA_VDE depends on ARCH_TEGRA || COMPILE_TEST select DMA_SHARED_BUFFER select IOMMU_IOVA + select PM_OPP select SRAM help Say Y here to enable support for the NVIDIA Tegra video decoder diff --git a/drivers/staging/media/tegra-vde/vde.c b/drivers/staging/media/tegra-vde/vde.c index 28845b5bafaf..9ad43a862eef 100644 --- a/drivers/staging/media/tegra-vde/vde.c +++ b/drivers/staging/media/tegra-vde/vde.c @@ -15,11 +15,13 @@ #include <linux/miscdevice.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/uaccess.h>

+#include <soc/tegra/fuse.h> #include <soc/tegra/pmc.h>

#include "uapi.h" @@ -926,6 +928,9 @@ static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev)

clk_disable_unprepare(vde->clk);

+ /* remove performance/voltage vote */ + dev_pm_opp_set_rate(dev, 0); + return 0; }

@@ -934,6 +939,12 @@ static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) struct tegra_vde *vde = dev_get_drvdata(dev); int err;

+ err = dev_pm_opp_set_rate(dev, vde->default_clk_rate); + if (err) { + dev_err(dev, "Failed to set clock rate: %d\n", err); + return err; + } + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC, vde->clk, vde->rst); if (err) { @@ -944,6 +955,118 @@ static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) return 0; }

+static void tegra_vde_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_tegra_vde_init_opp_table(struct device *dev, + struct tegra_vde *vde) +{ + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + struct dev_pm_opp *opp; + unsigned long rate; + u32 hw_version; + int err; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "Failed to prepare OPP table\n"); + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(dev, "Failed to set supported HW: %d\n", err); + goto put_table; + } + + /* + * OPP table presence is optional and we want the set_rate() of OPP + * API to work similarly to clk_set_rate() if table is missing in a + * device-tree. The add_table() errors out if OPP is missing in DT. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + if (!device_property_present(dev, "operating-points-v2")) { + vde->default_clk_rate = clk_get_rate(vde->clk); + goto add_action; + } + + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "Failed to add OPP table: %d\n", err); + goto put_hw; + } + + /* + * If voltage regulator presents, then we could select the fastest + * clock rate, but driver doesn't support frequency scaling yet, + * hence the top freq OPP may vote for a very high voltage that will + * produce lot's of heat. Let's select OPP for the current/default + * rate for now. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + rate = clk_get_rate(vde->clk); + + /* find suitable OPP for the clock rate supportable by SoC */ + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dev, &rate); + + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP for %ld Hz: %d\n", + rate, err); + goto remove_table; + } + + dev_pm_opp_put(opp); + + vde->default_clk_rate = clk_round_rate(vde->clk, rate); + +add_action: + err = devm_add_action(dev, tegra_vde_deinit_opp_table, dev); + if (err) + goto remove_table; + + dev_info(dev, "OPP HW ver. 0x%x, clock rate %lu MHz\n", + hw_version, vde->default_clk_rate / 1000000); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_vde_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1024,6 +1147,10 @@ static int tegra_vde_probe(struct platform_device *pdev) return err; }

+ err = devm_tegra_vde_init_opp_table(dev, vde); + if (err) + return dev_err_probe(dev, err, "Failed to initialize OPP\n"); + vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0); if (!vde->iram_pool) { dev_err(dev, "Could not get IRAM pool\n"); diff --git a/drivers/staging/media/tegra-vde/vde.h b/drivers/staging/media/tegra-vde/vde.h index 5561291b0c88..da83c2d6af8b 100644 --- a/drivers/staging/media/tegra-vde/vde.h +++ b/drivers/staging/media/tegra-vde/vde.h @@ -48,6 +48,7 @@ struct tegra_vde { struct iova_domain iova; struct iova *iova_resv_static_addresses; struct iova *iova_resv_last_page; + unsigned long default_clk_rate; dma_addr_t iram_lists_addr; u32 *iram; };

Add initial OPP and SoC core voltage scaling support to the Tegra EHCI driver. This is required for enabling system-wide DVFS on older Tegra SoCs.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/usb/host/Kconfig | 1 + drivers/usb/host/ehci-tegra.c | 79 +++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index ab12c4bf0ef1..35c42bc05c5a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -278,6 +278,7 @@ config USB_EHCI_TEGRA depends on ARCH_TEGRA select USB_EHCI_ROOT_HUB_TT select USB_TEGRA_PHY + select PM_OPP help This driver enables support for the internal USB Host Controllers found in NVIDIA Tegra SoCs. The controllers are EHCI compliant. diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 869d9c4de5fc..0976577f54b4 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -17,6 +17,7 @@ #include <linux/of_device.h> #include <linux/of_gpio.h> #include <linux/platform_device.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> @@ -364,6 +365,79 @@ static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) free_dma_aligned_buffer(urb); }

+static void tegra_ehci_deinit_opp_table(void *data) +{ + struct device *dev = data; + struct opp_table *opp_table; + + opp_table = dev_pm_opp_get_opp_table(dev); + dev_pm_opp_of_remove_table(dev); + dev_pm_opp_put_regulators(opp_table); + dev_pm_opp_put_opp_table(opp_table); +} + +static int devm_tegra_ehci_init_opp_table(struct device *dev) +{ + unsigned long rate = ULONG_MAX; + struct opp_table *opp_table; + const char *rname = "core"; + struct dev_pm_opp *opp; + int err; + + /* legacy device-trees don't have OPP table */ + if (!device_property_present(dev, "operating-points-v2")) + return 0; + + /* voltage scaling is optional */ + if (device_property_present(dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + err = dev_pm_opp_of_add_table(dev); + if (err) { + dev_err(dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + + /* find suitable OPP for the maximum clock rate */ + opp = dev_pm_opp_find_freq_floor(dev, &rate); + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP: %d\n", err); + goto remove_table; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + err = devm_add_action(dev, tegra_ehci_deinit_opp_table, dev); + if (err) + goto remove_table; + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static const struct tegra_ehci_soc_config tegra30_soc_config = { .has_hostpc = true, }; @@ -431,6 +505,11 @@ static int tegra_ehci_probe(struct platform_device *pdev) goto cleanup_hcd_create; }

+ err = devm_tegra_ehci_init_opp_table(&pdev->dev); + if (err) + return dev_err_probe(&pdev->dev, err, + "Failed to initialize OPP\n"); + err = clk_prepare_enable(tegra->clk); if (err) goto cleanup_hcd_create;

Sync driver state using the Tegra SoC device state syncing API, telling to regulators voltage coupler that EMC state is ready for DVFS. This is required for enabling system-wide DVFS on Tegra20.

Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/memory/tegra/tegra20-emc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 9946b957bb01..b1b0a2439689 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -1129,6 +1129,12 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; }

+static void tegra_emc_sync_state(struct device *dev) +{ + tegra_soc_device_sync_state(dev); + icc_sync_state(dev); +} + static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, @@ -1141,7 +1147,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra20-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, - .sync_state = icc_sync_state, + .sync_state = tegra_emc_sync_state, }, }; module_platform_driver(tegra_emc_driver);

Add OPP tables for Tegra20 SoC devices.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 386 ++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 14 + 2 files changed, 400 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index 25b1ba73951e..792dc79d32c5 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -89,4 +89,390 @@ opp@760000000 { opp-hz = /bits/ 64 <760000000>; }; }; + + vde_dvfs_opp_table: vde-opp-table { + compatible = "operating-points-v2"; + + opp@95000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + }; + + opp@123500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + }; + + opp@123500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + }; + + opp@152000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + }; + + opp@152000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + }; + + opp@171000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + }; + + opp@209000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + }; + + opp@218500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + }; + + opp@237500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + }; + + opp@275500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + }; + + opp@300000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + }; + + gr2d_dvfs_opp_table: gr2d-opp-table { + compatible = "operating-points-v2"; + + opp@133000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + }; + + opp@171000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + }; + }; + + gr3d_dvfs_opp_table: gr3d-opp-table { + compatible = "operating-points-v2"; + + opp@114000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + }; + + opp@161500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + }; + + opp@161500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + }; + + opp@218500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + }; + + opp@247000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + }; + + opp@256500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + }; + + opp@285000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + }; + + opp@304000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + }; + + opp@323000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + }; + + opp@333500000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + }; + + opp@333500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + }; + + opp@351500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + }; + + opp@361000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + }; + + opp@380000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + }; + + opp@400000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + }; + + opp@400000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + }; + }; + + host1x_dvfs_opp_table: host1x-opp-table { + compatible = "operating-points-v2"; + + opp@104500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + }; + + opp@133000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + }; + + opp@166000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + }; + }; + + usbd_dvfs_opp_table: usbd-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb2_dvfs_opp_table: usb2-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + usb3_dvfs_opp_table: usb3-opp-table { + compatible = "operating-points-v2"; + + opp@480000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + }; + }; + + sdmmc1_dvfs_opp_table: sdmmc1-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc2_dvfs_opp_table: sdmmc2-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc3_dvfs_opp_table: sdmmc3-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + sdmmc4_dvfs_opp_table: sdmmc4-opp-table { + compatible = "operating-points-v2"; + + opp@44000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + }; + + opp@52000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + }; + }; + + hdmi_dvfs_opp_table: hdmi-opp-table { + compatible = "operating-points-v2"; + + opp@148500000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + }; + }; + + dc0_dvfs_opp_table: dc0-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + }; + + dc1_dvfs_opp_table: dc1-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6ce498178105..317bdf75ff6c 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,7 @@ host1x@50000000 { clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&host1x_dvfs_opp_table>;

#address-cells = <1>; #size-cells = <1>; @@ -91,6 +92,7 @@ gr2d@54140000 { clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&gr2d_dvfs_opp_table>; };

gr3d@54180000 { @@ -99,6 +101,7 @@ gr3d@54180000 { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; };

dc@54200000 { @@ -110,6 +113,7 @@ dc@54200000 { clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dc0_dvfs_opp_table>;

nvidia,head = <0>;

@@ -138,6 +142,7 @@ dc@54240000 { clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dc1_dvfs_opp_table>;

nvidia,head = <1>;

@@ -167,6 +172,7 @@ hdmi@54280000 { resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&hdmi_dvfs_opp_table>; };

tvo@542c0000 { @@ -319,6 +325,7 @@ vde@6001a000 { clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + operating-points-v2 = <&vde_dvfs_opp_table>; };

apbmisc@70000800 { @@ -755,6 +762,7 @@ usb@c5000000 { nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; + operating-points-v2 = <&usbd_dvfs_opp_table>; };

phy1: usb-phy@c5000000 { @@ -792,6 +800,7 @@ usb@c5004000 { reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; + operating-points-v2 = <&usb2_dvfs_opp_table>; };

phy2: usb-phy@c5004000 { @@ -818,6 +827,7 @@ usb@c5008000 { reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; + operating-points-v2 = <&usb3_dvfs_opp_table>; };

phy3: usb-phy@c5008000 { @@ -852,6 +862,7 @@ mmc@c8000000 { resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; };

mmc@c8000200 { @@ -863,6 +874,7 @@ mmc@c8000200 { resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; };

mmc@c8000400 { @@ -874,6 +886,7 @@ mmc@c8000400 { resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; };

mmc@c8000600 { @@ -885,6 +898,7 @@ mmc@c8000600 { resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; };

cpus {

Add voltage supplies to DVFS-capable devices in order to enable system-wide voltage scaling and allow CORE/RTC regulators to go lower.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- arch/arm/boot/dts/tegra20-ventana.dts | 65 +++++++++++++++++++++++---- 1 file changed, 56 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b158771ac0b7..d5d90605e649 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -23,7 +23,19 @@ memory@0 { };

host1x@50000000 { + core-supply = <&vdd_core>; + + gr2d@54140000 { + core-supply = <&vdd_core>; + }; + + gr3d@54180000 { + core-supply = <&vdd_core>; + }; + dc@54200000 { + core-supply = <&vdd_core>; + rgb { status = "okay";

@@ -31,11 +43,16 @@ rgb { }; };

+ dc@54240000 { + core-supply = <&vdd_core>; + }; + hdmi@54280000 { status = "okay";

vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; + core-supply = <&vdd_core>;

nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) @@ -43,6 +60,10 @@ hdmi@54280000 { }; };

+ vde@6001a000 { + core-supply = <&vdd_core>; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -419,18 +440,28 @@ sys_reg: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; };

- sm1 { + vdd_cpu: sm1 { regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; };

sm2_reg: sm2 { @@ -449,10 +480,16 @@ ldo1 { regulator-always-on; };

- ldo2 { + rtc_vdd: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; };

ldo3 { @@ -526,8 +563,13 @@ pmc@7000e400 { nvidia,sys-clock-req-active-high; };

+ memory-controller@7000f400 { + core-supply = <&vdd_core>; + }; + usb@c5000000 { status = "okay"; + core-supply = <&vdd_core>; };

usb-phy@c5000000 { @@ -538,6 +580,7 @@ usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + core-supply = <&vdd_core>; };

usb-phy@c5004000 { @@ -548,6 +591,7 @@ usb-phy@c5004000 {

usb@c5008000 { status = "okay"; + core-supply = <&vdd_core>; };

usb-phy@c5008000 { @@ -559,6 +603,7 @@ mmc@c8000000 { power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; + core-supply = <&vdd_core>; };

mmc@c8000400 { @@ -567,12 +612,14 @@ mmc@c8000400 { wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; + core-supply = <&vdd_core>; };

mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; + core-supply = <&vdd_core>; };

backlight: backlight {

Add voltage supplies to DVFS-capable devices in order to enable system-wide voltage scaling and allow CORE/RTC regulators to go lower.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../boot/dts/tegra20-acer-a500-picasso.dts | 30 +++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index b4ed88802387..5ab6872cd84c 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -60,7 +60,19 @@ linux,cma@30000000 { };

host1x@50000000 { + core-supply = <&vdd_core>; + + gr2d@54140000 { + core-supply = <&vdd_core>; + }; + + gr3d@54180000 { + core-supply = <&vdd_core>; + }; + dc@54200000 { + core-supply = <&vdd_core>; + rgb { status = "okay";

@@ -73,12 +85,17 @@ lcd_output: endpoint { }; };

+ dc@54240000 { + core-supply = <&vdd_core>; + }; + hdmi@54280000 { status = "okay";

vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; hdmi-supply = <&vdd_5v0_sys>; + core-supply = <&vdd_core>;

nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) @@ -86,6 +103,10 @@ hdmi@54280000 { }; };

+ vde@6001a000 { + core-supply = <&vdd_core>; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -565,7 +586,7 @@ sys_reg: sys {

vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1300000>; regulator-coupled-with = <&rtc_vdd &vdd_cpu>; regulator-coupled-max-spread = <170000 550000>; @@ -606,7 +627,7 @@ ldo1 {

rtc_vdd: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1300000>; regulator-coupled-with = <&vdd_core &vdd_cpu>; regulator-coupled-max-spread = <170000 550000>; @@ -696,6 +717,7 @@ usb@c5000000 { compatible = "nvidia,tegra20-udc"; status = "okay"; dr_mode = "peripheral"; + core-supply = <&vdd_core>; };

usb-phy@c5000000 { @@ -709,6 +731,7 @@ usb-phy@c5000000 {

usb@c5008000 { status = "okay"; + core-supply = <&vdd_core>; };

usb-phy@c5008000 { @@ -746,6 +769,7 @@ sdmmc1: mmc@c8000000 { non-removable;

mmc-pwrseq = <&brcm_wifi_pwrseq>; + core-supply = <&vdd_core>; vmmc-supply = <&vdd_3v3_sys>; vqmmc-supply = <&vdd_3v3_sys>;

@@ -764,6 +788,7 @@ sdmmc3: mmc@c8000400 { bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + core-supply = <&vdd_core>; vmmc-supply = <&vdd_3v3_sys>; vqmmc-supply = <&vdd_3v3_sys>; }; @@ -771,6 +796,7 @@ sdmmc3: mmc@c8000400 { sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; + core-supply = <&vdd_core>; vmmc-supply = <&vcore_emmc>; vqmmc-supply = <&vdd_3v3_sys>; non-removable;

Add voltage supplies to DVFS-capable devices in order to enable system-wide voltage scaling.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../tegra30-asus-nexus7-grouper-common.dtsi | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 261e266c61d8..2b405872ad2d 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -60,7 +60,19 @@ trustzone@bfe00000 { };

host1x@50000000 { + core-supply = <&vdd_core>; + + gr2d@54140000 { + core-supply = <&vdd_core>; + }; + + gr3d@54180000 { + core-supply = <&vdd_core>; + }; + dc@54200000 { + core-supply = <&vdd_core>; + rgb { status = "okay";

@@ -72,6 +84,10 @@ lcd_output: endpoint { }; }; }; + + dc@54240000 { + core-supply = <&vdd_core>; + }; };

gpio@6000d000 { @@ -90,6 +106,10 @@ init-low-power-mode { }; };

+ vde@6001a000 { + core-supply = <&vdd_core>; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -835,6 +855,7 @@ bluetooth {

pwm: pwm@7000a000 { status = "okay"; + core-supply = <&vdd_core>; };

i2c@7000c400 { @@ -994,6 +1015,7 @@ sdmmc3: mmc@78000400 {

mmc-pwrseq = <&brcm_wifi_pwrseq>; vmmc-supply = <&vdd_3v3_sys>; + core-supply = <&vdd_core>; vqmmc-supply = <&vdd_1v8>;

/* Azurewave AW-NH665 BCM4330 */ @@ -1018,6 +1040,7 @@ usb@7d000000 { compatible = "nvidia,tegra30-udc"; status = "okay"; dr_mode = "peripheral"; + core-supply = <&vdd_core>; };

usb-phy@7d000000 {