DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values) says that FPDLink is sensitive to jitter on the vout clock, and that low PLL M and N values result in more jitter than high M and N values.

This patch implements a workaround for the problem by changing the PLL setup to search for clocks starting from high M and N values, instead of low values. This should not cause any functional change, and only reduces the jitter.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com --- drivers/gpu/drm/omapdrm/dss/pll.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c index 0a76c89cdc2e..5e221302768b 100644 --- a/drivers/gpu/drm/omapdrm/dss/pll.c +++ b/drivers/gpu/drm/omapdrm/dss/pll.c @@ -215,8 +215,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, dss_pll_calc_func func, void *data) { const struct dss_pll_hw *hw = pll->hw; - int n, n_start, n_stop; - int m, m_start, m_stop; + int n, n_min, n_max; + int m, m_min, m_max; unsigned long fint, clkdco; unsigned long pll_hw_max; unsigned long fint_hw_min, fint_hw_max; @@ -226,21 +226,22 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, fint_hw_min = hw->fint_min; fint_hw_max = hw->fint_max;

- n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); - n_stop = min((unsigned)(clkin / fint_hw_min), hw->n_max); + n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); + n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max);

pll_max = pll_max ? pll_max : ULONG_MAX;

- for (n = n_start; n <= n_stop; ++n) { + /* Try to find high N & M to avoid jitter (DRA7 errata i886) */ + for (n = n_max; n >= n_min; --n) { fint = clkin / n;

- m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), + m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), 1ul); - m_stop = min3((unsigned)(pll_max / fint / 2), + m_max = min3((unsigned)(pll_max / fint / 2), (unsigned)(pll_hw_max / fint / 2), hw->m_max);

- for (m = m_start; m <= m_stop; ++m) { + for (m = m_max; m >= m_min; --m) { clkdco = 2 * m * fint;

if (func(n, m, fint, clkdco, data))

The driver only uses even dividers for hsdiv when pclk >= 100MHz, as odd dividers can create uneven duty cycle. However, while this holds true for some dividers like DISPC's LCK and PCK dividers, it is not actually true for hsdiv.

hsdiv always produces even duty cycle, so the constraint can be removed.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com Acked-by: Laurent Pinchart laurent.pinchart@ideasonboard.com --- drivers/gpu/drm/omapdrm/dss/dpi.c | 8 -------- 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c index e75162d26ac0..e0b0c5c24c55 100644 --- a/drivers/gpu/drm/omapdrm/dss/dpi.c +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c @@ -170,14 +170,6 @@ static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, { struct dpi_clk_calc_ctx *ctx = data;

- /* - * Odd dividers give us uneven duty cycle, causing problem when level - * shifted. So skip all odd dividers when the pixel clock is on the - * higher side. - */ - if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) - return false; - ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;

The clock source selection for the LCD outputs is too hardcoded at the moment. For example, LCD3 is set to use PLL2_1, and PLL2 doesn't exist on DRA72x SoCs.

There are quite many ways to configure the clocks, even using HDMI PLL for LCD outputs, but enabling full configuration of the clocks is rather tricky.

This patch improves the situation a bit by checking if the PLL about to be used exists, and if not, tries another one.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/dpi.c | 50 +++++++++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c index e0b0c5c24c55..51d90a8a61cd 100644 --- a/drivers/gpu/drm/omapdrm/dss/dpi.c +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c @@ -67,6 +67,45 @@ static struct dpi_data *dpi_get_data_from_pdev(struct platform_device *pdev) return dev_get_drvdata(&pdev->dev); }

+static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel) +{ + /* + * Possible clock sources: + * LCD1: FCK/PLL1_1/HDMI_PLL + * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) + * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) + */ + + switch (channel) { + case OMAP_DSS_CHANNEL_LCD: + { + if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_1)) + return DSS_CLK_SRC_PLL1_1; + break; + } + case OMAP_DSS_CHANNEL_LCD2: + { + if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) + return DSS_CLK_SRC_PLL1_3; + if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_3)) + return DSS_CLK_SRC_PLL2_3; + break; + } + case OMAP_DSS_CHANNEL_LCD3: + { + if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_1)) + return DSS_CLK_SRC_PLL2_1; + if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) + return DSS_CLK_SRC_PLL1_3; + break; + } + default: + break; + } + + return DSS_CLK_SRC_FCK; +} + static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) { /* @@ -107,16 +146,7 @@ static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) }

case OMAPDSS_VER_DRA7xx: - switch (channel) { - case OMAP_DSS_CHANNEL_LCD: - return DSS_CLK_SRC_PLL1_1; - case OMAP_DSS_CHANNEL_LCD2: - return DSS_CLK_SRC_PLL1_3; - case OMAP_DSS_CHANNEL_LCD3: - return DSS_CLK_SRC_PLL2_1; - default: - return DSS_CLK_SRC_FCK; - } + return dpi_get_clk_src_dra7xx(channel);

default: return DSS_CLK_SRC_FCK;

While implementing writeback support, odd behavior of WBDELAYCOUNT was observed with the combination of WB capture and HDMI. The result of the debugging was that the HDMI sync polarities are not set correctly.

The current code sets the sync polarities going from HDMI WP to DISPC according to the video mode used, which seems to work normally fine, but causes problems with WB as WB expects the syncs to be active-high.

This patch changes the HDMI sync polarities so that the DISPC always gets active-high syncs from HDMI WP, and the HDMI core gets sync polarities according to the used video mode.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com Acked-by: Laurent Pinchart laurent.pinchart@ideasonboard.com --- drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index b783d5a0750e..597ec9d87d1d 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c @@ -147,15 +147,17 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, struct videomode *vm) { u32 r; - bool vsync_pol, hsync_pol; + bool vsync_inv, hsync_inv; DSSDBG("Enter hdmi_wp_video_config_interface\n");

- vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH); - hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH); + vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW); + hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);

r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); - r = FLD_MOD(r, vsync_pol, 7, 7); - r = FLD_MOD(r, hsync_pol, 6, 6); + r = FLD_MOD(r, 1, 7, 7); /* VSYNC_POL to dispc active high */ + r = FLD_MOD(r, 1, 6, 6); /* HSYNC_POL to dispc active high */ + r = FLD_MOD(r, vsync_inv, 5, 5); /* CORE_VSYNC_INV */ + r = FLD_MOD(r, hsync_inv, 4, 4); /* CORE_HSYNC_INV */ r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3); r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);

omapdss_is_initialized() is used to find out if omapdss has been probed successfully. This patch moves the related code to the common omapdss-base module, so that the same support will be there for both omapdss and omapdss6.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/base.c | 14 ++++++++++++++ drivers/gpu/drm/omapdrm/dss/dss.c | 12 ++---------- drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++ 3 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/base.c b/drivers/gpu/drm/omapdrm/dss/base.c index 943030a7523c..03942097b9f1 100644 --- a/drivers/gpu/drm/omapdrm/dss/base.c +++ b/drivers/gpu/drm/omapdrm/dss/base.c @@ -1,6 +1,20 @@ #include <linux/kernel.h> #include <linux/module.h>

+static bool dss_initialized; + +void omapdss_set_is_initialized(bool set) +{ + dss_initialized = set; +} +EXPORT_SYMBOL(omapdss_set_is_initialized); + +bool omapdss_is_initialized(void) +{ + return dss_initialized; +} +EXPORT_SYMBOL(omapdss_is_initialized); + MODULE_AUTHOR("Tomi Valkeinen tomi.valkeinen@ti.com"); MODULE_DESCRIPTION("OMAP Display Subsystem Base"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 4e72d2fefb4d..5eb2f1260547 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -117,14 +117,6 @@ static const char * const dss_generic_clk_source_names[] = { [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", };

-static bool dss_initialized; - -bool omapdss_is_initialized(void) -{ - return dss_initialized; -} -EXPORT_SYMBOL(omapdss_is_initialized); - static inline void dss_write_reg(const struct dss_reg idx, u32 val) { __raw_writel(val, dss.base + idx.idx); @@ -1266,7 +1258,7 @@ static int dss_bind(struct device *dev)

pm_set_vt_switch(0);

- dss_initialized = true; + omapdss_set_is_initialized(true);

return 0;

@@ -1290,7 +1282,7 @@ static void dss_unbind(struct device *dev) { struct platform_device *pdev = to_platform_device(dev);

- dss_initialized = false; + omapdss_set_is_initialized(false);

component_unbind_all(&pdev->dev, NULL);

diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 5b3b961127bd..b644b12345c3 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -844,6 +844,8 @@ omapdss_of_get_first_endpoint(const struct device_node *parent); struct omap_dss_device * omapdss_of_find_source_for_first_ep(struct device_node *node);

+void omapdss_set_is_initialized(bool set); + u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void);

display.c uses dsi_get_pixel_size() which is implemented in the DSI driver, and we won't have that in the omapdss-base module, to which we want to move display.c

This patch changes display.c not to use dsi_get_pixel_size(). The call can be replaced with a simple check for OMAP_DSS_DSI_FMT_RGB565.

We can also make dsi_get_pixel_size() static as it's no longer used outside dsi.c.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/display.c | 6 +++--- drivers/gpu/drm/omapdrm/dss/dsi.c | 2 +- drivers/gpu/drm/omapdrm/dss/dss.h | 8 -------- 3 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c index 425a5a8dff8b..333ba284ef6d 100644 --- a/drivers/gpu/drm/omapdrm/dss/display.c +++ b/drivers/gpu/drm/omapdrm/dss/display.c @@ -55,10 +55,10 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) else return 16; case OMAP_DISPLAY_TYPE_DSI: - if (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) > 16) - return 24; - else + if (dssdev->panel.dsi_pix_fmt == OMAP_DSS_DSI_FMT_RGB565) return 16; + else + return 24; case OMAP_DISPLAY_TYPE_VENC: case OMAP_DISPLAY_TYPE_SDI: case OMAP_DISPLAY_TYPE_HDMI: diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 5e51a5649efb..f50d6fc0d92e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -527,7 +527,7 @@ static inline int wait_for_bit_change(struct platform_device *dsidev, return !value; }

-u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) +static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) { switch (fmt) { case OMAP_DSS_DSI_FMT_RGB888: diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 78f6fc75948b..4d568ac76826 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -315,15 +315,7 @@ void dsi_uninit_platform_driver(void); void dsi_dump_clocks(struct seq_file *s);

void dsi_irq_handler(void); -u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);

-#else -static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) -{ - WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n", - __func__); - return 0; -} #endif

/* DPI */

omapdrm still uses a few non-dispc functions: dss_feat_get_num_mgrs(), dss_feat_get_num_ovls() and dss_feat_get_supported_color_modes(). We want to provide omapdrm a single dispc_ops function pointer struct so that omapdrm will use either the current omapdss or the new omapdss6 driver depending on the platform.

Those three functions are really dispc functions, but are located in the dss_features.c for legacy reasons.

This patch adds similar functionss to the dispc, and changes omapdrm to use those new functions. Underneath the functions still call the functions from dss_feature.c.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 18 ++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/dss_features.c | 3 --- drivers/gpu/drm/omapdrm/dss/dss_features.h | 4 ++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 5 +++++ drivers/gpu/drm/omapdrm/omap_drv.c | 4 ++-- drivers/gpu/drm/omapdrm/omap_irq.c | 2 +- drivers/gpu/drm/omapdrm/omap_plane.c | 2 +- 7 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index d956e6266368..53d08dc4ef5a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -1135,6 +1135,18 @@ static u32 dispc_ovl_get_burst_size(enum omap_plane plane) return unit * 8; }

+enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane) +{ + return dss_feat_get_supported_color_modes(plane); +} +EXPORT_SYMBOL(dispc_ovl_get_color_modes); + +int dispc_get_num_ovls(void) +{ + return dss_feat_get_num_ovls(); +} +EXPORT_SYMBOL(dispc_get_num_ovls); + static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) { if (channel == OMAP_DSS_CHANNEL_DIGIT) @@ -2967,6 +2979,12 @@ void dispc_pck_free_enable(bool enable) REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); }

+int dispc_get_num_mgrs(void) +{ + return dss_feat_get_num_mgrs(); +} +EXPORT_SYMBOL(dispc_get_num_mgrs); + static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) { mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index ee5b93ce2763..26c29332b8e3 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -774,13 +774,11 @@ int dss_feat_get_num_mgrs(void) { return omap_current_dss_features->num_mgrs; } -EXPORT_SYMBOL(dss_feat_get_num_mgrs);

int dss_feat_get_num_ovls(void) { return omap_current_dss_features->num_ovls; } -EXPORT_SYMBOL(dss_feat_get_num_ovls);

unsigned long dss_feat_get_param_min(enum dss_range_param param) { @@ -806,7 +804,6 @@ enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane) { return omap_current_dss_features->supported_color_modes[plane]; } -EXPORT_SYMBOL(dss_feat_get_supported_color_modes);

enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index bb4b7f0e642b..bcec68ba8db9 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -104,4 +104,8 @@ void dss_features_init(enum omapdss_version version); enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);

+int dss_feat_get_num_mgrs(void); +int dss_feat_get_num_ovls(void); +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); + #endif diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index dab367ae5ca1..4d3999c18fa2 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -860,6 +860,9 @@ void dispc_free_irq(void *dev_id); int dispc_runtime_get(void); void dispc_runtime_put(void);

+int dispc_get_num_ovls(void); +int dispc_get_num_mgrs(void); + void dispc_mgr_enable(enum omap_channel channel, bool enable); u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); @@ -872,6 +875,7 @@ void dispc_mgr_set_timings(enum omap_channel channel, const struct videomode *vm); void dispc_mgr_setup(enum omap_channel channel, const struct omap_overlay_manager_info *info); +enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); u32 dispc_mgr_gamma_size(enum omap_channel channel); void dispc_mgr_set_gamma(enum omap_channel channel, const struct drm_color_lut *lut, @@ -883,6 +887,7 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel); int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, bool replication, const struct videomode *vm, bool mem_to_mem); +enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane);

enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);

diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index ce0a1c04403d..db0b485ef6c2 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -320,8 +320,8 @@ static int omap_modeset_init(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; struct omap_dss_device *dssdev = NULL; - int num_ovls = dss_feat_get_num_ovls(); - int num_mgrs = dss_feat_get_num_mgrs(); + int num_ovls = dispc_get_num_ovls(); + int num_mgrs = dispc_get_num_mgrs(); int num_crtcs; int i, id = 0; int ret; diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 59f21add6f19..a3fd6e8266c8 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -249,7 +249,7 @@ static const u32 omap_underflow_irqs[] = { int omap_drm_irq_install(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; - unsigned int num_mgrs = dss_feat_get_num_mgrs(); + unsigned int num_mgrs = dispc_get_num_mgrs(); unsigned int max_planes; unsigned int i; int ret; diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 386d90af70f7..1067695af401 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -352,7 +352,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,

omap_plane->nformats = omap_framebuffer_get_formats( omap_plane->formats, ARRAY_SIZE(omap_plane->formats), - dss_feat_get_supported_color_modes(id)); + dispc_ovl_get_color_modes(id)); omap_plane->id = id; omap_plane->name = plane_names[id];

This patch changes the current omapdss driver to fill a dispc_ops struct and set it to omapdss-base.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 53d08dc4ef5a..f871f69dab1a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -4359,6 +4359,42 @@ static void dispc_errata_i734_wa(void) REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4); }

+static const struct dispc_ops dispc_ops = { + .read_irqstatus = dispc_read_irqstatus, + .clear_irqstatus = dispc_clear_irqstatus, + .read_irqenable = dispc_read_irqenable, + .write_irqenable = dispc_write_irqenable, + + .request_irq = dispc_request_irq, + .free_irq = dispc_free_irq, + + .runtime_get = dispc_runtime_get, + .runtime_put = dispc_runtime_put, + + .get_num_ovls = dispc_get_num_ovls, + .get_num_mgrs = dispc_get_num_mgrs, + + .mgr_enable = dispc_mgr_enable, + .mgr_is_enabled = dispc_mgr_is_enabled, + .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq, + .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq, + .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq, + .mgr_go_busy = dispc_mgr_go_busy, + .mgr_go = dispc_mgr_go, + .mgr_set_lcd_config = dispc_mgr_set_lcd_config, + .mgr_set_timings = dispc_mgr_set_timings, + .mgr_setup = dispc_mgr_setup, + .mgr_get_supported_outputs = dispc_mgr_get_supported_outputs, + .mgr_gamma_size = dispc_mgr_gamma_size, + .mgr_set_gamma = dispc_mgr_set_gamma, + + .ovl_enable = dispc_ovl_enable, + .ovl_enabled = dispc_ovl_enabled, + .ovl_set_channel_out = dispc_ovl_set_channel_out, + .ovl_setup = dispc_ovl_setup, + .ovl_get_color_modes = dispc_ovl_get_color_modes, +}; + /* DISPC HW IP initialisation */ static int dispc_bind(struct device *dev, struct device *master, void *data) { @@ -4431,6 +4467,8 @@ static int dispc_bind(struct device *dev, struct device *master, void *data)

dispc_runtime_put();

+ dispc_set_ops(&dispc_ops); + dss_debugfs_create_file("dispc", dispc_dump_regs);

return 0; @@ -4443,6 +4481,8 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) static void dispc_unbind(struct device *dev, struct device *master, void *data) { + dispc_set_ops(NULL); + pm_runtime_disable(dev);

dispc_errata_i734_wa_fini();

omapdrm now uses dispc_ops instead of direct function calls so we can remove all EXPORT_SYMBOLs from dispc. Most of the functions can also be made static, but a few are used outside dispc.c.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 84 +++++++++++++---------------------- drivers/gpu/drm/omapdrm/dss/dss.h | 3 ++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 42 ------------------ 3 files changed, 33 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index f871f69dab1a..7104cffde176 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -306,6 +306,10 @@ static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);

+static void dispc_clear_irqstatus(u32 mask); +static bool dispc_mgr_is_enabled(enum omap_channel channel); +static void dispc_clear_irqstatus(u32 mask); + static inline void dispc_write_reg(const u16 idx, u32 val) { __raw_writel(val, dispc.base + idx); @@ -581,7 +585,6 @@ int dispc_runtime_get(void) WARN_ON(r < 0); return r < 0 ? r : 0; } -EXPORT_SYMBOL(dispc_runtime_get);

void dispc_runtime_put(void) { @@ -592,54 +595,48 @@ void dispc_runtime_put(void) r = pm_runtime_put_sync(&dispc.pdev->dev); WARN_ON(r < 0 && r != -ENOSYS); } -EXPORT_SYMBOL(dispc_runtime_put);

-u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) +static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) { return mgr_desc[channel].vsync_irq; } -EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);

-u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) +static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) { if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) return 0;

return mgr_desc[channel].framedone_irq; } -EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);

-u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) +static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) { return mgr_desc[channel].sync_lost_irq; } -EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);

u32 dispc_wb_get_framedone_irq(void) { return DISPC_IRQ_FRAMEDONEWB; }

-void dispc_mgr_enable(enum omap_channel channel, bool enable) +static void dispc_mgr_enable(enum omap_channel channel, bool enable) { mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); /* flush posted write */ mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); } -EXPORT_SYMBOL(dispc_mgr_enable);

static bool dispc_mgr_is_enabled(enum omap_channel channel) { return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); }

-bool dispc_mgr_go_busy(enum omap_channel channel) +static bool dispc_mgr_go_busy(enum omap_channel channel) { return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; } -EXPORT_SYMBOL(dispc_mgr_go_busy);

-void dispc_mgr_go(enum omap_channel channel) +static void dispc_mgr_go(enum omap_channel channel) { WARN_ON(!dispc_mgr_is_enabled(channel)); WARN_ON(dispc_mgr_go_busy(channel)); @@ -648,7 +645,6 @@ void dispc_mgr_go(enum omap_channel channel)

mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); } -EXPORT_SYMBOL(dispc_mgr_go);

bool dispc_wb_go_busy(void) { @@ -997,7 +993,7 @@ static void dispc_ovl_configure_burst_type(enum omap_plane plane, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); }

-void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) +static void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) { int shift; u32 val; @@ -1057,7 +1053,6 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) } dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); } -EXPORT_SYMBOL(dispc_ovl_set_channel_out);

static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) { @@ -1135,17 +1130,15 @@ static u32 dispc_ovl_get_burst_size(enum omap_plane plane) return unit * 8; }

-enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane) +static enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane) { return dss_feat_get_supported_color_modes(plane); } -EXPORT_SYMBOL(dispc_ovl_get_color_modes);

-int dispc_get_num_ovls(void) +static int dispc_get_num_ovls(void) { return dss_feat_get_num_ovls(); } -EXPORT_SYMBOL(dispc_get_num_ovls);

static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) { @@ -2829,9 +2822,8 @@ static int dispc_ovl_setup_common(enum omap_plane plane, return 0; }

-int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, - bool replication, const struct videomode *vm, - bool mem_to_mem) +static int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, + bool replication, const struct videomode *vm, bool mem_to_mem) { int r; enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); @@ -2853,7 +2845,6 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,

return r; } -EXPORT_SYMBOL(dispc_ovl_setup);

int dispc_wb_setup(const struct omap_dss_writeback_info *wi, bool mem_to_mem, const struct videomode *vm) @@ -2923,7 +2914,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, return r; }

-int dispc_ovl_enable(enum omap_plane plane, bool enable) +static int dispc_ovl_enable(enum omap_plane plane, bool enable) { DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);

@@ -2931,19 +2922,16 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable)

return 0; } -EXPORT_SYMBOL(dispc_ovl_enable);

-bool dispc_ovl_enabled(enum omap_plane plane) +static bool dispc_ovl_enabled(enum omap_plane plane) { return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); } -EXPORT_SYMBOL(dispc_ovl_enabled);

-enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) +static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) { return dss_feat_get_supported_outputs(channel); } -EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);

void dispc_wb_enable(bool enable) { @@ -2979,11 +2967,10 @@ void dispc_pck_free_enable(bool enable) REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); }

-int dispc_get_num_mgrs(void) +static int dispc_get_num_mgrs(void) { return dss_feat_get_num_mgrs(); } -EXPORT_SYMBOL(dispc_get_num_mgrs);

static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) { @@ -3033,7 +3020,7 @@ static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); }

-void dispc_mgr_setup(enum omap_channel channel, +static void dispc_mgr_setup(enum omap_channel channel, const struct omap_overlay_manager_info *info) { dispc_mgr_set_default_color(channel, info->default_color); @@ -3046,7 +3033,6 @@ void dispc_mgr_setup(enum omap_channel channel, dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); } } -EXPORT_SYMBOL(dispc_mgr_setup);

static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) { @@ -3107,7 +3093,7 @@ static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); }

-void dispc_mgr_set_lcd_config(enum omap_channel channel, +static void dispc_mgr_set_lcd_config(enum omap_channel channel, const struct dss_lcd_mgr_config *config) { dispc_mgr_set_io_pad_mode(config->io_pad_mode); @@ -3123,7 +3109,6 @@ void dispc_mgr_set_lcd_config(enum omap_channel channel,

dispc_mgr_set_lcd_type_tft(channel); } -EXPORT_SYMBOL(dispc_mgr_set_lcd_config);

static bool _dispc_mgr_size_ok(u16 width, u16 height) { @@ -3254,7 +3239,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, }

/* change name to mode? */ -void dispc_mgr_set_timings(enum omap_channel channel, +static void dispc_mgr_set_timings(enum omap_channel channel, const struct videomode *vm) { unsigned xtot, ytot; @@ -3301,7 +3286,6 @@ void dispc_mgr_set_timings(enum omap_channel channel,

dispc_mgr_set_size(channel, t.hactive, t.vactive); } -EXPORT_SYMBOL(dispc_mgr_set_timings);

static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, u16 pck_div) @@ -3781,25 +3765,22 @@ int dispc_mgr_get_clock_div(enum omap_channel channel, return 0; }

-u32 dispc_read_irqstatus(void) +static u32 dispc_read_irqstatus(void) { return dispc_read_reg(DISPC_IRQSTATUS); } -EXPORT_SYMBOL(dispc_read_irqstatus);

-void dispc_clear_irqstatus(u32 mask) +static void dispc_clear_irqstatus(u32 mask) { dispc_write_reg(DISPC_IRQSTATUS, mask); } -EXPORT_SYMBOL(dispc_clear_irqstatus);

-u32 dispc_read_irqenable(void) +static u32 dispc_read_irqenable(void) { return dispc_read_reg(DISPC_IRQENABLE); } -EXPORT_SYMBOL(dispc_read_irqenable);

-void dispc_write_irqenable(u32 mask) +static void dispc_write_irqenable(u32 mask) { u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);

@@ -3808,7 +3789,6 @@ void dispc_write_irqenable(u32 mask)

dispc_write_reg(DISPC_IRQENABLE, mask); } -EXPORT_SYMBOL(dispc_write_irqenable);

void dispc_enable_sidle(void) { @@ -3820,7 +3800,7 @@ void dispc_disable_sidle(void) REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ }

-u32 dispc_mgr_gamma_size(enum omap_channel channel) +static u32 dispc_mgr_gamma_size(enum omap_channel channel) { const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;

@@ -3829,7 +3809,6 @@ u32 dispc_mgr_gamma_size(enum omap_channel channel)

return gdesc->len; } -EXPORT_SYMBOL(dispc_mgr_gamma_size);

static void dispc_mgr_write_gamma_table(enum omap_channel channel) { @@ -3874,7 +3853,7 @@ static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, };

-void dispc_mgr_set_gamma(enum omap_channel channel, +static void dispc_mgr_set_gamma(enum omap_channel channel, const struct drm_color_lut *lut, unsigned int length) { @@ -3920,7 +3899,6 @@ void dispc_mgr_set_gamma(enum omap_channel channel, if (dispc.is_enabled) dispc_mgr_write_gamma_table(channel); } -EXPORT_SYMBOL(dispc_mgr_set_gamma);

static int dispc_init_gamma_tables(void) { @@ -4167,7 +4145,7 @@ static irqreturn_t dispc_irq_handler(int irq, void *arg) return dispc.user_handler(irq, dispc.user_data); }

-int dispc_request_irq(irq_handler_t handler, void *dev_id) +static int dispc_request_irq(irq_handler_t handler, void *dev_id) { int r;

@@ -4189,16 +4167,14 @@ int dispc_request_irq(irq_handler_t handler, void *dev_id)

return r; } -EXPORT_SYMBOL(dispc_request_irq);

-void dispc_free_irq(void *dev_id) +static void dispc_free_irq(void *dev_id) { devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);

dispc.user_handler = NULL; dispc.user_data = NULL; } -EXPORT_SYMBOL(dispc_free_irq);

/* * Workaround for errata i734 in DSS dispc diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index b0551f0090b4..9f8937ae35b4 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -337,6 +337,9 @@ int dispc_init_platform_driver(void) __init; void dispc_uninit_platform_driver(void); void dispc_dump_clocks(struct seq_file *s);

+int dispc_runtime_get(void); +void dispc_runtime_put(void); + void dispc_enable_sidle(void); void dispc_disable_sidle(void);

diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index a7c2981fa322..3e61f4b2d1ce 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -849,48 +849,6 @@ void omapdss_set_is_initialized(bool set); struct device_node *dss_of_port_get_parent_device(struct device_node *port); u32 dss_of_port_get_port_number(struct device_node *port);

-u32 dispc_read_irqstatus(void); -void dispc_clear_irqstatus(u32 mask); -u32 dispc_read_irqenable(void); -void dispc_write_irqenable(u32 mask); - -int dispc_request_irq(irq_handler_t handler, void *dev_id); -void dispc_free_irq(void *dev_id); - -int dispc_runtime_get(void); -void dispc_runtime_put(void); - -int dispc_get_num_ovls(void); -int dispc_get_num_mgrs(void); - -void dispc_mgr_enable(enum omap_channel channel, bool enable); -u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); -u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); -u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); -bool dispc_mgr_go_busy(enum omap_channel channel); -void dispc_mgr_go(enum omap_channel channel); -void dispc_mgr_set_lcd_config(enum omap_channel channel, - const struct dss_lcd_mgr_config *config); -void dispc_mgr_set_timings(enum omap_channel channel, - const struct videomode *vm); -void dispc_mgr_setup(enum omap_channel channel, - const struct omap_overlay_manager_info *info); -enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); -u32 dispc_mgr_gamma_size(enum omap_channel channel); -void dispc_mgr_set_gamma(enum omap_channel channel, - const struct drm_color_lut *lut, - unsigned int length); - -int dispc_ovl_enable(enum omap_plane plane, bool enable); -bool dispc_ovl_enabled(enum omap_plane plane); -void dispc_ovl_set_channel_out(enum omap_plane plane, - enum omap_channel channel); -int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, - bool replication, const struct videomode *vm, bool mem_to_mem); -enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane); - -enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); - struct dss_mgr_ops { int (*connect)(enum omap_channel channel, struct omap_dss_device *dst);

DSS uses "replication logic" to convert color components from smaller bit widths to bigger bit widths. Without replication logic, the color component would be shifted and the least significant bits would be left at 0, whereas with replication logic, the least significat bits will be filled with the most significant bit.

For some reason omapdrm leaves replication logic always to off, which, in the most common case, means that showing 16-bit RGB colors on 24-bit display gives a bit darker colors than expected.

The reset value of the replication logic bit is enabled, and it should always be set, as there's no practical reason to disable it. This patch removes the option to disable it from omapdrm, and always sets it to enabled in dispc.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 7 ++++--- drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 +-- drivers/gpu/drm/omapdrm/omap_plane.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index e9d98046a97f..83241052df6b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -2823,11 +2823,12 @@ static int dispc_ovl_setup_common(enum omap_plane plane, }

static int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, - bool replication, const struct videomode *vm, bool mem_to_mem) + const struct videomode *vm, bool mem_to_mem) { int r; enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); enum omap_channel channel; + const bool replication = true;

channel = dispc_ovl_get_channel_out(plane);

@@ -2854,7 +2855,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi, enum omap_plane plane = OMAP_DSS_WB; const int pos_x = 0, pos_y = 0; const u8 zorder = 0, global_alpha = 0; - const bool replication = false; + const bool replication = true; bool truncation; int in_width = vm->hactive; int in_height = vm->vactive; @@ -4288,7 +4289,7 @@ static void dispc_errata_i734_wa(void)

/* Setup and enable GFX plane */ dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD); - dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.vm, false); + dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false); dispc_ovl_enable(OMAP_DSS_GFX, true);

/* Set up and enable display manager for LCD1 */ diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 3e61f4b2d1ce..4545f1824e66 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -928,8 +928,7 @@ struct dispc_ops { void (*ovl_set_channel_out)(enum omap_plane plane, enum omap_channel channel); int (*ovl_setup)(enum omap_plane plane, const struct omap_overlay_info *oi, - bool replication, const struct videomode *vm, - bool mem_to_mem); + const struct videomode *vm, bool mem_to_mem);

enum omap_color_mode (*ovl_get_color_modes)(enum omap_plane plane); }; diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index bdd74692e0cd..78a92422ede1 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -128,7 +128,7 @@ static void omap_plane_atomic_update(struct drm_plane *plane, omap_crtc_channel(state->crtc));

/* and finally, update omapdss: */ - ret = priv->dispc_ops->ovl_setup(omap_plane->id, &info, false, + ret = priv->dispc_ops->ovl_setup(omap_plane->id, &info, omap_crtc_timings(state->crtc), false); if (ret) { dev_err(plane->dev->dev, "Failed to setup plane %s\n",

From: Peter Ujfalusi peter.ujfalusi@ti.com

When omapdss is loaded (all core components are in place) create a list of devices used in the display graph. This list later can be used by omapdrm via the omapdss_stack_is_ready() function to check that these components are loaded. Based on this information, omapdrm can defer probe in case when the omapdss stack is not ready yet.

Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/base.c | 107 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/dss.c | 1 + drivers/gpu/drm/omapdrm/dss/omapdss.h | 3 + 3 files changed, 111 insertions(+)

diff --git a/drivers/gpu/drm/omapdrm/dss/base.c b/drivers/gpu/drm/omapdrm/dss/base.c index 7dd447e6c4d7..13e91faaf7a6 100644 --- a/drivers/gpu/drm/omapdrm/dss/base.c +++ b/drivers/gpu/drm/omapdrm/dss/base.c @@ -1,9 +1,21 @@ #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/list.h> +#include "omapdss.h"

static bool dss_initialized; static const struct dispc_ops *ops;

+static struct list_head omapdss_comp_list; + +struct omapdss_comp_node { + struct list_head list; + struct device_node *node; + bool dss_core_component; +}; + void omapdss_set_is_initialized(bool set) { dss_initialized = set; @@ -28,6 +40,101 @@ const struct dispc_ops *dispc_get_ops(void) } EXPORT_SYMBOL(dispc_get_ops);

+static bool omapdss_list_contains(const struct device_node *node) +{ + struct omapdss_comp_node *comp; + + list_for_each_entry(comp, &omapdss_comp_list, list) { + if (comp->node == node) + return true; + } + + return false; +} + +static void omapdss_walk_device(struct device *dev, struct device_node *node, + bool dss_core) +{ + struct device_node *n; + struct omapdss_comp_node *comp = devm_kzalloc(dev, sizeof(*comp), + GFP_KERNEL); + + if (comp) { + comp->node = node; + comp->dss_core_component = dss_core; + list_add(&comp->list, &omapdss_comp_list); + } + + /* + * of_graph_get_remote_port_parent() prints an error if there is no + * port/ports node. To avoid that, check first that there's the node. + */ + n = of_get_child_by_name(node, "ports"); + if (!n) + n = of_get_child_by_name(node, "port"); + if (!n) + return; + + of_node_put(n); + + n = NULL; + while ((n = of_graph_get_next_endpoint(node, n)) != NULL) { + struct device_node *pn = of_graph_get_remote_port_parent(n); + + if (!pn) + continue; + + if (!of_device_is_available(pn) || omapdss_list_contains(pn)) { + of_node_put(pn); + continue; + } + + omapdss_walk_device(dev, pn, false); + } +} + +void omapdss_gather_components(struct device *dev) +{ + struct device_node *child; + + INIT_LIST_HEAD(&omapdss_comp_list); + + omapdss_walk_device(dev, dev->of_node, true); + + for_each_available_child_of_node(dev->of_node, child) { + if (!of_find_property(child, "compatible", NULL)) + continue; + + omapdss_walk_device(dev, child, true); + } +} +EXPORT_SYMBOL(omapdss_gather_components); + +static bool omapdss_component_is_loaded(struct omapdss_comp_node *comp) +{ + if (comp->dss_core_component) + return true; + if (omapdss_component_is_display(comp->node)) + return true; + if (omapdss_component_is_output(comp->node)) + return true; + + return false; +} + +bool omapdss_stack_is_ready(void) +{ + struct omapdss_comp_node *comp; + + list_for_each_entry(comp, &omapdss_comp_list, list) { + if (!omapdss_component_is_loaded(comp)) + return false; + } + + return true; +} +EXPORT_SYMBOL(omapdss_stack_is_ready); + MODULE_AUTHOR("Tomi Valkeinen tomi.valkeinen@ti.com"); MODULE_DESCRIPTION("OMAP Display Subsystem Base"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 5eb2f1260547..ceb483650f8c 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -1258,6 +1258,7 @@ static int dss_bind(struct device *dev)

pm_set_vt_switch(0);

+ omapdss_gather_components(dev); omapdss_set_is_initialized(true);

return 0; diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 7e1feb935137..d5c369bd565c 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -939,4 +939,7 @@ const struct dispc_ops *dispc_get_ops(void); bool omapdss_component_is_display(struct device_node *node); bool omapdss_component_is_output(struct device_node *node);

+bool omapdss_stack_is_ready(void); +void omapdss_gather_components(struct device *dev); + #endif /* __OMAP_DRM_DSS_H */

From: Peter Ujfalusi peter.ujfalusi@ti.com

Keep the panel_list ordered according to aliases. The DRM connectors will be created following the panel_list. By keeping the list ordered the DRM connectors will be created in the same order regardless of the driver probe order.

Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/display.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c index 94c012e0584b..26cb59be045e 100644 --- a/drivers/gpu/drm/omapdrm/dss/display.c +++ b/drivers/gpu/drm/omapdrm/dss/display.c @@ -83,6 +83,7 @@ static int disp_num_counter; int omapdss_register_display(struct omap_dss_device *dssdev) { struct omap_dss_driver *drv = dssdev->driver; + struct list_head *cur; int id;

/* @@ -118,7 +119,14 @@ int omapdss_register_display(struct omap_dss_device *dssdev) drv->get_timings = omapdss_default_get_timings;

mutex_lock(&panel_list_mutex); - list_add_tail(&dssdev->panel_list, &panel_list); + list_for_each(cur, &panel_list) { + struct omap_dss_device *ldev = list_entry(cur, + struct omap_dss_device, + panel_list); + if (strcmp(ldev->alias, dssdev->alias) > 0) + break; + } + list_add_tail(&dssdev->panel_list, cur); mutex_unlock(&panel_list_mutex); return 0; }

From: Peter Ujfalusi peter.ujfalusi@ti.com

The associated backlight device can be configured via DT by providing the phandle to the device.

If the backlight device is configured, the driver can manage the backligt along with the panel's power state, iow it can turn on the backlight when the panel is enabled and turn it off when the panel is disabled.

Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com Cc: devicetree@vger.kernel.org --- .../bindings/display/panel/panel-dpi.txt | 3 ++ drivers/gpu/drm/omapdrm/displays/panel-dpi.c | 37 ++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt index d4add13e592d..6b203bc4d932 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt +++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt @@ -9,6 +9,7 @@ Optional properties: - enable-gpios: panel enable gpio - reset-gpios: GPIO to control the RESET pin - vcc-supply: phandle of regulator that will be used to enable power to the display +- backlight: phandle of the backlight device

Required nodes: - "panel-timing" containing video timings @@ -22,6 +23,8 @@ lcd0: display@0 { compatible = "samsung,lte430wq-f0c", "panel-dpi"; label = "lcd";

+ backlight = <&backlight>; + port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c index 38003208d9ca..04ce8c5f2954 100644 --- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c +++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c @@ -16,6 +16,7 @@ #include <linux/of.h> #include <linux/of_gpio.h> #include <linux/regulator/consumer.h> +#include <linux/backlight.h>

#include <video/omap-panel-data.h> #include <video/of_display_timing.h> @@ -30,6 +31,8 @@ struct panel_drv_data {

struct videomode vm;

+ struct backlight_device *backlight; + /* used for non-DT boot, to be removed */ int backlight_gpio;

@@ -97,6 +100,11 @@ static int panel_dpi_enable(struct omap_dss_device *dssdev) if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 1);

+ if (ddata->backlight) { + ddata->backlight->props.power = FB_BLANK_UNBLANK; + backlight_update_status(ddata->backlight); + } + dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;

return 0; @@ -113,6 +121,11 @@ static void panel_dpi_disable(struct omap_dss_device *dssdev) if (gpio_is_valid(ddata->backlight_gpio)) gpio_set_value_cansleep(ddata->backlight_gpio, 0);

+ if (ddata->backlight) { + ddata->backlight->props.power = FB_BLANK_POWERDOWN; + backlight_update_status(ddata->backlight); + } + gpiod_set_value_cansleep(ddata->enable_gpio, 0); regulator_disable(ddata->vcc_supply);

@@ -209,6 +222,7 @@ static int panel_dpi_probe_of(struct platform_device *pdev) { struct panel_drv_data *ddata = platform_get_drvdata(pdev); struct device_node *node = pdev->dev.of_node; + struct device_node *bl_node; struct omap_dss_device *in; int r; struct display_timing timing; @@ -236,10 +250,19 @@ static int panel_dpi_probe_of(struct platform_device *pdev)

ddata->backlight_gpio = -ENOENT;

+ bl_node = of_parse_phandle(node, "backlight", 0); + if (bl_node) { + ddata->backlight = of_find_backlight_by_node(bl_node); + of_node_put(bl_node); + + if (!ddata->backlight) + return -EPROBE_DEFER; + } + r = of_get_display_timing(node, "panel-timing", &timing); if (r) { dev_err(&pdev->dev, "failed to get video timing\n"); - return r; + goto error_free_backlight; }

videomode_from_timing(&timing, &ddata->vm); @@ -247,12 +270,19 @@ static int panel_dpi_probe_of(struct platform_device *pdev) in = omapdss_of_find_source_for_first_ep(node); if (IS_ERR(in)) { dev_err(&pdev->dev, "failed to find video source\n"); - return PTR_ERR(in); + r = PTR_ERR(in); + goto error_free_backlight; }

ddata->in = in;

return 0; + +error_free_backlight: + if (ddata->backlight) + put_device(&ddata->backlight->dev); + + return r; }

static int panel_dpi_probe(struct platform_device *pdev) @@ -321,6 +351,9 @@ static int __exit panel_dpi_remove(struct platform_device *pdev)

omap_dss_put_device(in);

+ if (ddata->backlight) + put_device(&ddata->backlight->dev); + return 0; }

Instead of printing 0/1 for display flags like vsync high/low, use a tri-state print (-1/0/1) to indicate the "undefined" state.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/dss/dispc.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 83241052df6b..2e6a71dbc25d 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -3229,6 +3229,16 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, } }

+static int vm_flag_to_int(enum display_flags flags, enum display_flags high, + enum display_flags low) +{ + if (flags & high) + return 1; + if (flags & low) + return -1; + return 0; +} + /* change name to mode? */ static void dispc_mgr_set_timings(enum omap_channel channel, const struct videomode *vm) @@ -3258,11 +3268,11 @@ static void dispc_mgr_set_timings(enum omap_channel channel, t.hsync_len, t.hfront_porch, t.hback_porch, t.vsync_len, t.vfront_porch, t.vback_porch); DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", - !!(t.flags & DISPLAY_FLAGS_VSYNC_HIGH), - !!(t.flags & DISPLAY_FLAGS_HSYNC_HIGH), - !!(t.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE), - !!(t.flags & DISPLAY_FLAGS_DE_HIGH), - !!(t.flags & DISPLAY_FLAGS_SYNC_POSEDGE)); + vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW), + vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW), + vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE), + vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW), + vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE));

DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); } else {

Use drm_atomic_helper_shutdown() to ensure that all crtcs are disabled when unloading the driver.

Signed-off-by: Tomi Valkeinen tomi.valkeinen@ti.com --- drivers/gpu/drm/omapdrm/omap_drv.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index ad8d16cf819c..7b917c0c1a27 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -865,6 +865,8 @@ static int pdev_remove(struct platform_device *pdev) if (priv->fbdev) omap_fbdev_free(ddev);

+ drm_atomic_helper_shutdown(ddev); + drm_mode_config_cleanup(ddev);

omap_drm_irq_uninstall(ddev);