This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next This series also depends on component support in mmsys[1]: - [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2 - [v4,07/10] soc: mediatek: mmsys: add component POSTMASK - [v4,08/10] soc: mediatek: mmsys: add component RDMA4
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-7...
Change since v3: - change several function to rebase to mediatek-drm-next - drop pm runtime patches due to it's not related to mt8192 support - fix review comments in v3
Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch
Yongqiang Niu (8): drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase drm/mediatek: separate ccorr module drm/mediatek: add matrix bits private data for ccorr soc: mediatek: add mtk mutex support for MT8192 drm/mediatek: add support for mediatek SOC MT8192
drivers/gpu/drm/mediatek/Makefile | 4 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 244 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 17 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 37 +++ drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 162 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 108 ++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 52 +++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 + drivers/soc/mediatek/mtk-mutex.c | 35 +++ 11 files changed, 572 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 5b7fcedb9f9a8..ccfaada998cf5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -479,6 +479,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ + mtk_disp_postmask.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ mtk_drm_ddp_comp.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev); + void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/* + * SPDX-License-Identifier: + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030 + +struct mtk_disp_postmask_data { + u32 reserved; +}; + +/** + * struct mtk_disp_postmask - DISP_postmask driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_postmask { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_postmask_data *data; +}; + +int mtk_postmask_clk_enable(struct device *dev) +{ + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev); + + return clk_prepare_enable(postmask->clk); +} + +void mtk_postmask_clk_disable(struct device *dev) +{ + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev); + + clk_disable_unprepare(postmask->clk); +} + +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs, + DISP_POSTMASK_SIZE); + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg, + postmask->regs, DISP_POSTMASK_CFG); +} + +void mtk_postmask_start(struct device *dev) +{ + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev); + + writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN); +} + +void mtk_postmask_stop(struct device *dev) +{ + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev); + + writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN); +} + +static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{ + return 0; +} + +static void mtk_disp_postmask_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_postmask_component_ops = { + .bind = mtk_disp_postmask_bind, + .unbind = mtk_disp_postmask_unbind, +}; + +static int mtk_disp_postmask_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_postmask *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get postmask clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap postmask\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + pm_runtime_enable(dev); + + ret = component_add(dev, &mtk_disp_postmask_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_postmask_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_postmask_component_ops); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = { + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match); + +struct platform_driver mtk_disp_postmask_driver = { + .probe = mtk_disp_postmask_probe, + .remove = mtk_disp_postmask_remove, + .driver = { + .name = "mediatek-disp-postmask", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_postmask_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = { + .clk_enable = mtk_postmask_clk_enable, + .clk_disable = mtk_postmask_clk_disable, + .config = mtk_postmask_config, + .start = mtk_postmask_start, + .stop = mtk_postmask_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls", + [MTK_DISP_POSTMASK] = "postmask", };
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || + type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have + * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have * separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ @@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || + comp_type == MTK_DISP_POSTMASK || comp_type == MTK_DISP_RDMA || comp_type == MTK_DSI || comp_type == MTK_DPI) { @@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, + &mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \
mtk_disp_postmask.o \diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);+void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/*
- SPDX-License-Identifier:
- Copyright (c) 2020 MediaTek Inc.
2021
- */
+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"
+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030
+struct mtk_disp_postmask_data {
- u32 reserved;
+};
Useless, so remove.
+/**
- struct mtk_disp_postmask - DISP_postmask driver structure
- @ddp_comp - structure containing type enum and hardware resources
- @crtc - associated crtc to report irq events to
- */
+struct mtk_disp_postmask {
- struct clk *clk;
- void __iomem *regs;
- struct cmdq_client_reg cmdq_reg;
- const struct mtk_disp_postmask_data *data;
+};
+int mtk_postmask_clk_enable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- return clk_prepare_enable(postmask->clk);
+}
+void mtk_postmask_clk_disable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- clk_disable_unprepare(postmask->clk);
+}
+void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
DISP_POSTMASK_SIZE);- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
postmask->regs, DISP_POSTMASK_CFG);+}
+void mtk_postmask_start(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+void mtk_postmask_stop(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{
- return 0;
+}
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
void *data)+{ +}
+static const struct component_ops mtk_disp_postmask_component_ops = {
- .bind = mtk_disp_postmask_bind,
- .unbind = mtk_disp_postmask_unbind,
+};
+static int mtk_disp_postmask_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct mtk_disp_postmask *priv;
- struct resource *res;
- int ret;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
return -ENOMEM;- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk)) {
dev_err(dev, "failed to get postmask clk\n");return PTR_ERR(priv->clk);- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap postmask\n");return PTR_ERR(priv->regs);- }
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
- if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");+#endif
- priv->data = of_device_get_match_data(dev);
- platform_set_drvdata(pdev, priv);
- pm_runtime_enable(dev);
Why this?
- ret = component_add(dev, &mtk_disp_postmask_component_ops);
- if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);- return ret;
+}
+static int mtk_disp_postmask_remove(struct platform_device *pdev) +{
- component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
- pm_runtime_disable(&pdev->dev);
- return 0;
+}
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
- {},
+}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+struct platform_driver mtk_disp_postmask_driver = {
- .probe = mtk_disp_postmask_probe,
- .remove = mtk_disp_postmask_remove,
- .driver = {
.name = "mediatek-disp-postmask",.owner = THIS_MODULE,.of_match_table = mtk_disp_postmask_driver_dt_match,- },
+}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_postmask_clk_enable,
.clk_disable = mtk_postmask_clk_disable,
tab.
- .config = mtk_postmask_config,
- .start = mtk_postmask_start,
- .stop = mtk_postmask_stop,
+};
static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",
- [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
- [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
Make other row the same indent.
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA ||
type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL ||diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,
- MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/*
* Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
* Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have*/
- separate component platform drivers and initialize their own
- DDP component structure. The others are initialized here.
@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_POSTMASK ||@@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver,
- &mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \
mtk_disp_postmask.o \diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);+void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/*
- SPDX-License-Identifier:
- Copyright (c) 2020 MediaTek Inc.
2021
- */
+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"
+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030
+struct mtk_disp_postmask_data {
- u32 reserved;
+};
Useless, so remove.
+/**
- struct mtk_disp_postmask - DISP_postmask driver structure
- @ddp_comp - structure containing type enum and hardware resources
- @crtc - associated crtc to report irq events to
- */
+struct mtk_disp_postmask {
- struct clk *clk;
- void __iomem *regs;
- struct cmdq_client_reg cmdq_reg;
- const struct mtk_disp_postmask_data *data;
+};
+int mtk_postmask_clk_enable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- return clk_prepare_enable(postmask->clk);
+}
+void mtk_postmask_clk_disable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- clk_disable_unprepare(postmask->clk);
+}
+void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
DISP_POSTMASK_SIZE);- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
postmask->regs, DISP_POSTMASK_CFG);+}
+void mtk_postmask_start(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+void mtk_postmask_stop(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{
- return 0;
+}
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
void *data)+{ +}
+static const struct component_ops mtk_disp_postmask_component_ops = {
- .bind = mtk_disp_postmask_bind,
- .unbind = mtk_disp_postmask_unbind,
+};
+static int mtk_disp_postmask_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct mtk_disp_postmask *priv;
- struct resource *res;
- int ret;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
return -ENOMEM;- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk)) {
dev_err(dev, "failed to get postmask clk\n");return PTR_ERR(priv->clk);- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap postmask\n");return PTR_ERR(priv->regs);- }
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
- if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");+#endif
- priv->data = of_device_get_match_data(dev);
- platform_set_drvdata(pdev, priv);
- pm_runtime_enable(dev);
Why this?
if add power domain information in dts, we need this to make sure display power domain will be off after module clock off.
- ret = component_add(dev, &mtk_disp_postmask_component_ops);
- if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);- return ret;
+}
+static int mtk_disp_postmask_remove(struct platform_device *pdev) +{
- component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
- pm_runtime_disable(&pdev->dev);
- return 0;
+}
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
- {},
+}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+struct platform_driver mtk_disp_postmask_driver = {
- .probe = mtk_disp_postmask_probe,
- .remove = mtk_disp_postmask_remove,
- .driver = {
.name = "mediatek-disp-postmask",.owner = THIS_MODULE,.of_match_table = mtk_disp_postmask_driver_dt_match,- },
+}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_postmask_clk_enable,
.clk_disable = mtk_postmask_clk_disable,tab.
- .config = mtk_postmask_config,
- .start = mtk_postmask_start,
- .stop = mtk_postmask_stop,
+};
static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",
- [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
- [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
Make other row the same indent.
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA ||
type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL ||diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,
- MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/*
* Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
* Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have*/
- separate component platform drivers and initialize their own
- DDP component structure. The others are initialized here.
@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_POSTMASK ||@@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver,
- &mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \
mtk_disp_postmask.o \diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);+void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/*
- SPDX-License-Identifier:
- Copyright (c) 2020 MediaTek Inc.
2021
- */
+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"
+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030
+struct mtk_disp_postmask_data {
- u32 reserved;
+};
Useless, so remove.
+/**
- struct mtk_disp_postmask - DISP_postmask driver structure
- @ddp_comp - structure containing type enum and hardware resources
- @crtc - associated crtc to report irq events to
- */
+struct mtk_disp_postmask {
- struct clk *clk;
- void __iomem *regs;
- struct cmdq_client_reg cmdq_reg;
- const struct mtk_disp_postmask_data *data;
+};
+int mtk_postmask_clk_enable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- return clk_prepare_enable(postmask->clk);
+}
+void mtk_postmask_clk_disable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- clk_disable_unprepare(postmask->clk);
+}
+void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
DISP_POSTMASK_SIZE);- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
postmask->regs, DISP_POSTMASK_CFG);+}
+void mtk_postmask_start(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+void mtk_postmask_stop(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{
- return 0;
+}
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
void *data)+{ +}
+static const struct component_ops mtk_disp_postmask_component_ops = {
- .bind = mtk_disp_postmask_bind,
- .unbind = mtk_disp_postmask_unbind,
+};
+static int mtk_disp_postmask_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct mtk_disp_postmask *priv;
- struct resource *res;
- int ret;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
return -ENOMEM;- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk)) {
dev_err(dev, "failed to get postmask clk\n");return PTR_ERR(priv->clk);- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap postmask\n");return PTR_ERR(priv->regs);- }
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
- if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");+#endif
- priv->data = of_device_get_match_data(dev);
- platform_set_drvdata(pdev, priv);
- pm_runtime_enable(dev);
Why this?
if add power domain information in dts, we need this to make sure display power domain will be off after module clock off.
Please align all sub driver. All do or all not do.
- ret = component_add(dev, &mtk_disp_postmask_component_ops);
- if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);- return ret;
+}
+static int mtk_disp_postmask_remove(struct platform_device *pdev) +{
- component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
- pm_runtime_disable(&pdev->dev);
- return 0;
+}
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
- {},
+}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+struct platform_driver mtk_disp_postmask_driver = {
- .probe = mtk_disp_postmask_probe,
- .remove = mtk_disp_postmask_remove,
- .driver = {
.name = "mediatek-disp-postmask",.owner = THIS_MODULE,.of_match_table = mtk_disp_postmask_driver_dt_match,- },
+}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_postmask_clk_enable,
.clk_disable = mtk_postmask_clk_disable,tab.
- .config = mtk_postmask_config,
- .start = mtk_postmask_start,
- .stop = mtk_postmask_stop,
+};
static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",
- [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
- [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
Make other row the same indent.
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA ||
type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL ||diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,
- MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/*
* Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
* Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have*/
- separate component platform drivers and initialize their own
- DDP component structure. The others are initialized here.
@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_POSTMASK ||@@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver,
- &mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
On Fri, 2021-01-29 at 16:35 +0800, CK Hu wrote:
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \
mtk_disp_postmask.o \diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);+void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/*
- SPDX-License-Identifier:
- Copyright (c) 2020 MediaTek Inc.
2021
- */
+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"
+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030
+struct mtk_disp_postmask_data {
- u32 reserved;
+};
Useless, so remove.
+/**
- struct mtk_disp_postmask - DISP_postmask driver structure
- @ddp_comp - structure containing type enum and hardware resources
- @crtc - associated crtc to report irq events to
- */
+struct mtk_disp_postmask {
- struct clk *clk;
- void __iomem *regs;
- struct cmdq_client_reg cmdq_reg;
- const struct mtk_disp_postmask_data *data;
+};
+int mtk_postmask_clk_enable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- return clk_prepare_enable(postmask->clk);
+}
+void mtk_postmask_clk_disable(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- clk_disable_unprepare(postmask->clk);
+}
+void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
DISP_POSTMASK_SIZE);- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
postmask->regs, DISP_POSTMASK_CFG);+}
+void mtk_postmask_start(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+void mtk_postmask_stop(struct device *dev) +{
- struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
- writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{
- return 0;
+}
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
void *data)+{ +}
+static const struct component_ops mtk_disp_postmask_component_ops = {
- .bind = mtk_disp_postmask_bind,
- .unbind = mtk_disp_postmask_unbind,
+};
+static int mtk_disp_postmask_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct mtk_disp_postmask *priv;
- struct resource *res;
- int ret;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
return -ENOMEM;- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk)) {
dev_err(dev, "failed to get postmask clk\n");return PTR_ERR(priv->clk);- }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap postmask\n");return PTR_ERR(priv->regs);- }
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
- if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");+#endif
- priv->data = of_device_get_match_data(dev);
- platform_set_drvdata(pdev, priv);
- pm_runtime_enable(dev);
Why this?
if add power domain information in dts, we need this to make sure display power domain will be off after module clock off.
Please align all sub driver. All do or all not do.
add for gamma and color https://patchwork.kernel.org/project/linux-mediatek/patch/1610351031-21133-1... https://patchwork.kernel.org/project/linux-mediatek/patch/1610351031-21133-1...
ovl and rdma in iommu series.
- ret = component_add(dev, &mtk_disp_postmask_component_ops);
- if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);- return ret;
+}
+static int mtk_disp_postmask_remove(struct platform_device *pdev) +{
- component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
- pm_runtime_disable(&pdev->dev);
- return 0;
+}
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
- {},
+}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+struct platform_driver mtk_disp_postmask_driver = {
- .probe = mtk_disp_postmask_probe,
- .remove = mtk_disp_postmask_remove,
- .driver = {
.name = "mediatek-disp-postmask",.owner = THIS_MODULE,.of_match_table = mtk_disp_postmask_driver_dt_match,- },
+}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_postmask_clk_enable,
.clk_disable = mtk_postmask_clk_disable,tab.
- .config = mtk_postmask_config,
- .start = mtk_postmask_start,
- .stop = mtk_postmask_stop,
+};
static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",
- [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
- [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
Make other row the same indent.
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, @@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA ||
type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL ||diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,
- MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/*
* Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
* Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have*/
- separate component platform drivers and initialize their own
- DDP component structure. The others are initialized here.
@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_POSTMASK ||@@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver,
- &mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
On Fri, Jan 29, 2021 at 4:49 PM Yongqiang Niu yongqiang.niu@mediatek.com wrote:
On Fri, 2021-01-29 at 16:35 +0800, CK Hu wrote:
On Fri, 2021-01-29 at 16:32 +0800, Yongqiang Niu wrote:
On Fri, 2021-01-29 at 16:18 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..13a0eafabf9c0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \
mtk_disp_postmask.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ mtk_drm_ddp_comp.o \diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 02191010699f8..d74e85db3fcdf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev); +void mtk_postmask_clk_disable(struct device *dev); +void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);+void mtk_postmask_start(struct device *dev); +void mtk_postmask_stop(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c new file mode 100644 index 0000000000000..d640cef9c15a4 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -0,0 +1,161 @@ +/*
- SPDX-License-Identifier:
- Copyright (c) 2020 MediaTek Inc.
2021
- */
+#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
+#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h"
+#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030
+struct mtk_disp_postmask_data {
u32 reserved;+};
Useless, so remove.
+/**
- struct mtk_disp_postmask - DISP_postmask driver structure
- @ddp_comp - structure containing type enum and hardware resources
- @crtc - associated crtc to report irq events to
- */
+struct mtk_disp_postmask {
struct clk *clk;void __iomem *regs;struct cmdq_client_reg cmdq_reg;const struct mtk_disp_postmask_data *data;+};
+int mtk_postmask_clk_enable(struct device *dev) +{
struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);return clk_prepare_enable(postmask->clk);+}
+void mtk_postmask_clk_disable(struct device *dev) +{
struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);clk_disable_unprepare(postmask->clk);+}
+void mtk_postmask_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,DISP_POSTMASK_SIZE);mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,postmask->regs, DISP_POSTMASK_CFG);+}
+void mtk_postmask_start(struct device *dev) +{
struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);+}
+void mtk_postmask_stop(struct device *dev) +{
struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);+}
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data) +{
return 0;+}
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
void *data)+{ +}
+static const struct component_ops mtk_disp_postmask_component_ops = {
.bind = mtk_disp_postmask_bind,.unbind = mtk_disp_postmask_unbind,+};
+static int mtk_disp_postmask_probe(struct platform_device *pdev) +{
struct device *dev = &pdev->dev;struct mtk_disp_postmask *priv;struct resource *res;int ret;priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);if (!priv)return -ENOMEM;priv->clk = devm_clk_get(dev, NULL);if (IS_ERR(priv->clk)) {dev_err(dev, "failed to get postmask clk\n");return PTR_ERR(priv->clk);}res = platform_get_resource(pdev, IORESOURCE_MEM, 0);priv->regs = devm_ioremap_resource(dev, res);if (IS_ERR(priv->regs)) {dev_err(dev, "failed to ioremap postmask\n");return PTR_ERR(priv->regs);}+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);if (ret)dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");+#endif
priv->data = of_device_get_match_data(dev);platform_set_drvdata(pdev, priv);pm_runtime_enable(dev);Why this?
if add power domain information in dts, we need this to make sure display power domain will be off after module clock off.
Please align all sub driver. All do or all not do.
add for gamma and color https://patchwork.kernel.org/project/linux-mediatek/patch/1610351031-21133-1... https://patchwork.kernel.org/project/linux-mediatek/patch/1610351031-21133-1...
ovl and rdma in iommu series.
https://patchwork.kernel.org/project/linux-mediatek/patch/1610351031-21133-1...
CK suggested to move to another series.
ret = component_add(dev, &mtk_disp_postmask_component_ops);if (ret)dev_err(dev, "Failed to add component: %d\n", ret);return ret;+}
+static int mtk_disp_postmask_remove(struct platform_device *pdev) +{
component_del(&pdev->dev, &mtk_disp_postmask_component_ops);pm_runtime_disable(&pdev->dev);return 0;+}
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
{},+}; +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+struct platform_driver mtk_disp_postmask_driver = {
.probe = mtk_disp_postmask_probe,.remove = mtk_disp_postmask_remove,.driver = {.name = "mediatek-disp-postmask",.owner = THIS_MODULE,.of_match_table = mtk_disp_postmask_driver_dt_match,},+}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index ccfaada998cf5..6c539783118dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -415,6 +415,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, };
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
.clk_enable = mtk_postmask_clk_enable,.clk_disable = mtk_postmask_clk_disable,tab.
.config = mtk_postmask_config,.start = mtk_postmask_start,.stop = mtk_postmask_stop,+};
static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -450,6 +458,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls",
[MTK_DISP_POSTMASK] = "postmask",};
struct mtk_ddp_comp_match { @@ -480,6 +489,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },Make other row the same indent.
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },@@ -603,6 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA ||
type == MTK_DISP_POSTMASK || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL ||diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI,
MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD,diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..d99afc8528684 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,7 +531,7 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/*
* Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
* Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have * separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */@@ -539,6 +539,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_POSTMASK || comp_type == MTK_DISP_RDMA || comp_type == MTK_DSI || comp_type == MTK_DPI) {@@ -637,6 +638,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver,
&mtk_disp_postmask_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, &mtk_drm_platform_driver,diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..7e7b28e32aa2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -49,6 +49,7 @@ struct mtk_drm_private { extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; +extern struct platform_driver mtk_disp_postmask_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver;
From: Yongqiang Niu yongqiang.niu@mediatek.com
This patch add component RDMA4
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6c539783118dd..543cbfc9c5d85 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -496,6 +496,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
From: Yongqiang Niu yongqiang.niu@mediatek.com
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index da7e38a28759b..961f87f8d4d15 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -24,6 +24,7 @@ #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 +#define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data { unsigned int gmc_bits; unsigned int layer_nr; bool fmt_rgb565_is_0; + bool smi_id_en; };
/** @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+ if (ovl->data->smi_id_en) { + unsigned int reg; + + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); + reg = reg | OVL_LAYER_SMI_ID_EN; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + } writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); }
@@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev) struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); + if (ovl->data->smi_id_en) { + unsigned int reg; + + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); + reg = reg & ~OVL_LAYER_SMI_ID_EN; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + } + }
void mtk_ovl_config(struct device *dev, unsigned int w,
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index da7e38a28759b..961f87f8d4d15 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -24,6 +24,7 @@ #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 +#define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data { unsigned int gmc_bits; unsigned int layer_nr; bool fmt_rgb565_is_0;
- bool smi_id_en;
};
/** @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
- if (ovl->data->smi_id_en) {
unsigned int reg;reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);reg = reg | OVL_LAYER_SMI_ID_EN;writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);- } writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
}
@@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev) struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
- if (ovl->data->smi_id_en) {
unsigned int reg;reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);reg = reg & ~OVL_LAYER_SMI_ID_EN;writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);- }
}
void mtk_ovl_config(struct device *dev, unsigned int w,
Hi, Hsin-Yi:
CK Hu ck.hu@mediatek.com 於 2021年1月29日 週五 下午4:21寫道：
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu ck.hu@mediatek.com
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?...
Regards, Chun-Kuang.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index da7e38a28759b..961f87f8d4d15 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -24,6 +24,7 @@ #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 +#define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data { unsigned int gmc_bits; unsigned int layer_nr; bool fmt_rgb565_is_0;
bool smi_id_en;};
/** @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
if (ovl->data->smi_id_en) {unsigned int reg;reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);reg = reg | OVL_LAYER_SMI_ID_EN;writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);} writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);}
@@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev) struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
if (ovl->data->smi_id_en) {unsigned int reg;reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);reg = reg & ~OVL_LAYER_SMI_ID_EN;writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);}}
void mtk_ovl_config(struct device *dev, unsigned int w,
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
From: Yongqiang Niu yongqiang.niu@mediatek.com
ccorr ctm matrix bits will be different in mt8192
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 242 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 13a0eafabf9c0..f119bef6d6e66 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0
-mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_postmask.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..0c68090eb1e92 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,222 @@ +/* + * SPDX-License-Identifier: + * + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + pm_runtime_enable(dev); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index d74e85db3fcdf..8282497ed1391 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h"
+void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 543cbfc9c5d85..6192c3ef926da 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030
-#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -236,82 +222,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); }
-static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -350,8 +260,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { };
static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -612,6 +522,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, }
if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DISP_POSTMASK || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index d99afc8528684..3da8996438dbc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node);
/* - * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -635,6 +636,7 @@ static struct platform_driver mtk_drm_platform_driver = { };
static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 7e7b28e32aa2f..b49062364c3d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; };
+extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver;
Hi, Hsin-Yi:
Hsin-Yi Wang hsinyi@chromium.org 於 2021年1月29日 週五 下午3:35寫道：
From: Yongqiang Niu yongqiang.niu@mediatek.com
ccorr ctm matrix bits will be different in mt8192
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 242 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
[snip]
+void mtk_ccorr_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)+{
struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,DISP_CCORR_SIZE);
You change w, h position here. Separate this modification to another patch.
mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,DISP_CCORR_CFG);+}
[snip]
-static void mtk_ccorr_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt)-{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE);mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG);-}
From: Yongqiang Niu yongqiang.niu@mediatek.com
matrix bits of mt8183 is 12 matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 0c68090eb1e92..1c7163a12f3b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -31,8 +31,10 @@ #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090
+#define CCORR_MATRIX_BITS 12 + struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; };
/** @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits;
if (!blob) return; @@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) ctm = (struct drm_color_ctm *)blob->data; input = ctm->matrix;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++) + if (ccorr->data) + matrix_bits = ccorr->data->matrix_bits; + else + matrix_bits = CCORR_MATRIX_BITS; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + if (matrix_bits > CCORR_MATRIX_BITS) + coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS); + }
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; }
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = CCORR_MATRIX_BITS, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
matrix bits of mt8183 is 12 matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 0c68090eb1e92..1c7163a12f3b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -31,8 +31,10 @@ #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090
+#define CCORR_MATRIX_BITS 12
struct mtk_disp_ccorr_data {
- u32 reserved;
- u32 matrix_bits;
};
/** @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL;
u32 matrix_bits;
if (!blob) return;
@@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) ctm = (struct drm_color_ctm *)blob->data; input = ctm->matrix;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++)
- if (ccorr->data)
matrix_bits = ccorr->data->matrix_bits;- else
matrix_bits = CCORR_MATRIX_BITS;- for (i = 0; i < ARRAY_SIZE(coeffs); i++) { coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
if (matrix_bits > CCORR_MATRIX_BITS)coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);
I think format of MT8192 ccorr coeffs is s1.11, after mtk_ctm_s31_32_to_s1_10(), you lose one bit precision. So modify mtk_ctm_s31_32_to_s1_10() to get maximum precision.
Regards, CK
}
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
@@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; }
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
- .matrix_bits = CCORR_MATRIX_BITS,
+};
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
- { .compatible = "mediatek,mt8183-disp-ccorr"},
- { .compatible = "mediatek,mt8183-disp-ccorr",
.data = &mt8183_ccorr_driver_data},}; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
On Fri, 2021-01-29 at 16:40 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
matrix bits of mt8183 is 12 matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 0c68090eb1e92..1c7163a12f3b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -31,8 +31,10 @@ #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090
+#define CCORR_MATRIX_BITS 12
struct mtk_disp_ccorr_data {
- u32 reserved;
- u32 matrix_bits;
};
/** @@ -116,6 +118,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL;
u32 matrix_bits;
if (!blob) return;
@@ -123,8 +126,16 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) ctm = (struct drm_color_ctm *)blob->data; input = ctm->matrix;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++)
- if (ccorr->data)
matrix_bits = ccorr->data->matrix_bits;- else
matrix_bits = CCORR_MATRIX_BITS;- for (i = 0; i < ARRAY_SIZE(coeffs); i++) { coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
if (matrix_bits > CCORR_MATRIX_BITS)coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);I think format of MT8192 ccorr coeffs is s1.11, after mtk_ctm_s31_32_to_s1_10(), you lose one bit precision. So modify mtk_ctm_s31_32_to_s1_10() to get maximum precision.
Regards, CK
mt8183 s2.10, default value 1024 mt8192 s2.11, default value 2048
}
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
@@ -205,8 +216,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; }
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
- .matrix_bits = CCORR_MATRIX_BITS,
+};
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
- { .compatible = "mediatek,mt8183-disp-ccorr"},
- { .compatible = "mediatek,mt8183-disp-ccorr",
.data = &mt8183_ccorr_driver_data},}; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
From: Yongqiang Niu yongqiang.niu@mediatek.com
Add mtk mutex support for MT8192 SoC.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, };
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, };
+static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17
#define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, };
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
- [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
- [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
- [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
- [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
- [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
- [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
- [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, };
+static const struct mtk_mutex_data mt8192_mutex_driver_data = {
- .mutex_mod = mt8192_mutex_mod,
- .mutex_sof = mt8183_mutex_sof,
- .mutex_mod_reg = MT8183_MUTEX0_MOD0,
- .mutex_sof_reg = MT8183_MUTEX0_SOF0,
+};
struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data},
- { .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},}; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
From: Yongqiang Niu yongqiang.niu@mediatek.com
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 +++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++++++++++ drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 1 + drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++ 5 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 1c7163a12f3b1..43794192e82b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -220,9 +220,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = CCORR_MATRIX_BITS, };
+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { + .matrix_bits = 13, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data}, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = &mt8192_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, };
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = &mt8192_ovl_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = &mt8192_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c index d640cef9c15a4..62c8431a09605 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c @@ -146,6 +146,7 @@ static int mtk_disp_postmask_remove(struct platform_device *pdev) }
static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = { + { .compatible = "mediatek,mt8192-disp-postmask"}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, };
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 3da8996438dbc..6261d6bbe863e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L2, + DDP_COMPONENT_RDMA4, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), };
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .main_path = mt8192_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), + .ext_path = mt8192_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR }, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, + { .compatible = "mediatek,mt8192-disp-aal", + .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, + { .compatible = "mediatek,mt8192-disp-postmask", + .data = (void *)MTK_DISP_POSTMASK }, { } };
@@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data}, { } };
dri-devel@lists.freedesktop.org
-
Chun-Kuang Hu -
CK Hu -
Hsin-Yi Wang -
Yongqiang Niu