This is to keep track of the id of the plane as there are 4 planes in Kmb and when update() is called, we need to know which plane need to be updated so that the corresponding plane's registers can be programmed.

v2: moved extern to .h, upclassed dev_private, minor changes from code review.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 13 ++++--- drivers/gpu/drm/kmb/kmb_crtc.h | 2 +- drivers/gpu/drm/kmb/kmb_drv.h | 2 +- drivers/gpu/drm/kmb/kmb_plane.c | 80 +++++++++++++++++++++++++++-------------- drivers/gpu/drm/kmb/kmb_plane.h | 28 +++++++++------ 5 files changed, 79 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 1a00015..63821ed 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -105,9 +105,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset); kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset); } - /* enable all 4 layers */ - ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE - | LCD_CTRL_VL2_ENABLE | LCD_CTRL_GL1_ENABLE | LCD_CTRL_GL2_ENABLE; + /* enable VL1 layer as default */ + ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE | LCD_CTRL_OUTPUT_ENABLED; kmb_write(lcd, LCD_CONTROL, ctrl); @@ -175,17 +174,17 @@ static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { int kmb_setup_crtc(struct drm_device *drm) { struct kmb_drm_private *lcd = to_kmb(drm); - struct drm_plane *primary; + struct kmb_plane *primary; int ret;

primary = kmb_plane_init(drm); if (IS_ERR(primary)) return PTR_ERR(primary);

- ret = drm_crtc_init_with_planes(drm, &lcd->crtc, primary, NULL, - &kmb_crtc_funcs, NULL); + ret = drm_crtc_init_with_planes(drm, &lcd->crtc, &primary->base_plane, + NULL, &kmb_crtc_funcs, NULL); if (ret) { - kmb_plane_destroy(primary); + kmb_plane_destroy(&primary->base_plane); return ret; }

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h index d7cc441..6c3efdd 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.h +++ b/drivers/gpu/drm/kmb/kmb_crtc.h @@ -35,5 +35,5 @@ struct kmb_crtc_state { #define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) #define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) extern void kmb_plane_destroy(struct drm_plane *plane); -extern struct drm_plane *kmb_plane_init(struct drm_device *drm); +extern struct kmb_plane *kmb_plane_init(struct drm_device *drm); #endif /* __KMB_CRTC_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 90e1c86..23299a5 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -16,7 +16,7 @@ struct kmb_drm_private { struct clk *clk; struct drm_fbdev_cma *fbdev; struct drm_crtc crtc; - struct drm_plane *plane; + struct kmb_plane *plane; struct drm_atomic_state *state; };

diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 9d4c8dc..7077a4c 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -41,46 +41,69 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, dma_addr_t addr; unsigned int width; unsigned int height; - unsigned int i; unsigned int dma_len; - struct kmb_plane_state *kmb_state = to_kmb_plane_state(plane->state); + struct kmb_plane *kmb_plane = to_kmb_plane(plane); unsigned int dma_cfg; + unsigned int ctrl = 0; + unsigned char plane_id = kmb_plane->id;

if (!fb) return;

lcd = to_kmb(plane->dev);

+ switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } + + ctrl |= LCD_CTRL_ENABLE; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_OUTPUT_ENABLED; + kmb_write(lcd, LCD_CONTROL, ctrl); + /* TBD */ /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START, * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG * CFG should set the pixel format, FIFO level and BPP */

+ /*TBD check visible? */ + /* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */ dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1;

- for (i = 0; i < kmb_state->no_planes; i++) { - /* disable DMA first */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), ~LCD_DMA_LAYER_ENABLE); + /* disable DMA first */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE);

- addr = drm_fb_cma_get_gem_addr(fb, plane->state, i); - kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(i), addr); - kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(i), addr); + addr = drm_fb_cma_get_gem_addr(fb, plane->state, plane_id); + kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); + kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr);

- width = fb->width; - height = fb->height; - dma_len = width * height * fb->format->cpp[i]; - kmb_write(lcd, LCD_LAYERn_DMA_LEN(i), dma_len); + width = fb->width; + height = fb->height; + dma_len = width * height * fb->format->cpp[plane_id]; + kmb_write(lcd, LCD_LAYERn_DMA_LEN(plane_id), dma_len);

- kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(i), fb->pitches[0]); - kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(i), - (width * fb->format->cpp[i])); + kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[plane_id]); + kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width * fb->format->cpp[plane_id])); + + /* enable DMA */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);

- /* enable DMA */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), dma_cfg); - } }

static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { @@ -90,7 +113,9 @@ static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = {

void kmb_plane_destroy(struct drm_plane *plane) { + struct kmb_plane *kmb_plane = to_kmb_plane(plane); drm_plane_cleanup(plane); + kfree(kmb_plane); }

static void kmb_destroy_plane_state(struct drm_plane *plane, @@ -185,11 +210,11 @@ static const u32 kmb_formats_v[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21, };

-struct drm_plane *kmb_plane_init(struct drm_device *drm) +struct kmb_plane *kmb_plane_init(struct drm_device *drm) { struct kmb_drm_private *lcd = to_kmb(drm); - struct drm_plane *plane = NULL; - struct drm_plane *primary = NULL; + struct kmb_plane *plane = NULL; + struct kmb_plane *primary = NULL; int i = 0; int ret; enum drm_plane_type plane_type; @@ -213,18 +238,21 @@ struct drm_plane *kmb_plane_init(struct drm_device *drm) num_plane_formats = ARRAY_SIZE(kmb_formats_g); }

- ret = drm_universal_plane_init(drm, plane, 0xFF, - &kmb_plane_funcs, plane_formats, - num_plane_formats, - NULL, plane_type, "plane %d", i); + ret = + drm_universal_plane_init(drm, &plane->base_plane, + POSSIBLE_CRTCS, &kmb_plane_funcs, + plane_formats, num_plane_formats, + NULL, plane_type, "plane %d", i); if (ret < 0) goto cleanup;

- drm_plane_helper_add(plane, &kmb_plane_helper_funcs); + drm_plane_helper_add(&plane->base_plane, + &kmb_plane_helper_funcs); if (plane_type == DRM_PLANE_TYPE_PRIMARY) { primary = plane; lcd->plane = plane; } + plane->id = i; }

cleanup: diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 46cdcaa..38b32a2 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -8,25 +8,31 @@

#include "kmb_drv.h"

-#define KMB_MAX_PLANES 4 +enum layer_id { + LAYER_0, + LAYER_1, + LAYER_2, + LAYER_3, + KMB_MAX_PLANES, +}; + +struct kmb_plane { + struct drm_plane base_plane; + struct kmb_drm_private kmb_dev; + unsigned char id; +};

-/* this struct may be needed in the future - *struct kmb_plane { - * struct drm_plane base_plane; - * struct kmb_drm_private kmb_dev; - *}; - */ struct kmb_plane_state { struct drm_plane_state base_plane_state; unsigned char no_planes; };

-/* may be needed in the future - *#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) - */ +#define POSSIBLE_CRTCS 1 +#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) + #define to_kmb_plane_state(x) \ container_of(x, struct kmb_plane_state, base_plane_state)

-struct drm_plane *kmb_plane_init(struct drm_device *drm); +struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); #endif /* __KMB_PLANE_H__ */

Did some general clean up and organization.

v2: corrected spelling

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 3 +- drivers/gpu/drm/kmb/kmb_regs.h | 852 +++++++++++++++-------------------------- 2 files changed, 307 insertions(+), 548 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 28aa625..11f8d1f 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -113,8 +113,7 @@ static irqreturn_t kmb_irq(int irq, void *arg) if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ val = kmb_read(lcd, LCD_VSTATUS); - /* BITS 13 and 14 */ - val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK) >> 12; + val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: case LCD_VSTATUS_COMPARE_BACKPORCH: diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 0f879b9..8346a04 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -6,35 +6,181 @@ #ifndef __KMB_REGS_H__ #define __KMB_REGS_H__

-/*LCD CONTROLLER REGISTERS */ -#define LCD_CONTROL (0x4 * 0x000) -#define LCD_INT_STATUS (0x4 * 0x001) -#define LCD_INT_ENABLE (0x4 * 0x002) -#define LCD_INT_CLEAR (0x4 * 0x003) -#define LCD_LINE_COUNT (0x4 * 0x004) -#define LCD_LINE_COMPARE (0x4 * 0x005) -#define LCD_VSTATUS (0x4 * 0x006) -#define LCD_VSTATUS_COMPARE (0x4 * 0x007) -#define LCD_SCREEN_WIDTH (0x4 * 0x008) -#define LCD_SCREEN_HEIGHT (0x4 * 0x009) -#define LCD_FIELD_INT_CFG (0x4 * 0x00a) -#define LCD_FIFO_FLUSH (0x4 * 0x00b) -#define LCD_BG_COLOUR_LS (0x4 * 0x00c) -#define LCD_BG_COLOUR_MS (0x4 * 0x00d) -#define LCD_RAM_CFG (0x4 * 0x00e) +#define ENABLE 1 +/*************************************************************************** + * LCD controller control register defines + ***************************************************************************/ +#define LCD_CONTROL (0x4 * 0x000) +#define LCD_CTRL_PROGRESSIVE (0<<0) +#define LCD_CTRL_INTERLACED (1<<0) +#define LCD_CTRL_ENABLE (1<<1) +#define LCD_CTRL_VL1_ENABLE (1<<2) +#define LCD_CTRL_VL2_ENABLE (1<<3) +#define LCD_CTRL_GL1_ENABLE (1<<4) +#define LCD_CTRL_GL2_ENABLE (1<<5) +#define LCD_CTRL_ALPHA_BLEND_VL1 (0<<6) +#define LCD_CTRL_ALPHA_BLEND_VL2 (1<<6) +#define LCD_CTRL_ALPHA_BLEND_GL1 (2<<6) +#define LCD_CTRL_ALPHA_BLEND_GL2 (3<<6) +#define LCD_CTRL_ALPHA_TOP_VL1 (0<<8) +#define LCD_CTRL_ALPHA_TOP_VL2 (1<<8) +#define LCD_CTRL_ALPHA_TOP_GL1 (2<<8) +#define LCD_CTRL_ALPHA_TOP_GL2 (3<<8) +#define LCD_CTRL_ALPHA_MIDDLE_VL1 (0<<10) +#define LCD_CTRL_ALPHA_MIDDLE_VL2 (1<<10) +#define LCD_CTRL_ALPHA_MIDDLE_GL1 (2<<10) +#define LCD_CTRL_ALPHA_MIDDLE_GL2 (3<<10) +#define LCD_CTRL_ALPHA_BOTTOM_VL1 (0<<12) +#define LCD_CTRL_ALPHA_BOTTOM_VL2 (1<<12) +#define LCD_CTRL_ALPHA_BOTTOM_GL1 (2<<12) +#define LCD_CTRL_ALPHA_BOTTOM_GL2 (3<<12) +#define LCD_CTRL_TIM_GEN_ENABLE (1<<14) +#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (1<<15) +#define LCD_CTRL_PWM0_EN (1<<16) +#define LCD_CTRL_PWM1_EN (1<<17) +#define LCD_CTRL_PWM2_EN (1<<18) +#define LCD_CTRL_OUTPUT_DISABLED (0<<19) +#define LCD_CTRL_OUTPUT_ENABLED (1<<19) +#define LCD_CTRL_BPORCH_ENABLE (1<<21) +#define LCD_CTRL_FPORCH_ENABLE (1<<22) +#define LCD_CTRL_PIPELINE_DMA (1<<28) + +/*interrupts */ +#define LCD_INT_STATUS (0x4 * 0x001) +#define LCD_INT_EOF (1<<0) +#define LCD_INT_LINE_CMP (1<<1) +#define LCD_INT_VERT_COMP (1<<2) +#define LAYER0_DMA_DONE_BIT (1<<3) +#define LAYER0_DMA_IDLE_BIT (1<<4) +#define LAYER0_DMA_OVERFLOW_BIT (1<<5) +#define LAYER0_DMA_FIFO_UNDERFLOW_BIT (1<<6) +#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) +#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) +#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) +#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) +#define LAYER1_DMA_DONE_BIT (1<<11) +#define LAYER1_DMA_IDLE_BIT (1<<12) +#define LAYER1_DMA_OVERFLOW_BIT (1<<13) +#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) +#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) +#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) +#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) +#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) +#define LAYER2_DMA_DONE_BIT (1<<19) +#define LAYER2_DMA_IDLE_BIT (1<<20) +#define LAYER2_DMA_OVERFLOW_BIT (1<<21) +#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) +#define LAYER3_DMA_DONE_BIT (1<<23) +#define LAYER3_DMA_IDLE_BIT (1<<24) +#define LAYER3_DMA_OVERFLOW_BIT (1<<25) +#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) + +#define LCD_INT_ENABLE (0x4 * 0x002) +#define LCD_INT_CLEAR (0x4 * 0x003) +#define LCD_LINE_COUNT (0x4 * 0x004) +#define LCD_LINE_COMPARE (0x4 * 0x005) +#define LCD_VSTATUS (0x4 * 0x006) + +/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal + * interval interrupt + */ +/* BITS 13 and 14 */ +#define LCD_VSTATUS_COMPARE (0x4 * 0x007) +#define LCD_VSTATUS_VERTICAL_STATUS_MASK (3<<13) +#define LCD_VSTATUS_COMPARE_VSYNC (0<<13) +#define LCD_VSTATUS_COMPARE_BACKPORCH (1<<13) +#define LCD_VSTATUS_COMPARE_ACTIVE (2<<13) +#define LCD_VSTATUS_COMPARE_FRONT_PORCH (3<<13) + +#define LCD_SCREEN_WIDTH (0x4 * 0x008) +#define LCD_SCREEN_HEIGHT (0x4 * 0x009) +#define LCD_FIELD_INT_CFG (0x4 * 0x00a) +#define LCD_FIFO_FLUSH (0x4 * 0x00b) +#define LCD_BG_COLOUR_LS (0x4 * 0x00c) +#define LCD_BG_COLOUR_MS (0x4 * 0x00d) +#define LCD_RAM_CFG (0x4 * 0x00e) + +/**************************************************************************** + * LCD controller Layer config register + **************************************************************************** + */ #define LCD_LAYER0_CFG (0x4 * 0x100) -#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) +#define LCD_LAYER_SCALE_H (1<<1) +#define LCD_LAYER_SCALE_V (1<<2) +#define LCD_LAYER_SCALE_H_V (LCD_LAYER_SCALE_H | \ + LCD_LAYER_SCALE_V) +#define LCD_LAYER_CSC_EN (1<<3) +#define LCD_LAYER_ALPHA_STATIC (1<<4) +#define LCD_LAYER_ALPHA_EMBED (1<<5) +#define LCD_LAYER_ALPHA_COMBI (LCD_LAYER_ALPHA_STATIC | \ + LCD_LAYER_ALPHA_EMBED) +/* RGB multiplied with alpha */ +#define LCD_LAYER_ALPHA_PREMULT (1<<6) +#define LCD_LAYER_INVERT_COL (1<<7) +#define LCD_LAYER_TRANSPARENT_EN (1<<8) +#define LCD_LAYER_FORMAT_YCBCR444PLAN (0<<9) +#define LCD_LAYER_FORMAT_YCBCR422PLAN (1<<9) +#define LCD_LAYER_FORMAT_YCBCR420PLAN (2<<9) +#define LCD_LAYER_FORMAT_RGB888PLAN (3<<9) +#define LCD_LAYER_FORMAT_YCBCR444LIN (4<<9) +#define LCD_LAYER_FORMAT_YCBCR422LIN (5<<9) +#define LCD_LAYER_FORMAT_RGB888 (6<<9) +#define LCD_LAYER_FORMAT_RGBA8888 (7<<9) +#define LCD_LAYER_FORMAT_RGBX8888 (8<<9) +#define LCD_LAYER_FORMAT_RGB565 (9<<9) +#define LCD_LAYER_FORMAT_RGBA1555 (0xa<<9) +#define LCD_LAYER_FORMAT_XRGB1555 (0xb<<9) +#define LCD_LAYER_FORMAT_RGB444 (0xc<<9) +#define LCD_LAYER_FORMAT_RGBA4444 (0xd<<9) +#define LCD_LAYER_FORMAT_RGBX4444 (0xe<<9) +#define LCD_LAYER_FORMAT_RGB332 (0xf<<9) +#define LCD_LAYER_FORMAT_RGBA3328 (0x10<<9) +#define LCD_LAYER_FORMAT_RGBX3328 (0x11<<9) +#define LCD_LAYER_FORMAT_CLUT (0x12<<9) +#define LCD_LAYER_FORMAT_NV12 (0x1c<<9) +#define LCD_LAYER_PLANAR_STORAGE (1<<14) +#define LCD_LAYER_8BPP (0<<15) +#define LCD_LAYER_16BPP (1<<15) +#define LCD_LAYER_24BPP (2<<15) +#define LCD_LAYER_32BPP (3<<15) +#define LCD_LAYER_Y_ORDER (1<<17) +#define LCD_LAYER_CRCB_ORDER (1<<18) +#define LCD_LAYER_BGR_ORDER (1<<19) +#define LCD_LAYER_LUT_2ENT (0<<20) +#define LCD_LAYER_LUT_4ENT (1<<20) +#define LCD_LAYER_LUT_16ENT (2<<20) +#define LCD_LAYER_NO_FLIP (0<<22) +#define LCD_LAYER_FLIP_V (1<<22) +#define LCD_LAYER_FLIP_H (2<<22) +#define LCD_LAYER_ROT_R90 (3<<22) +#define LCD_LAYER_ROT_L90 (4<<22) +#define LCD_LAYER_ROT_180 (5<<22) +#define LCD_LAYER_FIFO_00 (0<<25) +#define LCD_LAYER_FIFO_25 (1<<25) +#define LCD_LAYER_FIFO_50 (2<<25) +#define LCD_LAYER_FIFO_100 (3<<25) +#define LCD_LAYER_INTERLEAVE_DIS (0<<27) +#define LCD_LAYER_INTERLEAVE_V (1<<27) +#define LCD_LAYER_INTERLEAVE_H (2<<27) +#define LCD_LAYER_INTERLEAVE_CH (3<<27) +#define LCD_LAYER_INTERLEAVE_V_SUB (4<<27) +#define LCD_LAYER_INTERLEAVE_H_SUB (5<<27) +#define LCD_LAYER_INTERLEAVE_CH_SUB (6<<27) +#define LCD_LAYER_INTER_POS_EVEN (0<<30) +#define LCD_LAYER_INTER_POS_ODD (1<<30) + #define LCD_LAYER0_COL_START (0x4 * 0x101) #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) #define LCD_LAYER0_ROW_START (0x4 * 0x102) #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) -#define LCD_LAYER0_WIDTH (0x4 * 0x103) +#define LCD_LAYER0_WIDTH (0x4 * 0x103) #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) #define LCD_LAYER0_HEIGHT (0x4 * 0x104) #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105) #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) -#define LCD_LAYER0_ALPHA (0x4 * 0x106) +#define LCD_LAYER0_ALPHA (0x4 * 0x106) #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107) #define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) @@ -68,540 +214,154 @@ #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116) #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) -#define LCD_LAYER0_DMA_CFG (0x4 * 0x117) -#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) -#define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) -#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR + (0x400*N)) -#define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) -#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW + (0x400*N)) -#define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) -#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + (0x400*N)) -#define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) -#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) -#define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) -#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) -#define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) -#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + (0x400*N)) -#define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) -#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE + (0x400*N)) -#define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) -#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) -#define LCD_LAYER0_CFG2 (0x4 * 0x120) -#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) - -#define LCD_LAYER1_CFG (0x4 * 0x200) -#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) -#define LCD_LAYER1_COL_START (0x4 * 0x201) -#define LCD_LAYER1_ROW_START (0x4 * 0x202) -#define LCD_LAYER1_WIDTH (0x4 * 0x203) -#define LCD_LAYER1_HEIGHT (0x4 * 0x204) -#define LCD_LAYER1_SCALE_CFG (0x4 * 0x205) -#define LCD_LAYER1_ALPHA (0x4 * 0x206) -#define LCD_LAYER1_INV_COLOUR_LS (0x4 * 0x207) -#define LCD_LAYER1_INV_COLOUR_MS (0x4 * 0x208) -#define LCD_LAYER1_TRANS_COLOUR_LS (0x4 * 0x209) -#define LCD_LAYER1_TRANS_COLOUR_MS (0x4 * 0x20a) -#define LCD_LAYER1_CSC_COEFF11 (0x4 * 0x20b) -#define LCD_LAYER1_CSC_COEFF12 (0x4 * 0x20c) -#define LCD_LAYER1_CSC_COEFF13 (0x4 * 0x20d) -#define LCD_LAYER1_CSC_COEFF21 (0x4 * 0x20e) -#define LCD_LAYER1_CSC_COEFF22 (0x4 * 0x20f) -#define LCD_LAYER1_CSC_COEFF23 (0x4 * 0x210) -#define LCD_LAYER1_CSC_COEFF31 (0x4 * 0x211) -#define LCD_LAYER1_CSC_COEFF32 (0x4 * 0x212) -#define LCD_LAYER1_CSC_COEFF33 (0x4 * 0x213) -#define LCD_LAYER1_CSC_OFF1 (0x4 * 0x214) -#define LCD_LAYER1_CSC_OFF2 (0x4 * 0x215) -#define LCD_LAYER1_CSC_OFF3 (0x4 * 0x216) -#define LCD_LAYER1_DMA_CFG (0x4 * 0x217) -#define LCD_LAYER1_DMA_START_ADR (0x4 * 0x218) -#define LCD_LAYER1_DMA_START_SHADOW (0x4 * 0x219) -#define LCD_LAYER1_DMA_LEN (0x4 * 0x21a) -#define LCD_LAYER1_DMA_LEN_SHADOW (0x4 * 0x21b) -#define LCD_LAYER1_DMA_STATUS (0x4 * 0x21c) -#define LCD_LAYER1_DMA_LINE_WIDTH (0x4 * 0x21d) -#define LCD_LAYER1_DMA_LINE_VSTRIDE (0x4 * 0x21e) -#define LCD_LAYER1_DMA_FIFO_STATUS (0x4 * 0x21f) -#define LCD_LAYER1_CFG2 (0x4 * 0x220) -#define LCD_LAYER2_CFG (0x4 * 0x300) -#define LCD_LAYER2_COL_START (0x4 * 0x301) -#define LCD_LAYER2_ROW_START (0x4 * 0x302) -#define LCD_LAYER2_WIDTH (0x4 * 0x303) -#define LCD_LAYER2_HEIGHT (0x4 * 0x304) -#define LCD_LAYER2_SCALE_CFG (0x4 * 0x305) -#define LCD_LAYER2_ALPHA (0x4 * 0x306) -#define LCD_LAYER2_INV_COLOUR_LS (0x4 * 0x307) -#define LCD_LAYER2_INV_COLOUR_MS (0x4 * 0x308) -#define LCD_LAYER2_TRANS_COLOUR_LS (0x4 * 0x309) -#define LCD_LAYER2_TRANS_COLOUR_MS (0x4 * 0x30a) -#define LCD_LAYER2_CSC_COEFF11 (0x4 * 0x30b) -#define LCD_LAYER2_CSC_COEFF12 (0x4 * 0x30c) -#define LCD_LAYER2_CSC_COEFF13 (0x4 * 0x30d) -#define LCD_LAYER2_CSC_COEFF21 (0x4 * 0x30e) -#define LCD_LAYER2_CSC_COEFF22 (0x4 * 0x30f) -#define LCD_LAYER2_CSC_COEFF23 (0x4 * 0x310) -#define LCD_LAYER2_CSC_COEFF31 (0x4 * 0x311) -#define LCD_LAYER2_CSC_COEFF32 (0x4 * 0x312) -#define LCD_LAYER2_CSC_COEFF33 (0x4 * 0x313) -#define LCD_LAYER2_CSC_OFF1 (0x4 * 0x314) -#define LCD_LAYER2_CSC_OFF2 (0x4 * 0x315) -#define LCD_LAYER2_CSC_OFF3 (0x4 * 0x316) -#define LCD_LAYER2_DMA_CFG (0x4 * 0x317) -#define LCD_LAYER2_DMA_START_ADR (0x4 * 0x318) -#define LCD_LAYER2_DMA_START_SHADOW (0x4 * 0x319) -#define LCD_LAYER2_DMA_LEN (0x4 * 0x31a) -#define LCD_LAYER2_DMA_LEN_SHADOW (0x4 * 0x31b) -#define LCD_LAYER2_DMA_STATUS (0x4 * 0x31c) -#define LCD_LAYER2_DMA_LINE_WIDTH (0x4 * 0x31d) -#define LCD_LAYER2_DMA_LINE_VSTRIDE (0x4 * 0x31e) -#define LCD_LAYER2_DMA_FIFO_STATUS (0x4 * 0x31f) -#define LCD_LAYER2_CFG2 (0x4 * 0x320) -#define LCD_LAYER3_CFG (0x4 * 0x400) -#define LCD_LAYER3_COL_START (0x4 * 0x401) -#define LCD_LAYER3_ROW_START (0x4 * 0x402) -#define LCD_LAYER3_WIDTH (0x4 * 0x403) -#define LCD_LAYER3_HEIGHT (0x4 * 0x404) -#define LCD_LAYER3_SCALE_CFG (0x4 * 0x405) -#define LCD_LAYER3_ALPHA (0x4 * 0x406) -#define LCD_LAYER3_INV_COLOUR_LS (0x4 * 0x407) -#define LCD_LAYER3_INV_COLOUR_MS (0x4 * 0x408) -#define LCD_LAYER3_TRANS_COLOUR_LS (0x4 * 0x409) -#define LCD_LAYER3_TRANS_COLOUR_MS (0x4 * 0x40a) -#define LCD_LAYER3_CSC_COEFF11 (0x4 * 0x40b) -#define LCD_LAYER3_CSC_COEFF12 (0x4 * 0x40c) -#define LCD_LAYER3_CSC_COEFF13 (0x4 * 0x40d) -#define LCD_LAYER3_CSC_COEFF21 (0x4 * 0x40e) -#define LCD_LAYER3_CSC_COEFF22 (0x4 * 0x40f) -#define LCD_LAYER3_CSC_COEFF23 (0x4 * 0x410) -#define LCD_LAYER3_CSC_COEFF31 (0x4 * 0x411) -#define LCD_LAYER3_CSC_COEFF32 (0x4 * 0x412) -#define LCD_LAYER3_CSC_COEFF33 (0x4 * 0x413) -#define LCD_LAYER3_CSC_OFF1 (0x4 * 0x414) -#define LCD_LAYER3_CSC_OFF2 (0x4 * 0x415) -#define LCD_LAYER3_CSC_OFF3 (0x4 * 0x416) -#define LCD_LAYER3_DMA_CFG (0x4 * 0x417) -#define LCD_LAYER3_DMA_START_ADR (0x4 * 0x418) -#define LCD_LAYER3_DMA_START_SHADOW (0x4 * 0x419) -#define LCD_LAYER3_DMA_LEN (0x4 * 0x41a) -#define LCD_LAYER3_DMA_LEN_SHADOW (0x4 * 0x41b) -#define LCD_LAYER3_DMA_STATUS (0x4 * 0x41c) -#define LCD_LAYER3_DMA_LINE_WIDTH (0x4 * 0x41d) -#define LCD_LAYER3_DMA_LINE_VSTRIDE (0x4 * 0x41e) -#define LCD_LAYER3_DMA_FIFO_STATUS (0x4 * 0x41f) -#define LCD_LAYER3_CFG2 (0x4 * 0x420) -#define LCD_LAYER2_CLUT0 (0x4 * 0x500) -#define LCD_LAYER2_CLUT1 (0x4 * 0x501) -#define LCD_LAYER2_CLUT2 (0x4 * 0x502) -#define LCD_LAYER2_CLUT3 (0x4 * 0x503) -#define LCD_LAYER2_CLUT4 (0x4 * 0x504) -#define LCD_LAYER2_CLUT5 (0x4 * 0x505) -#define LCD_LAYER2_CLUT6 (0x4 * 0x506) -#define LCD_LAYER2_CLUT7 (0x4 * 0x507) -#define LCD_LAYER2_CLUT8 (0x4 * 0x508) -#define LCD_LAYER2_CLUT9 (0x4 * 0x509) -#define LCD_LAYER2_CLUT10 (0x4 * 0x50a) -#define LCD_LAYER2_CLUT11 (0x4 * 0x50b) -#define LCD_LAYER2_CLUT12 (0x4 * 0x50c) -#define LCD_LAYER2_CLUT13 (0x4 * 0x50d) -#define LCD_LAYER2_CLUT14 (0x4 * 0x50e) -#define LCD_LAYER2_CLUT15 (0x4 * 0x50f) -#define LCD_LAYER3_CLUT0 (0x4 * 0x600) -#define LCD_LAYER3_CLUT1 (0x4 * 0x601) -#define LCD_LAYER3_CLUT2 (0x4 * 0x602) -#define LCD_LAYER3_CLUT3 (0x4 * 0x603) -#define LCD_LAYER3_CLUT4 (0x4 * 0x604) -#define LCD_LAYER3_CLUT5 (0x4 * 0x605) -#define LCD_LAYER3_CLUT6 (0x4 * 0x606) -#define LCD_LAYER3_CLUT7 (0x4 * 0x607) -#define LCD_LAYER3_CLUT8 (0x4 * 0x608) -#define LCD_LAYER3_CLUT9 (0x4 * 0x609) -#define LCD_LAYER3_CLUT10 (0x4 * 0x60a) -#define LCD_LAYER3_CLUT11 (0x4 * 0x60b) -#define LCD_LAYER3_CLUT12 (0x4 * 0x60c) -#define LCD_LAYER3_CLUT13 (0x4 * 0x60d) -#define LCD_LAYER3_CLUT14 (0x4 * 0x60e) -#define LCD_LAYER3_CLUT15 (0x4 * 0x60f) -#define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) -#define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) -#define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) -#define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) -#define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) -#define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) -#define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) -#define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) -#define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) -#define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) -#define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) -#define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) -#define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) -#define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) -#define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) -#define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) -#define LCD_OUT_FORMAT_CFG (0x4 * 0x800) -#define LCD_HSYNC_WIDTH (0x4 * 0x801) -#define LCD_H_BACKPORCH (0x4 * 0x802) -#define LCD_H_ACTIVEWIDTH (0x4 * 0x803) -#define LCD_H_FRONTPORCH (0x4 * 0x804) -#define LCD_VSYNC_WIDTH (0x4 * 0x805) -#define LCD_V_BACKPORCH (0x4 * 0x806) -#define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) -#define LCD_V_FRONTPORCH (0x4 * 0x808) -#define LCD_VSYNC_START (0x4 * 0x809) -#define LCD_VSYNC_END (0x4 * 0x80a) -#define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) -#define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) -#define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) -#define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) -#define LCD_VSYNC_START_EVEN (0x4 * 0x80f) -#define LCD_VSYNC_END_EVEN (0x4 * 0x810) -#define LCD_TIMING_GEN_TRIG (0x4 * 0x811) -#define LCD_PWM0_CTRL (0x4 * 0x812) -#define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) -#define LCD_PWM0_HIGH_LOW (0x4 * 0x814) -#define LCD_PWM1_CTRL (0x4 * 0x815) -#define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) -#define LCD_PWM1_HIGH_LOW (0x4 * 0x817) -#define LCD_PWM2_CTRL (0x4 * 0x818) -#define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) -#define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) -#define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) -#define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) -#define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) -#define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) -#define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) -#define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) -#define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) -#define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) -#define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) -#define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) -#define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) -#define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) -#define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) -#define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) -#define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) -#define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) - -#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) -#define LAYER3_DMA_OVERFLOW_BIT (1<<25) -#define LAYER3_DMA_IDLE_BIT (1<<24) -#define LAYER3_DMA_DONE_BIT (1<<23) - -#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) -#define LAYER2_DMA_OVERFLOW_BIT (1<<21) -#define LAYER2_DMA_IDLE_BIT (1<<20) -#define LAYER2_DMA_DONE_BIT (1<<19) - -#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) -#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) -#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) -#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) - -#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) -#define LAYER1_DMA_OVERFLOW_BIT (1<<13) -#define LAYER1_DMA_IDLE_BIT (1<<12) -#define LAYER1_DMA_DONE_BIT (1<<11) - -#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) -#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) -#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) -#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) - -#define LAYER0_DMA_FIFO_UNDERFLOW_BIT (1<<6) -#define LAYER0_DMA_OVERFLOW_BIT (1<<5) -#define LAYER0_DMA_IDLE_BIT (1<<4) -#define LAYER0_DMA_DONE_BIT (1<<3) - -#define BLT_VIDEOn_DMAm_STATE 0x00 -#define BLT_VIDEOn_DMAm_BYTES 0x00 -#define BLT_RAM_CFG 0x00 - -#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) -#define BLT_LAYERn_HEIGHT_OFFSET(N) (0x410 + (0x400*N)) - -#define BLT_LAYERn_TRANS_COLOUR_MS 0x0 -#define BLT_LAYERn_TRANS_COLOUR_LS 0x0 -#define BLT_LAYERn_SCALE_CFG 0x0 -#define BLT_LAYERn_ROW_START 0x0 -#define BLT_LAYERn_INV_COLOUR_MS 0x0 -#define BLT_LAYERn_INV_COLOUR_LS 0x0

/* LCD controller Layer DMA config register */ +#define LCD_LAYER0_DMA_CFG (0x4 * 0x117) +#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) +#define LCD_DMA_LAYER_ENABLE (1<<0) +#define LCD_DMA_LAYER_STATUS (1<<1) +#define LCD_DMA_LAYER_AUTO_UPDATE (1<<2) +#define LCD_DMA_LAYER_CONT_UPDATE (1<<3) +#define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (LCD_DMA_LAYER_AUTO_UPDATE \ + | LCD_DMA_LAYER_CONT_UPDATE) +#define LCD_DMA_LAYER_FIFO_ADR_MODE (1<<4) +#define LCD_DMA_LAYER_AXI_BURST_1 (1<<5) +#define LCD_DMA_LAYER_AXI_BURST_2 (2<<5) +#define LCD_DMA_LAYER_AXI_BURST_3 (3<<5) +#define LCD_DMA_LAYER_AXI_BURST_4 (4<<5) +#define LCD_DMA_LAYER_AXI_BURST_5 (5<<5) +#define LCD_DMA_LAYER_AXI_BURST_6 (6<<5) +#define LCD_DMA_LAYER_AXI_BURST_7 (7<<5) +#define LCD_DMA_LAYER_AXI_BURST_8 (8<<5) +#define LCD_DMA_LAYER_AXI_BURST_9 (9<<5) +#define LCD_DMA_LAYER_AXI_BURST_10 (0xa<<5) +#define LCD_DMA_LAYER_AXI_BURST_11 (0xb<<5) +#define LCD_DMA_LAYER_AXI_BURST_12 (0xc<<5) +#define LCD_DMA_LAYER_AXI_BURST_13 (0xd<<5) +#define LCD_DMA_LAYER_AXI_BURST_14 (0xe<<5) +#define LCD_DMA_LAYER_AXI_BURST_15 (0xf<<5) +#define LCD_DMA_LAYER_AXI_BURST_16 (0x10<<5) +#define LCD_DMA_LAYER_V_STRIDE_EN (1<<10)

-/* bit 0 default is disabled */ -#define LCD_DMA_LAYER_ENABLE (0x001) -/* bit 1 this should be used only as a mask when reading the status from - * the DMA CFG register - */ -#define LCD_DMA_LAYER_STATUS (0x002) -/* bit 2 */ -#define LCD_DMA_LAYER_AUTO_UPDATE (0x004) -/* bit 3 */ -#define LCD_DMA_LAYER_CONT_UPDATE (0x008) -/* bit 2 + bit 3 */ -#define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (0x00C) -/* bit 4 set FIFO addressing mode, default is increment after each burst */ -#define LCD_DMA_LAYER_FIFO_ADR_MODE (0x010) -/* bit 5:9 default axi burst is 1 */ -#define LCD_DMA_LAYER_AXI_BURST_1 (0x020) -#define LCD_DMA_LAYER_AXI_BURST_2 (0x040) -#define LCD_DMA_LAYER_AXI_BURST_3 (0x060) -#define LCD_DMA_LAYER_AXI_BURST_4 (0x080) -#define LCD_DMA_LAYER_AXI_BURST_5 (0x0A0) -#define LCD_DMA_LAYER_AXI_BURST_6 (0x0C0) -#define LCD_DMA_LAYER_AXI_BURST_7 (0x0E0) -#define LCD_DMA_LAYER_AXI_BURST_8 (0x100) -#define LCD_DMA_LAYER_AXI_BURST_9 (0x120) -#define LCD_DMA_LAYER_AXI_BURST_10 (0x140) -#define LCD_DMA_LAYER_AXI_BURST_11 (0x160) -#define LCD_DMA_LAYER_AXI_BURST_12 (0x180) -#define LCD_DMA_LAYER_AXI_BURST_13 (0x1A0) -#define LCD_DMA_LAYER_AXI_BURST_14 (0x1C0) -#define LCD_DMA_LAYER_AXI_BURST_15 (0x1E0) -#define LCD_DMA_LAYER_AXI_BURST_16 (0x200) -/* bit 10 */ -#define LCD_DMA_LAYER_V_STRIDE_EN (0x400) - -/****************************************************************************** - * LCD controller Layer config register - ******************************************************************************/ -/* ---bit 1:2 */ -/* enable horizontal scaling,default is - * no scaling - */ -#define LCD_LAYER_SCALE_H (0x0002) -/* enable vertical scaling*/ -#define LCD_LAYER_SCALE_V (0x0004) -/* enable vertical and horizontal - * scaling - */ -#define LCD_LAYER_SCALE_H_V (0x0006) -/* --- bit 3*/ -/* enable CSC, default is bypassed*/ -#define LCD_LAYER_CSC_EN (0x0008) -/* --- bit 4:5*/ -/* use static alpha value for layer, - * default is disabled - */ -#define LCD_LAYER_ALPHA_STATIC (0x10) -/* use embedded value for alpha blending*/ -#define LCD_LAYER_ALPHA_EMBED (0x20) -/* use static alpha and embedded value, - * by multiplication - */ -#define LCD_LAYER_ALPHA_COMBI (0x30) -/* --- bit 6*/ -/* indicates that the RGB values have - * been multiplied with alpha - */ -#define LCD_LAYER_ALPHA_PREMULT (0x40) -/* --- bit 7*/ -#define LCD_LAYER_INVERT_COL (0x80) -/* enable color inversion, - * default is not inverted - */ -/* --- bit 8*/ -/* enable transparency */ -#define LCD_LAYER_TRANSPARENT_EN (0x100) -/* --- bit 9:13*/ -/* default Layer config */ -#define LCD_LAYER_FORMAT_YCBCR444PLAN (0x0000) -#define LCD_LAYER_FORMAT_YCBCR422PLAN (0x0200) -#define LCD_LAYER_FORMAT_YCBCR420PLAN (0x0400) -#define LCD_LAYER_FORMAT_RGB888PLAN (0x0600) -#define LCD_LAYER_FORMAT_YCBCR444LIN (0x0800) -#define LCD_LAYER_FORMAT_YCBCR422LIN (0x0A00) -#define LCD_LAYER_FORMAT_RGB888 (0x0C00) -#define LCD_LAYER_FORMAT_RGBA8888 (0x0E00) -#define LCD_LAYER_FORMAT_RGBX8888 (0x1000) -#define LCD_LAYER_FORMAT_RGB565 (0x1200) -#define LCD_LAYER_FORMAT_RGBA1555 (0x1400) -#define LCD_LAYER_FORMAT_XRGB1555 (0x1600) -#define LCD_LAYER_FORMAT_RGB444 (0x1800) -#define LCD_LAYER_FORMAT_RGBA4444 (0x1A00) -#define LCD_LAYER_FORMAT_RGBX4444 (0x1C00) -#define LCD_LAYER_FORMAT_RGB332 (0x1E00) -#define LCD_LAYER_FORMAT_RGBA3328 (0x2000) -#define LCD_LAYER_FORMAT_RGBX3328 (0x2200) -#define LCD_LAYER_FORMAT_CLUT (0x2400) -#define LCD_LAYER_FORMAT_NV12 (0x3800) -/* --- bit 14*/ -/* planar storege format */ -#define LCD_LAYER_PLANAR_STORAGE (0x4000) -/* --- bit 15:16*/ -#define LCD_LAYER_8BPP (0x00000) -#define LCD_LAYER_16BPP (0x08000) -#define LCD_LAYER_24BPP (0x10000) -#define LCD_LAYER_32BPP (0x18000) -/* --- bit 17*/ -/* Y after CRCb, - * default is Y before crcb - */ -#define LCD_LAYER_Y_ORDER (0x020000) -/* --- bit 18*/ -/* CR before Cb, - * default is CB before Cr - */ -#define LCD_LAYER_CRCB_ORDER (0x040000) -/*--- but 19*/ -/* BGR order, default is RGB */ -#define LCD_LAYER_BGR_ORDER (0x080000) -/* ---bit 20:21*/ -/* 2 entry clut, 1bpp */ -#define LCD_LAYER_LUT_2ENT (0x000000) -/* 4 entry clut, 2bpp */ -#define LCD_LAYER_LUT_4ENT (0x100000) -/* 18 entry clut, 4bpp */ -#define LCD_LAYER_LUT_16ENT (0x200000) -/*--- bit 22:24*/ -/* no flip or rotaton */ -#define LCD_LAYER_NO_FLIP (0x000000) -/* flip vertical */ -#define LCD_LAYER_FLIP_V (0x400000) -/* flip horizontal */ -#define LCD_LAYER_FLIP_H (0x800000) -/* rotate right 90 */ -#define LCD_LAYER_ROT_R90 (0xC00000) -/* rotate left 90 */ -#define LCD_LAYER_ROT_L90 (0x1000000) -/* rotate 180 (flip H & V ) */ -#define LCD_LAYER_ROT_180 (0x1400000) -/* --- bit 25:26*/ -/* fifo empty */ -#define LCD_LAYER_FIFO_00 (0x0000000) -/* fifo 25% */ -#define LCD_LAYER_FIFO_25 (0x2000000) -/* fifo 50% */ -#define LCD_LAYER_FIFO_50 (0x4000000) -/* fifo 100% , full */ -#define LCD_LAYER_FIFO_100 (0x6000000) - -/* --- bit 27:29*/ -#define LCD_LAYER_INTERLEAVE_DIS (0x00000000) -#define LCD_LAYER_INTERLEAVE_V (0x08000000) -#define LCD_LAYER_INTERLEAVE_H (0x10000000) -#define LCD_LAYER_INTERLEAVE_CH (0x18000000) -#define LCD_LAYER_INTERLEAVE_V_SUB (0x20000000) -#define LCD_LAYER_INTERLEAVE_H_SUB (0x28000000) -#define LCD_LAYER_INTERLEAVE_CH_SUB (0x30000000) -/*bit 30*/ -#define LCD_LAYER_INTER_POS_EVEN (0x00000000) -#define LCD_LAYER_INTER_POS_ODD (0x40000000) +#define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) +#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \ + + (0x400*N)) +#define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) +#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW \ + + (0x400*N)) +#define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) +#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + \ + (0x400*N)) +#define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) +#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) +#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE +\ + (0x400*N)) +#define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + \ + (0x400*N)) +#define LCD_LAYER0_CFG2 (0x4 * 0x120) +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) +#define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) +#define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) +#define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) +#define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) +#define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) +#define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) +#define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) +#define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) +#define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) +#define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) +#define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) +#define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) +#define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) +#define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) +#define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) +#define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f)

/**************************************************************************** * LCD controller output format register defines ****************************************************************************/ -/* --- bits 0:4*/ -#define D_LCD_OUTF_FORMAT_RGB121212 (0x00 << 0) -#define D_LCD_OUTF_FORMAT_RGB101010 (0x01 << 0) -#define D_LCD_OUTF_FORMAT_RGB888 (0x02 << 0) -#define D_LCD_OUTF_FORMAT_RGB666 (0x03 << 0) -#define D_LCD_OUTF_FORMAT_RGB565 (0x04 << 0) -#define D_LCD_OUTF_FORMAT_RGB444 (0x05 << 0) -#define D_LCD_OUTF_FORMAT_MRGB121212 (0x10 << 0) -#define D_LCD_OUTF_FORMAT_MRGB101010 (0x11 << 0) -#define D_LCD_OUTF_FORMAT_MRGB888 (0x12 << 0) -#define D_LCD_OUTF_FORMAT_MRGB666 (0x13 << 0) -#define D_LCD_OUTF_FORMAT_MRGB565 (0x14 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B (0x0A << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_10B (0x0B << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_12B (0x0C << 0) -#define D_LCD_OUTF_FORMAT_YCBCR422_8B (0x0D << 0) -#define D_LCD_OUTF_FORMAT_YCBCR422_10B (0x0E << 0) -#define D_LCD_OUTF_FORMAT_YCBCR444 (0x0F << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18 << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19 << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR444 (0x1F << 0) -/* --- bit 5*/ -/* default is 0, RGB order */ -#define D_LCD_OUTF_BGR_ORDER (1 << 5) -/* --- bit 6*/ -/* Y after CB/Cr, default is Y before CB/CR */ -#define D_LCD_OUTF_Y_ORDER (1 << 6) -/* --- bit 7*/ -/* Cr before Cb, default is Cb before Cr */ -#define D_LCD_OUTF_CRCB_ORDER (1 << 7) - -/* ************************************************************************** - * LCD controller control register defines - **************************************************************************** - */ -/* --- bit 0 */ -#define LCD_CTRL_PROGRESSIVE (0x00) /* default */ -#define LCD_CTRL_INTERLACED (0x01) -/* --- bit 1 */ -#define LCD_CTRL_ENABLE (0x02) /* enable conrtoller */ -/* --- bits 2,3,4,5 */ -#define LCD_CTRL_VL1_ENABLE (0x04) /* enable video layer 1 */ -#define LCD_CTRL_VL2_ENABLE (0x08) /* enable video layer 2 */ -#define LCD_CTRL_GL1_ENABLE (0x10) /* enable graphics layer 1 */ -#define LCD_CTRL_GL2_ENABLE (0x20) /* enable graphics layer 2 */ -/* --- bits 6:7 */ -#define LCD_CTRL_ALPHA_BLEND_VL1 (0x00) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_BLEND_VL2 (0x40) /* video layer 2 */ -#define LCD_CTRL_ALPHA_BLEND_GL1 (0x80) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_BLEND_GL2 (0xC0) /* graphics layer 2 */ -/* --- bits 8:9 */ -#define LCD_CTRL_ALPHA_TOP_VL1 (0x000) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_TOP_VL2 (0x100) /* video layer 2 */ -#define LCD_CTRL_ALPHA_TOP_GL1 (0x200) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_TOP_GL2 (0x300) /* graphics layer 2 */ -/* --- bits 10:11 */ -#define LCD_CTRL_ALPHA_MIDDLE_VL1 (0x000) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_MIDDLE_VL2 (0x400) /* video layer 2 */ -#define LCD_CTRL_ALPHA_MIDDLE_GL1 (0x800) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_MIDDLE_GL2 (0xC00) /* graphics layer 2 */ -/* --- bits 12:13 */ -#define LCD_CTRL_ALPHA_BOTTOM_VL1 (0x0000) /* video layer 1 */ -#define LCD_CTRL_ALPHA_BOTTOM_VL2 (0x1000) /* video layer 2 */ -#define LCD_CTRL_ALPHA_BOTTOM_GL1 (0x2000) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_BOTTOM_GL2 (0x3000) /* graphics layer 2 */ -/* --- bit 14 */ -#define LCD_CTRL_TIM_GEN_ENABLE (0x4000) /* timing generator */ -/* --- bit 15 */ -#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (0x8000) /* default continuous */ -/* --- bits 16, 17, 18 */ -#define LCD_CTRL_PWM0_EN (0x10000) /* enable PWM 0 */ -#define LCD_CTRL_PWM1_EN (0x20000) /* enable PWM 1 */ -#define LCD_CTRL_PWM2_EN (0x40000) /* enable PWM 2 */ -/* --- bits 19:20 */ -#define LCD_CTRL_OUTPUT_DISABLED (0x000000) /* output disabled */ -#define LCD_CTRL_OUTPUT_ENABLED (0x080000) -/* --- bit 21 */ -#define LCD_CTRL_SHARP_TFT (0x200000) -/* = bit 21 VSYNC BACK PORCH LEVEL */ -#define LCD_CTRL_BPORCH_ENABLE (0x00200000) -/* = bit 22 VSYNC FRONT PORCH LEVEL */ -#define LCD_CTRL_FPORCH_ENABLE (0x00400000) -/* = bit 28 enable pipelined (outstanding) DMA reads */ -#define LCD_CTRL_PIPELINE_DMA (0x10000000) - -/* LCD Control register bit fields */ - -#define EIGHT_BITS 8 -#define SIXTEEN_BITS 8 -#define TWENTY_FOUR_BITS 8 -#define THIRT_TWO_BITS 8 - -#define ENABLE 1 -/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal - * interval interrupt - */ -#define LCD_VSTATUS_VERTICAL_STATUS_MASK 0x60 /* BITS 13 and 14 */ -#define LCD_VSTATUS_COMPARE_VSYNC 0x00 -#define LCD_VSTATUS_COMPARE_BACKPORCH 0x01 -#define LCD_VSTATUS_COMPARE_ACTIVE 0x10 -#define LCD_VSTATUS_COMPARE_FRONT_PORCH 0x11 +#define LCD_OUT_FORMAT_CFG (0x4 * 0x800) +#define LCD_OUTF_FORMAT_RGB121212 (0x00) +#define LCD_OUTF_FORMAT_RGB101010 (0x01) +#define LCD_OUTF_FORMAT_RGB888 (0x02) +#define LCD_OUTF_FORMAT_RGB666 (0x03) +#define LCD_OUTF_FORMAT_RGB565 (0x04) +#define LCD_OUTF_FORMAT_RGB444 (0x05) +#define LCD_OUTF_FORMAT_MRGB121212 (0x10) +#define LCD_OUTF_FORMAT_MRGB101010 (0x11) +#define LCD_OUTF_FORMAT_MRGB888 (0x12) +#define LCD_OUTF_FORMAT_MRGB666 (0x13) +#define LCD_OUTF_FORMAT_MRGB565 (0x14) +#define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08) +#define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09) +#define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A) +#define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B) +#define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C) +#define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D) +#define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E) +#define LCD_OUTF_FORMAT_YCBCR444 (0x0F) +#define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18) +#define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19) +#define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A) +#define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B) +#define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C) +#define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D) +#define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E) +#define LCD_OUTF_FORMAT_MYCBCR444 (0x1F) +#define LCD_OUTF_BGR_ORDER (1 << 5) +#define LCD_OUTF_Y_ORDER (1 << 6) +#define LCD_OUTF_CRCB_ORDER (1 << 7)

-/*interrupt bits */ -#define LCD_INT_VERT_COMP (1 << 2) -#define LCD_INT_LINE_CMP (1 << 1) -#define LCD_INT_EOF (1 << 0) +#define LCD_HSYNC_WIDTH (0x4 * 0x801) +#define LCD_H_BACKPORCH (0x4 * 0x802) +#define LCD_H_ACTIVEWIDTH (0x4 * 0x803) +#define LCD_H_FRONTPORCH (0x4 * 0x804) +#define LCD_VSYNC_WIDTH (0x4 * 0x805) +#define LCD_V_BACKPORCH (0x4 * 0x806) +#define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) +#define LCD_V_FRONTPORCH (0x4 * 0x808) +#define LCD_VSYNC_START (0x4 * 0x809) +#define LCD_VSYNC_END (0x4 * 0x80a) +#define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) +#define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) +#define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) +#define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) +#define LCD_VSYNC_START_EVEN (0x4 * 0x80f) +#define LCD_VSYNC_END_EVEN (0x4 * 0x810) +#define LCD_TIMING_GEN_TRIG (0x4 * 0x811) +#define LCD_PWM0_CTRL (0x4 * 0x812) +#define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) +#define LCD_PWM0_HIGH_LOW (0x4 * 0x814) +#define LCD_PWM1_CTRL (0x4 * 0x815) +#define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) +#define LCD_PWM1_HIGH_LOW (0x4 * 0x817) +#define LCD_PWM2_CTRL (0x4 * 0x818) +#define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) +#define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) +#define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) +#define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) +#define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) +#define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) +#define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) +#define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) +#define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) +#define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) +#define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) +#define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) +#define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) +#define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) +#define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) +#define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) +#define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) +#define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f)

#endif /* __KMB_REGS_H__ */

Basic frame work for mipi encoder and connector. More hardware specific details will be added in the future commits.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/Makefile | 2 +- drivers/gpu/drm/kmb/kmb_drv.c | 2 + drivers/gpu/drm/kmb/kmb_dsi.c | 94 +++++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 38 +++++++++++++++++ 4 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h

diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile index be9f19c..8102bc9 100644 --- a/drivers/gpu/drm/kmb/Makefile +++ b/drivers/gpu/drm/kmb/Makefile @@ -1,2 +1,2 @@ -kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o +kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 11f8d1f..aec8a5b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -25,6 +25,7 @@ #include <drm/drm_probe_helper.h> #include "kmb_crtc.h" #include "kmb_drv.h" +#include "kmb_dsi.h" #include "kmb_plane.h" #include "kmb_regs.h"

@@ -63,6 +64,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

+ kmb_dsi_init(drm); ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c new file mode 100644 index 0000000..654fae8 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright © 2019-2020 Intel Corporation + */ + +#include <linux/gpio/consumer.h> +#include <linux/slab.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_connector.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_edid.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_probe_helper.h> +#include "kmb_drv.h" +#include "kmb_dsi.h" + +static enum drm_mode_status +kmb_dsi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static int kmb_dsi_get_modes(struct drm_connector *connector) +{ + struct drm_display_mode *mode; + struct kmb_connector *kmb_connector = to_kmb_connector(connector); + + mode = drm_mode_duplicate(connector->dev, kmb_connector->fixed_mode); + drm_mode_probed_add(connector, mode); + return 1; +} + +static void kmb_dsi_connector_destroy(struct drm_connector *connector) +{ + struct kmb_connector *kmb_connector = to_kmb_connector(connector); + + drm_connector_cleanup(connector); + kfree(kmb_connector); +} + +static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder) +{ + struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder); + + drm_encoder_cleanup(encoder); + kfree(kmb_dsi); +} + +static const struct drm_encoder_funcs kmb_dsi_funcs = { + .destroy = kmb_dsi_encoder_destroy, +}; + +static const struct +drm_connector_helper_funcs kmb_dsi_connector_helper_funcs = { + .get_modes = kmb_dsi_get_modes, + .mode_valid = kmb_dsi_mode_valid, +}; + +static const struct drm_connector_funcs kmb_dsi_connector_funcs = { + .destroy = kmb_dsi_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, +}; + +void kmb_dsi_init(struct drm_device *dev) +{ + struct kmb_dsi *kmb_dsi; + struct drm_encoder *encoder; + struct kmb_connector *kmb_connector; + struct drm_connector *connector; + + kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); + if (!kmb_dsi) + return; + + kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); + if (!kmb_connector) { + kfree(kmb_dsi); + return; + } + + kmb_dsi->attached_connector = kmb_connector; + + connector = &kmb_connector->base; + encoder = &kmb_dsi->base; + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, + "MIPI-DSI"); + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, + DRM_MODE_CONNECTOR_DSI); + drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); +} diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h new file mode 100644 index 0000000..9a6b0b7 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright © 2019-2020 Intel Corporation + */ + +#ifndef __KMB_DSI_H__ +#define __KMB_DSI_H__ + +#include <drm/drm_crtc.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include "kmb_drv.h" + +struct kmb_connector; + +struct kmb_dsi { + struct drm_encoder base; + struct kmb_connector *attached_connector; +}; + +struct kmb_dsi_host { + struct mipi_dsi_host base; + struct kmb_dsi *kmb_dsi; +}; + +struct kmb_connector { + struct drm_connector base; + struct drm_display_mode *fixed_mode; +}; + +void kmb_dsi_init(struct drm_device *dev); +void kmb_plane_destroy(struct drm_plane *plane); + +#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) +#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) +#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) + +#endif /* __KMB_DSI_H__ */

Added mipi DSI host initialization functions

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++ 2 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 654fae8..d82411e 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -65,12 +65,59 @@ static const struct drm_connector_funcs kmb_dsi_connector_funcs = { .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, };

+static ssize_t kmb_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + return 0; +} + +static int kmb_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *dev) +{ + return 0; +} + +static int kmb_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *dev) +{ + return 0; +} + +static const struct mipi_dsi_host_ops kmb_dsi_host_ops = { + .attach = kmb_dsi_host_attach, + .detach = kmb_dsi_host_detach, + .transfer = kmb_dsi_host_transfer, +}; + +static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi) +{ + struct kmb_dsi_host *host; + struct mipi_dsi_device *device; + + host = kzalloc(sizeof(*host), GFP_KERNEL); + if (!host) + return NULL; + + host->base.ops = &kmb_dsi_host_ops; + host->kmb_dsi = kmb_dsi; + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + kfree(host); + return NULL; + } + device->host = &host->base; + host->device = device; + return host; +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; struct kmb_connector *kmb_connector; struct drm_connector *connector; + struct kmb_dsi_host *host;

kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) @@ -88,7 +135,19 @@ void kmb_dsi_init(struct drm_device *dev) encoder = &kmb_dsi->base; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); + + host = kmb_dsi_host_init(kmb_dsi); + if (!host) { + drm_encoder_cleanup(encoder); + kfree(kmb_dsi); + kfree(kmb_connector); + } + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); + + connector->encoder = encoder; + drm_connector_attach_encoder(connector, encoder); + } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 9a6b0b7..0f5da87 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -12,19 +12,23 @@ #include "kmb_drv.h"

struct kmb_connector; +struct kmb_dsi_host;

struct kmb_dsi { struct drm_encoder base; struct kmb_connector *attached_connector; + struct kmb_dsi_host *dsi_host; };

struct kmb_dsi_host { struct mipi_dsi_host base; struct kmb_dsi *kmb_dsi; + struct mipi_dsi_device *device; };

struct kmb_connector { struct drm_connector base; + struct drm_encoder *encoder; struct drm_display_mode *fixed_mode; };

Mipi TX Frame generator timing configuration

Compute and set frame generator timings like hactive, front porch, back porch etc.

v2: minor code review changes Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 132 ++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/kmb/kmb_regs.h | 37 ++++++++++++ 2 files changed, 166 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index cb6082d..951a742 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -391,6 +391,123 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_priv, return 0; }

+static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, + u8 frame_gen, + struct mipi_tx_frame_timing_cfg *fg_cfg) +{ + u32 sysclk; + /*float ppl_llp_ratio; */ + u32 ppl_llp_ratio; + u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; + + /*Get system clock for blanking period cnfigurations */ + /*TODO need to get system clock from clock driver */ + /* Assume 700 Mhz system clock for now */ + sysclk = 700; + + /*ppl-pixel packing layer, llp-low level protocol + * frame genartor timing parameters are clocked on the system clock + * whereas as the equivalent parameters in the LLP blocks are clocked + * on LLP Tx clock from the D-PHY - BYTE clock + */ + + /*multiply by 1000 to keep the precision */ + ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / + ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); + + /*frame generator number of lines */ + reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->v_active); + + /*vsync width */ + /* + *there are 2 registers for vsync width -VSA in lines for channels 0-3 + *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 + *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 + */ + offset = (frame_gen % 2) * 16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->vsync_width); + + /*v backporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_backporch); + + /*v frontporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_frontporch); + + /*v active - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_active); + + /*hsyc width */ + reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + + /*h backporch */ + reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + + /*h frontporch */ + reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + + /*h active */ + reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); + /*convert h_active which is wc in bytes to cycles */ + val = (fg_cfg->h_active * sysclk * 1000) / + ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); + val /= 1000; + kmb_write(dev_priv, reg_adr, val); + + /* llp hsync width */ + reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); + + /* llp h backporch */ + reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); + + /* llp h frontporch */ + reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); +} + +static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, + u8 active_lanes, u32 bpp, u32 wc, + u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) +{ + u32 i, fg_num_lines = 0; + struct mipi_tx_frame_timing_cfg fg_t_cfg; + + /*calculate the total frame generator number of lines based on it's + * active sections + */ + for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) { + if (fg_cfg->sections[i] != NULL) + fg_num_lines += fg_cfg->sections[i]->height_lines; + } + + fg_t_cfg.bpp = bpp; + fg_t_cfg.lane_rate_mbps = lane_rate_mbps; + fg_t_cfg.hsync_width = fg_cfg->hsync_width; + fg_t_cfg.h_backporch = fg_cfg->h_backporch; + fg_t_cfg.h_frontporch = fg_cfg->h_frontporch; + fg_t_cfg.h_active = wc; + fg_t_cfg.vsync_width = fg_cfg->vsync_width; + fg_t_cfg.v_backporch = fg_cfg->v_backporch; + fg_t_cfg.v_frontporch = fg_cfg->v_frontporch; + fg_t_cfg.v_active = fg_num_lines; + fg_t_cfg.active_lanes = active_lanes; + + /*apply frame generator timing setting */ + mipi_tx_fg_cfg_regs(dev_priv, frame_gen, &fg_t_cfg); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -412,12 +529,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) continue;

+ /* Frame Section configuration */ /*TODO - assume there is only one valid section in a frame, so * bits_per_pclk and word_count are only set once */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + == NULL) continue;

ret = mipi_tx_fg_section_cfg(dev_priv, frame_id, sect, @@ -429,9 +547,17 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv,

}

+ /* set frame specific parameters */ + mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, + bits_per_pclk, + word_count, + ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); /*function for setting frame sepecific parameters will be - * called here bits_per_pclk and word_count will be passed - * in to this function + * called here + */ + /*bits_per_pclk and word_count will be passed in to this + * function */

} diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index c63199b..bdb55b7 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -390,4 +390,41 @@ + (0x400*M) + (0x2C*N) + (8*O)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44)

+#define MIPI_TX_HS_FG0_NUM_LINES (0x68) +#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ + (0x400*M) + (0x2C*N)) +#define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) +#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) +#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) +#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_ACTIVE0 (0x17c) +#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) +#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_BACKPORCH0 (0x11c) +#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) +#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_ACTIVE0 (0x184) +#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) +#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) +#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) +#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + + (0x400*M) + (0x4*N)) + #endif /* __KMB_REGS_H__ */

This initializes the multichannel fifo in the mipi transmitter and sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6

v2: code review changes to make code simpler

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.h | 25 +++++++++++++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 58 ++++++++++++++++++++++++++++++++++-------- drivers/gpu/drm/kmb/kmb_dsi.h | 3 +++ drivers/gpu/drm/kmb/kmb_regs.h | 30 +++++++++++++++++++--- 4 files changed, 99 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index d2a0f91..f1d5b3a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -8,8 +8,8 @@

#include "kmb_regs.h"

-#define KMB_MAX_WIDTH 16384 /*max width in pixels */ -#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ +#define KMB_MAX_WIDTH 16384 /*max width in pixels */ +#define KMB_MAX_HEIGHT 16384 /*max height in pixels */

struct kmb_drm_private { struct drm_device drm; @@ -64,6 +64,11 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, } #endif

+static inline void kmb_write(void *reg, u32 value) +{ + writel(value, reg); +} + static inline void kmb_write_lcd(unsigned int reg, u32 value) { writel(value, (LCD_BASE_ADDR + reg)); @@ -85,7 +90,7 @@ static inline u32 kmb_read_mipi(unsigned int reg) }

static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, - u32 num_bits, u32 value) + u32 num_bits, u32 value) { u32 reg_val = kmb_read_mipi(reg); u32 mask = (1 << num_bits) - 1; @@ -97,6 +102,20 @@ static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, kmb_write_mipi(reg, reg_val); }

+static inline void kmb_set_bit_mipi(unsigned int reg, u32 offset) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, reg_val | (1 << offset)); +} + +static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, reg_val & (~(1 << offset))); +} + int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 2326d3b..a5b9681 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -503,10 +503,41 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, mipi_tx_fg_cfg_regs(dev_priv, frame_gen, &fg_t_cfg); }

+static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) +{ + u32 fifo_size, fifo_rthreshold; + u32 ctrl_no = MIPI_CTRL6; + + /*clear all mc fifo channel sizes and thresholds*/ + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); + + fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? + MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : + MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; + /*MC fifo size for virtual channels 0-3 */ + /* + *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 + *REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 + */ + SET_MC_FIFO_CHAN_ALLOC(ctrl_no, vchannel_id, fifo_size); + + /*set threshold to half the fifo size, actual size=size*16*/ + fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; + SET_MC_FIFO_RTHRESHOLD(ctrl_no, vchannel_id, fifo_rthreshold); + + /*enable the MC FIFO channel corresponding to the Virtual Channel */ + kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; + u8 active_vchannels = 0; u8 frame_id, sect; u32 bits_per_pclk = 0; u32 word_count = 0; @@ -544,18 +575,23 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv,

/* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, - ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); - /*function for setting frame sepecific parameters will be - * called here - */ - /*bits_per_pclk and word_count will be passed in to this - * function - */ + bits_per_pclk, + word_count, + ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + + active_vchannels++;

+ /*connect lcd to mipi */ + kmb_write(MSS_CAM_BASE_ADDR + MIPI_TX_MSS_LCD_MIPI_CFG, 1); + + break; } + + if (active_vchannels == 0) + return -EINVAL; + /*Multi-Channel FIFO Configuration*/ + mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); return ret; }

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index e50cd88..d1ec5a6 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -35,6 +35,9 @@ struct kmb_connector { #define MIPI_TX_FRAME_GEN 4 #define MIPI_TX_FRAME_GEN_SECTIONS 4 #define MIPI_CTRL_VIRTUAL_CHANNELS 4 +#define MIPI_D_LANES_PER_DPHY 2 +#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 +#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511

enum mipi_ctrl_num { MIPI_CTRL0 = 0, diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 600838f..ef6b4ee 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -11,6 +11,7 @@ #define MIPI_BASE_ADDR (void *)(0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (void *)(0x20930000) +#define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000)

/*************************************************************************** * LCD controller control register defines @@ -375,6 +376,9 @@ ***********************************************i****************************/ #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) #define MIPI_CTRL_HS_BASE_ADDR (0x400) + +#define MIPI_TX_HS_CTRL (0x0) +#define MIPI_TX_HS_SYNC_CFG (0x8) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ (0x400*M) + (0x2C*N) + (8*O)) @@ -389,10 +393,10 @@ #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ - (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) -#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) (MIPI_TX_HS_FG0_SECT0_LINE_CFG \ - + (0x400*M) + (0x2C*N) + (8*O)) + (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) +#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ + (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O))

#define MIPI_TX_HS_FG0_NUM_LINES (0x68) #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ @@ -431,4 +435,24 @@ #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + (0x400*M) + (0x4*N))

+#define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) +#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ + + (0x400*M)) +#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) +#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) +#define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ + (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N)) +#define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \ + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \ + (vc % 2)*16, 16, sz) +#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) +#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) +#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ + (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N)) +#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ + (vc % 2)*16, 16, th) + +#define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) +#define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */

Mipi HS registers start at an additional offset of 0x400 which needs to be added at the register macro definition and not at the read/write function level.

v2: replaced calculations with macro to make code simpler Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 16 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 116 ++++++++++++++++++++++++----------------- 2 files changed, 75 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index a685a7a..a255210 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -423,20 +423,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2) * 16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); + offset = (frame_gen % 2)*16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width);

- /*v backporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); + /*v backporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch);

- /*v frontporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); + /*v frontporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch);

- /*v active - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); + /*v active - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active);

/*hsyc width */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 2d25c50..381e255 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -375,10 +375,10 @@ * MIPI controller control register defines ***********************************************i****************************/ #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) -#define MIPI_CTRL_HS_BASE_ADDR (0x400) +#define HS_OFFSET(M) ((M + 1) * 0x400)

#define MIPI_TX_HS_CTRL (0x0) -#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) #define HS_CTRL_EN (1 << 0) #define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ #define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ @@ -391,7 +391,7 @@ #define HSCLKIDLE_CNT (1 << 24) #define MIPI_TX_HS_SYNC_CFG (0x8) #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ - + (0x400*M)) + + HS_OFFSET(M)) #define LINE_SYNC_PKT_ENABLE (1 << 0) #define FRAME_COUNTER_ACTIVE (1 << 1) #define LINE_COUNTER_ACTIVE (1 << 2) @@ -408,75 +408,93 @@ #define FRAME_GEN_EN(f) ((f) << 23) #define HACT_WAIT_STOP(f) ((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) -#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ - (0x400*M) + (0x2C*N) + (8*O)) -#define MIPI_TX_SECT_WC_MASK (0xffff) -#define MIPI_TX_SECT_VC_MASK (3) -#define MIPI_TX_SECT_VC_SHIFT (22) -#define MIPI_TX_SECT_DT_MASK (0x3f) -#define MIPI_TX_SECT_DT_SHIFT (16) -#define MIPI_TX_SECT_DM_MASK (3) -#define MIPI_TX_SECT_DM_SHIFT (24) -#define MIPI_TX_SECT_DMA_PACKED (1<<26) +#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ + HS_OFFSET(M) + (0x2C*N) + (8*O)) +#define MIPI_TX_SECT_WC_MASK (0xffff) +#define MIPI_TX_SECT_VC_MASK (3) +#define MIPI_TX_SECT_VC_SHIFT (22) +#define MIPI_TX_SECT_DT_MASK (0x3f) +#define MIPI_TX_SECT_DT_SHIFT (16) +#define MIPI_TX_SECT_DM_MASK (3) +#define MIPI_TX_SECT_DM_SHIFT (24) +#define MIPI_TX_SECT_DMA_PACKED (1<<26) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) -#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ - (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) +#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ + (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \ + + HS_OFFSET(M) + (0x2C*N)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) -#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ - (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O)) +#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ + (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \ + + (0x2C*N) + (8*O))

#define MIPI_TX_HS_FG0_NUM_LINES (0x68) -#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ - (0x400*M) + (0x2C*N)) +#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ + (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \ + + (0x2C*N)) #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) -#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) -#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ + (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) -#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ + (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_ACTIVE0 (0x17c) -#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_ACTIVEn(M, N) \ + (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) -#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_BACKPORCH0 (0x11c) -#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_BACKPORCHn(M, N) \ + (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) -#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \ + (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_ACTIVE0 (0x184) -#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_ACTIVEn(M, N) \ + (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) -#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) -#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \ + (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) -#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ - + (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \ + (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) + #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) -#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ - + (0x400*M)) +#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \ + (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M)) + #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ - (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N)) + (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ + + (0x4*N)) #define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \ - kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \ - (vc % 2)*16, 16, sz) + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ + vc/2), (vc % 2)*16, 16, sz) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) -#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ - (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N)) -#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ +#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ + (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \ + + (0x4*N)) +#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th)

This is part2 of DPHY initialization- sets up DPHY PLLs.

v2: simplified mipi_tx_get_vco_params() based on review v3: added WARN_ON for invalid freq v4: fixed bug in mipi_tx_get_vco_params

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 194 +++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 2 + 2 files changed, 189 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index d15cf6f..02555c6 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -28,11 +28,33 @@ #define MIPI_TX_CFG_CLK_KHZ 24000

/*DPHY Tx test codes*/ -#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 -#define TEST_CODE_PLL_ANALOG_PROG 0x1F -#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 -#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 -#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 +#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E +#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F +#define TEST_CODE_PLL_VCO_CTRL 0x12 +#define TEST_CODE_PLL_GMP_CTRL 0x13 +#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 +#define TEST_CODE_PLL_LOCK_FILTER 0x15 +#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 +#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 +#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 +#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) +#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 +#define PLL_N_OVR_EN (1 << 4) +#define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C +#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D +#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 +#define TEST_CODE_PLL_ANALOG_PROG 0x1F +#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 +#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 +#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 + +/* D-Phy params */ +#define PLL_N_MIN 0 +#define PLL_N_MAX 15 +#define PLL_M_MIN 62 +#define PLL_M_MAX 623 +#define PLL_FVCO_MAX 1250

/* * These are added here only temporarily for testing, @@ -780,8 +802,158 @@ static inline void set_test_mode_src_osc_freq_target_hi_bits(u32 dphy_no, test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); }

+struct vco_params { + u32 freq; + u32 range; + u32 divider; +}; + +static struct vco_params vco_table[] = { + {52, 0x3f, 8}, + {80, 0x39, 8}, + {105, 0x2f, 4}, + {160, 0x29, 4}, + {210, 0x1f, 2}, + {320, 0x19, 2}, + {420, 0x0f, 1}, + {630, 0x09, 1}, + {1100, 0x03, 1}, + {0xffff, 0x01, 1}, +}; + +static void mipi_tx_get_vco_params(struct vco_params *vco) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vco_table); i++) { + if (vco->freq < vco_table[i].freq) { + *vco = vco_table[i]; + return; + } + } + WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); +} + +static void mipi_tx_pll_setup(u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) +{ + /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz + * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) + * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) + * n: - valid range [0 15] + * N: - N = n + 1 + * -valid range: [1 16] + * -conditions: - (pll_ref_clk / N) >= 2 MHz + * -(pll_ref_clk / N) <= 8 MHz + * m: valid range [62 623] + * M: - M = m + 2 + * -valid range [64 625] + * -Fvco = (M/N) * pll_ref_clk + */ + struct vco_params vco_p = { + .range = 0, + .divider = 1, + }; + u32 best_n = 0, best_m = 0; + u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; + u32 best_freq_delta = 3000; + + vco_p.freq = target_freq_mhz; + mipi_tx_get_vco_params(&vco_p); + /*search pll n parameter */ + for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) { + /*calculate the pll input frequency division ratio + * multiply by 1000 for precision - + * no floating point, add n for rounding + */ + div = ((ref_clk_mhz * 1000) + n)/(n+1); + /*found a valid n parameter */ + if ((div < 2000 || div > 8000)) + continue; + /*search pll m parameter */ + for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) { + /*calculate the Fvco(DPHY PLL output frequency) + * using the current n,m params + */ + freq = div * (m + 2); + freq /= 1000; + /* trim the potential pll freq to max supported*/ + if (freq > PLL_FVCO_MAX) + continue; + + delta = abs(freq - target_freq_mhz); + /*select the best (closest to target pll freq) + * n,m parameters so far + */ + if (delta < best_freq_delta) { + best_n = n; + best_m = m; + best_freq_delta = delta; + } + } + } + + /*Program vco_cntrl parameter + *PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, + * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en + */ + test_mode_send(dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range + | (1 << 6))); + + /*Program m, n pll parameters */ + + /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ + test_mode_send(dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, (best_n & 0x0f)); + + /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ + test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + (best_m & 0x1f)); + + /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ + test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); + + /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en*/ + test_mode_send(dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, + (PLL_N_OVR_EN | PLL_M_OVR_EN)); + + /*Program Charge-Pump parameters */ + + /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ + t_freq = target_freq_mhz * vco_p.divider; + test_mode_send(dphy_no, TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, + ((t_freq > 1150) ? 0x0C : 0x0B)); + + /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ + test_mode_send(dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, + 0x00); + + /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ + test_mode_send(dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); + + /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ + test_mode_send(dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); + + /*PLL Lock Configuration */ + + /*pll_th1 -Lock Detector Phase error threshold, + * document gives fixed value + */ + test_mode_send(dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); + + /*pll_th2 - Lock Filter length, document gives fixed value */ + test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); + + /*pll_th3- PLL Unlocking filter, document gives fixed value */ + test_mode_send(dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03); + + /*pll_lock_sel-PLL Lock Detector Selection, document gives + * fixed value + */ + test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); +} + static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, - enum dphy_mode mode) + enum dphy_mode mode) { u32 test_code = 0; u32 test_data = 0, val; @@ -884,7 +1056,15 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, /*Set PLL regulator in bypass */ test_mode_send(dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01);

- /*TODO - PLL Parameters Setup */ + /* PLL Parameters Setup */ + mipi_tx_pll_setup(dphy_no, cfg->ref_clk_khz/1000, + cfg->lane_rate_mbps/2); + + /*Set clksel */ + kmb_write_bits_mipi(DPHY_INIT_CTRL1, 18, 2, 0x01); + + /*Set pll_shadow_control */ + kmb_write_bits_mipi(DPHY_INIT_CTRL1, 16, 1, 0x01); }

/*Send NORMAL OPERATION test code */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 899a5d3..9ed91ea 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -504,6 +504,7 @@ /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104) +#define DPHY_INIT_CTRL1 (0x108) #define SHUTDOWNZ 0 #define RESETZ 12 #define DPHY_INIT_CTRL2 (0x10c) @@ -513,6 +514,7 @@ #define CLR_DPHY_INIT_CTRL0(dphy, offset) \ kmb_clr_bit_mipi(DPHY_INIT_CTRL0, \ (dphy+offset)) +#define DPHY_INIT_CTRL2 (0x10c) #define DPHY_FREQ_CTRL0_3 (0x11c) #define SET_DPHY_FREQ_CTRL0_3(dphy, val) \ kmb_write_bits_mipi(DPHY_FREQ_CTRL0_3 \

This initializes the interrupts for DSI. This is the final part of mipi DSI initialization.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 1 + drivers/gpu/drm/kmb/kmb_drv.h | 30 +++++++++++----- drivers/gpu/drm/kmb/kmb_dsi.c | 46 ++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 13 +++++++ drivers/gpu/drm/kmb/kmb_regs.h | 81 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 163 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 224a7f8..19f78ba 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -58,6 +58,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) if (ret && ret != -ENODEV) return ret;

+ spin_lock_init(&lcd->irq_lock); ret = kmb_setup_crtc(drm); if (ret < 0) { DRM_ERROR("failed to create crtc\n"); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 3996c84..14bdfc8 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -12,14 +12,15 @@ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */

struct kmb_drm_private { - struct drm_device drm; - void __iomem *mmio; - unsigned char n_layers; - struct clk *clk; - struct drm_fbdev_cma *fbdev; - struct drm_crtc crtc; - struct kmb_plane *plane; - struct drm_atomic_state *state; + struct drm_device drm; + void __iomem *mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_fbdev_cma *fbdev; + struct drm_crtc crtc; + struct kmb_plane *plane; + struct drm_atomic_state *state; + spinlock_t irq_lock; };

static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) @@ -111,6 +112,19 @@ static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset) kmb_write_mipi(reg, reg_val & (~(1 << offset))); }

+static inline void kmb_set_bitmask_mipi(unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, (reg_val | mask)); +} + +static inline void kmb_clr_bitmask_mipi(unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, (reg_val & (~mask))); +} int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index f8ddb87..47456b2 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -5,6 +5,7 @@

#include <linux/gpio/consumer.h> #include <linux/slab.h> +#include <linux/spinlock.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> @@ -188,6 +189,11 @@ static mipi_hs_freq_range_cfg {.default_bit_rate_mbps = 2500, .hsfreqrange_code = 0x49} };

+union mipi_irq_cfg int_cfg = { + .irq_cfg.frame_done = 1, + .irq_cfg.ctrl_error = 1, +}; + static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -1174,6 +1180,43 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) return 0; }

+static void mipi_tx_init_irqs(union mipi_irq_cfg *cfg, + struct kmb_drm_private *dev_priv, + struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) +{ + unsigned long irqflags; + uint8_t vc; + + /* clear all interrupts first */ + /*local interrupts */ + SET_MIPI_TX_HS_IRQ_CLEAR(MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); + /*global interrupts */ + SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_HS_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR1(MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); + + /*enable interrupts */ + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { + if (tx_ctrl_cfg->frames[vc] == NULL) + continue; + /*enable FRAME_DONE interrupt if VC is configured */ + SET_HS_IRQ_ENABLE(MIPI_CTRL6, + MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); + break; /*only one vc for LCD interface */ + } + + /*enable user enabled interrupts */ + if (cfg->irq_cfg.dphy_error) + SET_MIPI_CTRL_IRQ_ENABLE0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + if (cfg->irq_cfg.line_compare) + SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_LINE_COMPARE); + if (cfg->irq_cfg.ctrl_error) + SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; @@ -1219,4 +1262,7 @@ void kmb_dsi_init(struct drm_device *dev)

/*d-phy initialization */ mipi_tx_init_dphy(&mipi_tx_init_cfg); + + /* irq initialization */ + mipi_tx_init_irqs(&int_cfg, dev_priv, &mipi_tx_init_cfg.tx_ctrl_cfg); } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 7db7f58..810c5c7 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -295,6 +295,19 @@ struct mipi_ctrl_cfg { uint32_t data_if; /*MIPI_IF_DMA or MIPI_IF_PARALLEL */ struct mipi_tx_ctrl_cfg tx_ctrl_cfg; }; + +/*structure for storing user specified interrupts that are enabled */ +union mipi_irq_cfg { + uint8_t value; + struct { + uint8_t line_compare : 1; + uint8_t dma_event : 1; + uint8_t frame_done : 1; + uint8_t ctrl_error : 1; + uint8_t dphy_error : 1; + } irq_cfg; +}; + void kmb_dsi_init(struct drm_device *dev); void kmb_plane_destroy(struct drm_plane *plane);

diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index eec434e7..5d08ee4 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -501,6 +501,87 @@ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th)

+/* MIPI IRQ */ +#define MIPI_CTRL_IRQ_STATUS0 (0x00) +#define MIPI_DHY_ERR_IRQ 1 +#define MIPI_HS_IRQ 13 +#define MIPI_LP_EVENT_IRQ 25 +#define MIPI_CTRL_IRQ_STATUS1 (0x04) +#define MIPI_HS_RX_EVENT_IRQ 0 +#define MIPI_CTRL_IRQ_ENABLE0 (0x08) +#define SET_MIPI_CTRL_IRQ_ENABLE0(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_ENABLE0, M+N) +#define MIPI_CTRL_IRQ_ENABLE1 (0x0c) +#define MIPI_CTRL_IRQ_CLEAR0 (0x010) +#define SET_MIPI_CTRL_IRQ_CLEAR0(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR0, M+N) +#define MIPI_CTRL_IRQ_CLEAR1 (0x014) +#define SET_MIPI_CTRL_IRQ_CLEAR1(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR1, M+N) +#define MIPI_TX_HS_IRQ_STATUS (0x01c) +#define MIPI_TX_HS_IRQ_STATUSm(M) \ + (MIPI_TX_HS_IRQ_STATUS + HS_OFFSET(M)) +#define MIPI_TX_HS_IRQ_LINE_COMPARE (1<<1) +#define MIPI_TX_HS_IRQ_FRAME_DONE_0 (1<<2) +#define MIPI_TX_HS_IRQ_FRAME_DONE_1 (1<<3) +#define MIPI_TX_HS_IRQ_FRAME_DONE_2 (1<<4) +#define MIPI_TX_HS_IRQ_FRAME_DONE_3 (1<<5) +#define MIPI_TX_HS_IRQ_DMA_DONE_0 (1<<6) +#define MIPI_TX_HS_IRQ_DMA_IDLE_0 (1<<7) +#define MIPI_TX_HS_IRQ_DMA_DONE_1 (1<<8) +#define MIPI_TX_HS_IRQ_DMA_IDLE_1 (1<<9) +#define MIPI_TX_HS_IRQ_DMA_DONE_2 (1<<10) +#define MIPI_TX_HS_IRQ_DMA_IDLE_2 (1<<11) +#define MIPI_TX_HS_IRQ_DMA_DONE_3 (1<<12) +#define MIPI_TX_HS_IRQ_DMA_IDLE_3 (1<<13) +#define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW (1<<14) +#define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW (1<<15) +#define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY (1<<16) +#define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL (1<<17) +#define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR (1<<18) +#define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR (1<<20) +#define MIPI_TX_HS_IRQ_FRAME_DONE \ + (MIPI_TX_HS_IRQ_FRAME_DONE_0 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_1 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_2 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_3) + +#define MIPI_TX_HS_IRQ_DMA_DONE \ + (MIPI_TX_HS_IRQ_DMA_DONE_0 | \ + MIPI_TX_HS_IRQ_DMA_DONE_1 | \ + MIPI_TX_HS_IRQ_DMA_DONE_2 | \ + MIPI_TX_HS_IRQ_DMA_DONE_3) + +#define MIPI_TX_HS_IRQ_DMA_IDLE \ + (MIPI_TX_HS_IRQ_DMA_IDLE_0 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_1 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_2 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_3) + +#define MIPI_TX_HS_IRQ_ERROR \ + (MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW | \ + MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW | \ + MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY | \ + MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL | \ + MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR | \ + MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR) + +#define MIPI_TX_HS_IRQ_ALL \ + (MIPI_TX_HS_IRQ_FRAME_DONE | \ + MIPI_TX_HS_IRQ_DMA_DONE | \ + MIPI_TX_HS_IRQ_DMA_IDLE | \ + MIPI_TX_HS_IRQ_LINE_COMPARE | \ + MIPI_TX_HS_IRQ_ERROR) + +#define MIPI_TX_HS_IRQ_ENABLE (0x020) +#define SET_HS_IRQ_ENABLE(M, val) \ + kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_ENABLE \ + + HS_OFFSET(M), val) +#define MIPI_TX_HS_IRQ_CLEAR (0x024) +#define SET_MIPI_TX_HS_IRQ_CLEAR(M, val) \ + kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_CLEAR \ + + HS_OFFSET(M), val) + /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104)

This code is commented out until firmware is updated to redirect LCD IRQ from MSSCPU to A53.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 5192040..594e64c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -29,12 +29,16 @@ #include "kmb_plane.h" #include "kmb_regs.h"

+/*IRQ handler*/ +static irqreturn_t kmb_isr(int irq, void *arg); + static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = to_kmb(drm); struct platform_device *pdev = to_platform_device(drm->dev); /*struct resource *res;*/ /*u32 version;*/ + /*int irq_lcd, irq_mipi; */ int ret;

/* TBD - not sure if clock_get needs to be called here */ @@ -85,6 +89,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE);

+ /*TODO - register irqs here - section 17.3 in databook + * lists LCD at 79 under MSS CPU - firmware has to redirect it to A53 + * May be 33 for LCD and 34 for MIPI? Will wait till firmware + * finalizes the IRQ numbers for redirection + */ + /*TBD read and check for correct product version here */

/* Get the optional framebuffer memory resource */ @@ -132,7 +142,7 @@ static void kmb_setup_mode_config(struct drm_device *drm) drm->mode_config.funcs = &kmb_mode_config_funcs; }

-static irqreturn_t kmb_irq(int irq, void *arg) +static irqreturn_t kmb_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; unsigned long status, val; @@ -178,8 +188,9 @@ DEFINE_DRM_GEM_CMA_FOPS(fops);

static struct drm_driver kmb_driver = { .driver_features = DRIVER_GEM | - DRIVER_MODESET | DRIVER_ATOMIC, - .irq_handler = kmb_irq, + DRIVER_MODESET | + DRIVER_ATOMIC, + .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, .gem_free_object_unlocked = drm_gem_cma_free_object,

Myriadx code has it set to these values.

v2: upclassed dev_private

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 5c1e858..eca0f3a 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -102,6 +102,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_H_BACKPORCH, vm.hback_porch - 1); kmb_write_lcd(dev_p, LCD_H_FRONTPORCH, vm.hfront_porch - 1); kmb_write_lcd(dev_p, LCD_HSYNC_WIDTH, vm.hsync_len - 1); + /*this is hardcoded as 0 in the Myriadx code */ + kmb_write_lcd(dev_p, LCD_VSYNC_START, 0); + kmb_write_lcd(dev_p, LCD_VSYNC_END, 0);

if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev_p, @@ -112,10 +115,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); kmb_write_lcd(dev_p, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); - kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, - vsync_start_offset); - kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, - vsync_end_offset); + /*this is hardcoded as 10 in the Myriadx code*/ + kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, 10); + kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10); } /* enable VL1 layer as default */ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;

Find ADV 7535 from the device tree and get the bridge driver and attach it to the DRM and the MIPI encoder.

v2: check for valid encoder node

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 27 ++++++++++++++++++++++++++- drivers/gpu/drm/kmb/kmb_dsi.c | 26 +++++++++++++++++++++----- drivers/gpu/drm/kmb/kmb_dsi.h | 3 ++- 3 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index f4553c2..5a2ff9d 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -36,10 +36,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = to_kmb(drm); struct platform_device *pdev = to_platform_device(drm->dev); + struct drm_bridge *bridge; /*struct resource *res;*/ /*u32 version;*/ int irq_lcd, irq_mipi; int ret; + struct device_node *encoder_node;

/* TBD - not sure if clock_get needs to be called here */ /* @@ -127,7 +129,30 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

- kmb_dsi_init(drm); + /* find ADV7535 node and initialize it */ + encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0); + if (!encoder_node) { + DRM_ERROR("failed to get bridge info from DT\n"); + ret = -EPROBE_DEFER; + goto setup_fail; + } + + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(encoder_node); + if (!bridge) { + DRM_ERROR("failed to get bridge driver from DT\n"); + ret = -EPROBE_DEFER; + goto setup_fail; + } + + of_node_put(encoder_node); + + ret = kmb_dsi_init(drm, bridge); + if (ret) { + DRM_ERROR("failed to initialize DSI\n"); + goto setup_fail; + } + ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 969890b..09d5805 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -7,6 +7,7 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_crtc_helper.h> @@ -1240,7 +1241,6 @@ static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); }

- void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) { uint32_t irq_ctrl_stat_0, hs_stat, hs_enable; @@ -1273,7 +1273,7 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)

}

-void kmb_dsi_init(struct drm_device *dev) +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1281,21 +1281,27 @@ void kmb_dsi_init(struct drm_device *dev) struct drm_connector *connector; struct kmb_dsi_host *host; struct kmb_drm_private *dev_p = dev->dev_private; + int ret = 0;

kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); - if (!kmb_dsi) - return; + if (!kmb_dsi) { + DRM_ERROR("failed to allocate kmb_dsi\n"); + return -ENOMEM; + }

kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); - return; + DRM_ERROR("failed to allocate kmb_connector\n"); + return -ENOMEM; }

kmb_dsi->attached_connector = kmb_connector;

connector = &kmb_connector->base; encoder = &kmb_dsi->base; + encoder->possible_crtcs = 1; + encoder->possible_clones = 0; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI");

@@ -1313,6 +1319,14 @@ void kmb_dsi_init(struct drm_device *dev) connector->encoder = encoder; drm_connector_attach_encoder(connector, encoder);

+ /* Link drm_bridge to encoder */ + ret = drm_bridge_attach(encoder, bridge, NULL, 0); + if (ret) { + DRM_ERROR("failed to attach bridge to MIPI\n"); + drm_encoder_cleanup(encoder); + return ret; + } + /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg);

@@ -1321,4 +1335,6 @@ void kmb_dsi_init(struct drm_device *dev)

/* irq initialization */ mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + + return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index f7e2f9e..702ad58 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -18,6 +18,7 @@ struct kmb_dsi { struct drm_encoder base; struct kmb_connector *attached_connector; struct kmb_dsi_host *dsi_host; + struct drm_bridge *bridge; };

struct kmb_dsi_host { @@ -308,7 +309,7 @@ union mipi_irq_cfg { } irq_cfg; };

-void kmb_dsi_init(struct drm_device *dev); +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p);

cleanup code

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 5 +++-- drivers/gpu/drm/kmb/kmb_drv.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 71fdb94..78cb91b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -282,8 +282,7 @@ DEFINE_DRM_GEM_CMA_FOPS(fops);

static struct drm_driver kmb_driver = { .driver_features = DRIVER_GEM | - DRIVER_MODESET | - DRIVER_ATOMIC, + DRIVER_MODESET | DRIVER_ATOMIC, .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, @@ -362,6 +361,8 @@ static int kmb_drm_bind(struct device *dev) if (ret) goto err_register;

+ drm_fbdev_generic_setup(drm, 32); + return 0;

err_register: diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 586b53e..1150505 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -18,7 +18,6 @@ struct kmb_drm_private { void __iomem *msscam_mmio; unsigned char n_layers; struct clk *clk; - struct drm_fbdev_cma *fbdev; struct drm_crtc crtc; struct kmb_plane *plane; struct drm_atomic_state *state;

Also added debug messages

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 16 ++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 6 +++--- 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 4afdb9c..d13552a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -29,6 +29,7 @@ #include "kmb_plane.h" #include "kmb_regs.h"

+#define DEBUG /*IRQ handler*/ static irqreturn_t kmb_isr(int irq, void *arg);

@@ -327,6 +328,7 @@ static int kmb_drm_bind(struct device *dev) dev_set_drvdata(dev, drm);

kmb_setup_mode_config(drm); + DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n"); ret = kmb_load(drm, 0); if (ret) goto err_free; @@ -439,17 +441,27 @@ static int kmb_probe(struct platform_device *pdev) { struct device_node *port; struct component_match *match = NULL; + int ret;

/* there is only one output port inside each device, find it */ + DRM_DEBUG("%s : ENTER", __func__); + port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); + DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port); if (!port) return -ENODEV;

+ DRM_DEBUG("%s : after get_remote", __func__); + DRM_DEBUG("Adding component %pOF\n", port); drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); + DRM_DEBUG("%s : after get_match", __func__); of_node_put(port);

- return component_master_add_with_match(&pdev->dev, &kmb_master_ops, - match); + ret = component_master_add_with_match(&pdev->dev, &kmb_master_ops, + match); + + DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret); + return ret; }

static int kmb_remove(struct platform_device *pdev) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 85b55cb..e98e144 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -13,9 +13,9 @@ /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (0x20930000) #define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000) -#define LCD_MMIO_SIZE (0x10000) -#define MIPI_MMIO_SIZE (0x10000) -#define MSS_CAM_MMIO_SIZE (0x10000) +#define LCD_MMIO_SIZE (0x3000) +#define MIPI_MMIO_SIZE (0x4000) +#define MSS_CAM_MMIO_SIZE (0x10)

/*************************************************************************** * LCD controller control register defines

of probe and return probe_defer early on, so that all the other initializations can be done after adv driver is loaded successfully.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 74 +++++++++++++--------- drivers/gpu/drm/kmb/kmb_dsi.c | 144 ++++++++++++++++++++++++++---------------- drivers/gpu/drm/kmb/kmb_dsi.h | 6 +- 3 files changed, 138 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 36edfbf..76f3c43 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -37,11 +37,24 @@ static struct clk *clk_lcd; static struct clk *clk_mipi;

static int probe_deferred; +struct drm_bridge *adv_bridge;

static int kmb_display_clk_enable(void) { - clk_prepare_enable(clk_lcd); - clk_prepare_enable(clk_mipi); + int ret; + + ret = clk_prepare_enable(clk_lcd); + if (ret) { + DRM_ERROR("Failed to enable LCD clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(clk_mipi); + if (ret) { + DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); + return ret; + } + DRM_INFO("SUCCESS : enabled LCD MIPI clocks\n"); return 0; }

@@ -86,8 +99,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) *} */ /* LCD mmio */ - if (!probe_deferred) { - probe_deferred = 1; + probe_deferred = 1;

if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) { DRM_ERROR("failed to reserve LCD registers\n"); @@ -120,9 +132,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has to redirect it to A53 */ -/*TBD read and check for correct product version here */

- /* Get the optional framebuffer memory resource */ + /*TBD read and check for correct product version here */ + + /* Get the optional framebuffer memory resource */ ret = of_reserved_mem_device_init(drm->dev); if (ret && ret != -ENODEV) return ret; @@ -134,8 +147,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

-/* ret = kmb_dsi_init(drm, bridge);*/ - ret = kmb_dsi_init(drm); + ret = kmb_dsi_init(drm, adv_bridge); if (ret == -EPROBE_DEFER) { DRM_INFO("%s: wait for external bridge driver DT", __func__); return -EPROBE_DEFER; @@ -143,7 +155,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } -} /* enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (!clk_lcd) { @@ -157,10 +168,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } DRM_INFO("%s : %d\n", __func__, __LINE__); - kmb_display_clk_enable(); - - DRM_INFO("%s : %d\n", __func__, __LINE__); + ret = kmb_display_clk_enable();

+ DRM_INFO("%s : %d clk enabling ret=%d\n", __func__, __LINE__, ret); return 0;

drm_crtc_cleanup(&dev_p->crtc); @@ -268,7 +278,7 @@ static struct drm_driver kmb_driver = { .gem_prime_vunmap = drm_gem_cma_prime_vunmap, .gem_prime_mmap = drm_gem_cma_prime_mmap, .fops = &fops, - .name = "kmb", + .name = "kmb_display", .desc = "KEEMBAY DISPLAY DRIVER ", .date = "20190122", .major = 1, @@ -277,7 +287,7 @@ static struct drm_driver kmb_driver = {

static int kmb_drm_bind(struct device *dev) { - struct drm_device *drm; + struct drm_device *drm = NULL; struct kmb_drm_private *lcd; int ret;

@@ -296,7 +306,9 @@ static int kmb_drm_bind(struct device *dev) dev_set_drvdata(dev, drm);

kmb_setup_mode_config(drm); - DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n"); + dev_set_drvdata(dev, drm); + + /* load the driver */ ret = kmb_load(drm, 0); DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); if (ret == -EPROBE_DEFER) { @@ -337,7 +349,6 @@ static int kmb_drm_bind(struct device *dev) drm_kms_helper_poll_fini(drm); err_vblank: pm_runtime_disable(drm->dev); - component_unbind_all(dev, drm); of_node_put(lcd->crtc.port); lcd->crtc.port = NULL; drm_irq_uninstall(drm); @@ -355,9 +366,9 @@ static void kmb_drm_unbind(struct device *dev) struct drm_device *drm = dev_get_drvdata(dev); struct kmb_drm_private *dev_p = to_kmb(drm);

+ dump_stack(); drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); - component_unbind_all(dev, drm); of_node_put(dev_p->crtc.port); dev_p->crtc.port = NULL; pm_runtime_get_sync(drm->dev); @@ -365,12 +376,15 @@ static void kmb_drm_unbind(struct device *dev) pm_runtime_put_sync(drm->dev); pm_runtime_disable(drm->dev);

+ DRM_INFO("%s : %d\n", __func__, __LINE__); if (dev_p->lcd_mmio) { + DRM_INFO("%s : %d\n", __func__, __LINE__); iounmap(dev_p->lcd_mmio); release_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE); }

if (dev_p->mipi_mmio) { + DRM_INFO("%s : %d\n", __func__, __LINE__); iounmap(dev_p->mipi_mmio); release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); } @@ -378,6 +392,7 @@ static void kmb_drm_unbind(struct device *dev) if (dev_p->msscam_mmio) iounmap(dev_p->msscam_mmio);

+ DRM_INFO("%s : %d\n", __func__, __LINE__); of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm);

@@ -389,32 +404,31 @@ static void kmb_drm_unbind(struct device *dev) drm_dev_put(drm); drm->dev_private = NULL; dev_set_drvdata(dev, NULL); + DRM_INFO("%s : %d\n", __func__, __LINE__); }

-static const struct component_master_ops kmb_master_ops = { - .bind = kmb_drm_bind, - .unbind = kmb_drm_unbind, -}; - static int kmb_probe(struct platform_device *pdev) { - struct device_node *port; - int ret = 0; + struct device *device = get_device(&pdev->dev);

/* there is only one output port inside each device, find it */ DRM_DEBUG("%s : ENTER", __func__);

- port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); - DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port); - if (!port) - return -ENODEV; - DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret); + adv_bridge = kmb_dsi_host_bridge_init(device); + if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) + return -EPROBE_DEFER; + else if (adv_bridge < 0) { + DRM_ERROR(" PROBE failed\n"); + return -EINVAL; + } + return kmb_drm_bind(&pdev->dev); }

static int kmb_remove(struct platform_device *pdev) { - component_master_del(&pdev->dev, &kmb_master_ops); +// component_master_del(&pdev->dev, &kmb_master_ops); + kmb_drm_unbind(&pdev->dev); return 0; }

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 2bc63e2..6e4b8da 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -59,6 +59,9 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250

+static struct mipi_dsi_host *dsi_host; +static struct mipi_dsi_device *dsi_device; + /* * These are added here only temporarily for testing, * these will eventually go to the device tree sections, @@ -273,33 +276,68 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct kmb_dsi *kmb_dsi) { struct kmb_dsi_host *host; - struct mipi_dsi_device *device; - int err;

host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL;

- host->base.ops = &kmb_dsi_host_ops; + host->base = dsi_host; + host->base->ops = &kmb_dsi_host_ops; host->kmb_dsi = kmb_dsi;

- device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { - kfree(host); - return NULL; - } + host->base->dev = drm->dev; + + dsi_device->host = host->base; + host->device = dsi_device; + return host; +}

- host->base.dev = drm->dev; - err = mipi_dsi_host_register(&host->base); - if (err < 0) { - DRM_ERROR("failed to register DSI host: %d\n", err); - kfree(host); - kfree(device); +struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) +{ + int ret; + struct device_node *encoder_node; + struct drm_bridge *bridge; + + if (!dsi_host) { + dsi_host = kzalloc(sizeof(*dsi_host), GFP_KERNEL); + if (!dsi_host) + return ERR_PTR(-ENOMEM); + + dsi_host->ops = &kmb_dsi_host_ops; + + if (!dsi_device) + dsi_device = kzalloc(sizeof(*dsi_device), GFP_KERNEL); + if (!dsi_device) { + kfree(dsi_host); + return ERR_PTR(-ENOMEM); + } + + dsi_host->dev = dev; + ret = mipi_dsi_host_register(dsi_host); + if (ret < 0) { + DRM_ERROR("failed to register DSI host: %d\n", ret); + kfree(dsi_host); + kfree(dsi_device); + return ERR_PTR(ret); + } }

- device->host = &host->base; - host->device = device; - return host; + /* find ADV7535 node and initialize it */ + DRM_DEBUG("trying to get bridge info %pOF\n", dev->of_node); + encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); + DRM_DEBUG("encoder node = %pOF\n", encoder_node); + if (!encoder_node) { + DRM_ERROR("failed to get bridge info from DT\n"); + ret = -EINVAL; + } + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(encoder_node); + of_node_put(encoder_node); + if (!bridge) { + DRM_INFO("wait for external bridge driver DT\n"); + return ERR_PTR(-EPROBE_DEFER); + } + return bridge; }

u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, @@ -662,7 +700,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6;

- /*MIPI_TX_HS_SYNC_CFG */ + DRM_INFO("%s : %d\n", __func__, __LINE__); + /*MIPI_TX_HS_SYNC_CFG*/ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -673,6 +712,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= DSI_V_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) sync_cfg |= DSI_HSA_BLANKING; + DRM_INFO("%s : %d\n", __func__, __LINE__); if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) sync_cfg |= DSI_HBP_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) @@ -684,6 +724,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) sync_cfg |= DSI_LPM_LAST_VFP_LINE; /* enable frame generator */ + DRM_INFO("%s : %d\n", __func__, __LINE__); fg_en = 1 << fg_id; sync_cfg |= FRAME_GEN_EN(fg_en); if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) @@ -702,7 +743,9 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43);

+ DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); }

@@ -1284,8 +1327,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)

}

-//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) -int kmb_dsi_init(struct drm_device *dev) +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) +//int kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1293,10 +1336,9 @@ int kmb_dsi_init(struct drm_device *dev) struct drm_connector *connector; struct kmb_dsi_host *host; struct kmb_drm_private *dev_p = dev->dev_private; - struct device_node *encoder_node; - struct drm_bridge *bridge; int ret = 0;

+ DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) { DRM_ERROR("failed to allocate kmb_dsi\n"); @@ -1310,52 +1352,44 @@ int kmb_dsi_init(struct drm_device *dev) return -ENOMEM; }

+ DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi->attached_connector = kmb_connector;

- connector = &kmb_connector->base; - encoder = &kmb_dsi->base; - encoder->possible_crtcs = 1; - encoder->possible_clones = 0; - drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, - "MIPI-DSI"); - + DRM_INFO("%s : %d\n", __func__, __LINE__); host = kmb_dsi_host_init(dev, kmb_dsi); + DRM_INFO("%s : %d\n", __func__, __LINE__); if (!host) { - drm_encoder_cleanup(encoder); + DRM_ERROR("Faile to allocate host\n"); +// drm_encoder_cleanup(encoder); kfree(kmb_dsi); kfree(kmb_connector); + return -ENOMEM; }

+ DRM_INFO("%s : %d\n", __func__, __LINE__); + connector = &kmb_connector->base; + DRM_INFO("%s : %d\n", __func__, __LINE__); + encoder = &kmb_dsi->base; + encoder->possible_crtcs = 1; + encoder->possible_clones = 0; + DRM_INFO("%s : %d\n", __func__, __LINE__); + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, + "MIPI-DSI"); + DRM_INFO("%s : %d\n", __func__, __LINE__); + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, - DRM_MODE_CONNECTOR_DSI); + DRM_MODE_CONNECTOR_DSI); + DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs);

+ DRM_INFO("%s : %d\n", __func__, __LINE__); // connector->encoder = encoder; - DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, __LINE__, - connector->name, encoder->name); - DRM_INFO("%s : %d connector->encoder = 0x%p\n", __func__, __LINE__, - connector->encoder); + DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, + __LINE__, connector->name, encoder->name);

ret = drm_connector_attach_encoder(connector, encoder); - DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); - - /* find ADV7535 node and initialize it */ - DRM_DEBUG("trying to get bridge info %pOF\n", dev->dev->of_node); - encoder_node = of_parse_phandle(dev->dev->of_node, "encoder-slave", 0); - DRM_DEBUG("encoder node = %pOF\n", encoder_node); - if (!encoder_node) { - DRM_ERROR("failed to get bridge info from DT\n"); - ret = -EINVAL; - } - /* Locate drm bridge from the hdmi encoder DT node */ - bridge = of_drm_find_bridge(encoder_node); - of_node_put(encoder_node); - if (!bridge) { - DRM_INFO("wait for external bridge driver DT\n"); - return -EPROBE_DEFER; - } - /* Link drm_bridge to encoder */ + DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); @@ -1363,14 +1397,18 @@ int kmb_dsi_init(struct drm_device *dev) return ret; }

+ DRM_INFO("%s : %d\n", __func__, __LINE__); /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__);

/*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__);

/* irq initialization */ mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__);

return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 5fc1547..e9bcc7e 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -22,7 +22,7 @@ struct kmb_dsi { };

struct kmb_dsi_host { - struct mipi_dsi_host base; + struct mipi_dsi_host *base; struct kmb_dsi *kmb_dsi; struct mipi_dsi_device *device; }; @@ -309,8 +309,8 @@ union mipi_irq_cfg { } irq_cfg; };

-//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); -int kmb_dsi_init(struct drm_device *dev); +struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev); +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p);

From: Edmund Dea edmund.j.dea@intel.com

revert dsi_host to static and instead add dsi_host_unregister.

Signed-off-by: Edmund Dea edmund.j.dea@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 6 +++--- drivers/gpu/drm/kmb/kmb_drv.h | 1 - drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++++++-- drivers/gpu/drm/kmb/kmb_dsi.h | 1 + 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 25daba7..1368770 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -379,7 +379,7 @@ static void kmb_drm_unload(struct device *dev) dev_set_drvdata(dev, NULL);

/* Unregister DSI host */ - mipi_dsi_host_unregister(dsi_host); + dsi_host_unregister(); }

static int kmb_probe(struct platform_device *pdev) @@ -420,7 +420,7 @@ static int kmb_probe(struct platform_device *pdev) dev_set_drvdata(dev, drm);

kmb_setup_mode_config(drm); - dev_set_drvdata(dev, drm); + dev_set_drvdata(dev, drm);

/* Load driver */ ret = kmb_load(drm, 0); @@ -461,7 +461,7 @@ static int kmb_probe(struct platform_device *pdev) drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_put(drm); - mipi_dsi_host_unregister(dsi_host); + dsi_host_unregister();

return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 54780ec..1150505 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -11,7 +11,6 @@ #define KMB_MAX_WIDTH 16384 /*max width in pixels */ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */

-extern struct mipi_dsi_host *dsi_host; struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 70bb231..4ec1753 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -59,7 +59,7 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250

-struct mipi_dsi_host *dsi_host; +static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device;

/* @@ -337,8 +337,13 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) return bridge; }

+void dsi_host_unregister(void) +{ + mipi_dsi_host_unregister(dsi_host); +} + u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { struct mipi_data_type_params data_type_parameters;

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index e9bcc7e..811f3b8 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -313,6 +313,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev); int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); +void dsi_host_unregister(void);

#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base)

Enable clocks for LCD, mipi common and mipi tx0 Renamed MSS_CAM_CLK_CTRL and also fixed bug in the call to set this register.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 8 ++++---- drivers/gpu/drm/kmb/kmb_drv.h | 14 ++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.c | 6 ++++-- drivers/gpu/drm/kmb/kmb_regs.h | 7 ++++++- 4 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 9dc5f91..90db07c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -241,6 +241,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk); }

+ /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ + kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON | + MIPI_TX0); #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -292,10 +295,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)

/* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); - if (ret == -EPROBE_DEFER) { - DRM_INFO("%s: wait for external bridge driver DT", __func__); - return -EPROBE_DEFER; - } else if (ret) { + if (ret) { DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 8c5ccf7..71dc883 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -88,6 +88,20 @@ static inline void kmb_write_msscam(struct kmb_drm_private *dev_p, writel(value, (dev_p->msscam_mmio + reg)); }

+static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p, + unsigned int reg) +{ + return readl(dev_p->msscam_mmio + reg); +} + +static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_msscam(dev_p, reg); + + kmb_write_msscam(dev_p, reg, (reg_val | mask)); +} + static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) { return readl(dev_p->lcd_mmio + reg); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 4ec1753..01fa378 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -794,9 +794,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, active_vchannels++;

/*connect lcd to mipi */ - kmb_write_msscam(dev_p, MSS_CAM_BASE_ADDR + - MIPI_TX_MSS_LCD_MIPI_CFG, 1); + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);

+ /*stop iterating as only one virtual channel shall be used for + * LCD connection + */ break; }

diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index e98e144..a3f1a3a 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -677,6 +677,11 @@ & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c)

-#define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) +#define MSS_LCD_MIPI_CFG (0x04) +#define MSS_CAM_CLK_CTRL (0x10) +#define LCD (1<<1) +#define MIPI_COMMON (1<<2) +#define MIPI_TX0 (1<<9) + #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */

From: Edmund Dea edmund.j.dea@intel.com

Added test pattern generator function. Enable this at compile time to test if mipi is working. mipi->hdmi section

Signed-off-by: Edmund Dea edmund.j.dea@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 7 +++++++ drivers/gpu/drm/kmb/kmb_regs.h | 11 +++++++++++ 3 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 01fa378..960ecfa 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -744,6 +744,32 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); }

+#ifdef MIPI_TX_TEST_PATTERN_GENERATION +static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, + int tp_sel, u32 stripe_width, u32 color0, u32 color1) +{ + u32 ctrl_no = MIPI_CTRL6; + + /* Select test pattern mode on the virtual channel */ + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_SEL_VCm(vc, tp_sel)); + + if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || + tp_sel == MIPI_TX_HS_TP_H_STRIPES) { + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_STRIPE_WIDTH(stripe_width)); + } + + /* Configure test pattern colors */ + kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR0, color0); + kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR1, color1); + + /* Enable test pattern generation on the virtual channel */ + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_EN_VCm(vc)); +} +#endif + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -807,6 +833,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, /*Multi-Channel FIFO Configuration*/ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id);

+#ifdef MIPI_TX_TEST_PATTERN_GENERATION + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0, 0, + 0xffffffff, 0); +#endif + /*Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); return ret; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 811f3b8..3de68de 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -180,6 +180,13 @@ enum mipi_dsi_data_type { DSI_LP_DT_RESERVED_3F = 0x3f };

+enum mipi_tx_hs_tp_sel { + MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0, + MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1, + MIPI_TX_HS_TP_V_STRIPES, + MIPI_TX_HS_TP_H_STRIPES, +}; + enum dphy_mode { MIPI_DPHY_SLAVE = 0, MIPI_DPHY_MASTER diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index a3f1a3a..207a161 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -625,6 +625,17 @@ MIPI_TX_HS_IRQ_CLEAR \ + HS_OFFSET(M), val)

+/* MIPI Test Pattern Generation */ +#define MIPI_TX_HS_TEST_PAT_CTRL (0x230) +#define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ + (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) +#define TP_EN_VCm(M) ((M) * 0x04) +#define TP_SEL_VCm(M, N) \ + (N << (((M) * 0x04) + 1)) +#define TP_STRIPE_WIDTH(M) ((M) << 16) +#define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) +#define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) + /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104)

Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI

- Fix test_mode_send when sending normal mode test codes - Change dphy_wait_fsm to check for IDLE status rather than LOCK status for 2-lane MIPI

v2: upclassed dev_private

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Signed-off-by: Edmund Dea edmund.j.dea@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 23 +- drivers/gpu/drm/kmb/kmb_drv.c | 90 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 23 +- drivers/gpu/drm/kmb/kmb_dsi.c | 904 +++++++++++++++++++++++++++++----------- drivers/gpu/drm/kmb/kmb_dsi.h | 2 +- drivers/gpu/drm/kmb/kmb_plane.c | 57 ++- drivers/gpu/drm/kmb/kmb_regs.h | 34 +- 7 files changed, 838 insertions(+), 295 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index eca0f3a..21b2d7f 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -20,6 +20,7 @@ #include "kmb_drv.h" #include "kmb_plane.h" #include "kmb_regs.h" +#include "kmb_dsi.h"

static void kmb_crtc_cleanup(struct drm_crtc *crtc) { @@ -74,24 +75,34 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = {

static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) { - struct drm_display_mode *m = &crtc->state->adjusted_mode; struct drm_device *dev = crtc->dev; +#ifdef LCD_TEST + struct drm_display_mode *m = &crtc->state->adjusted_mode; struct videomode vm; int vsync_start_offset; int vsync_end_offset; unsigned int ctrl = 0; struct kmb_drm_private *dev_p = to_kmb(dev); - +#endif + /* initialize mipi */ + kmb_dsi_hw_init(dev); +#ifdef LCD_TEST vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; - vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; + //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; + vm.hfront_porch = 0; vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;

vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;

+ DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d\n", + __func__, __LINE__, m->crtc_vdisplay, + vm.vback_porch, vm.vfront_porch, + vm.vsync_len, m->crtc_hdisplay, + vm.hback_porch, vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev_p, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); kmb_write_lcd(dev_p, LCD_V_BACKPORCH, vm.vback_porch - 1); @@ -126,7 +137,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_CONTROL, ctrl);

kmb_write_lcd(dev_p, LCD_TIMING_GEN_TRIG, ENABLE); - +#endif /* TBD */ /* set clocks here */ } @@ -138,7 +149,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,

clk_prepare_enable(lcd->clk); kmb_crtc_mode_set_nofb(crtc); - drm_crtc_vblank_on(crtc); +// drm_crtc_vblank_on(crtc); }

static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -149,7 +160,7 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, /* always disable planes on the CRTC that is being turned off */ drm_atomic_helper_disable_planes_on_crtc(old_state, false);

- drm_crtc_vblank_off(crtc); +// drm_crtc_vblank_off(crtc); clk_disable_unprepare(lcd->clk); }

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 64db9a1..2a93b13 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -13,6 +13,7 @@ #include <linux/pm_runtime.h> #include <linux/spinlock.h> #include <drm/drm.h> +#include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_fb_cma_helper.h> @@ -37,27 +38,27 @@ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; static struct clk *clk_msscam; +static struct clk *clk_pll0out0; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg;

struct drm_bridge *adv_bridge;

-static int kmb_display_clk_enable(void) +int kmb_display_clk_enable(void) { int ret = 0; - +#ifdef LCD_TEST ret = clk_prepare_enable(clk_lcd); if (ret) { DRM_ERROR("Failed to enable LCD clock: %d\n", ret); return ret; } - +#endif ret = clk_prepare_enable(clk_mipi); if (ret) { DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); return ret; } - /* ret = clk_prepare_enable(clk_msscam); if (ret) { DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); @@ -158,19 +159,47 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } +/*testing*/ + if (!request_mem_region(CPR_BASE_ADDR, 100, "cpr")) { + DRM_ERROR("failed to reserve %s registers\n", "cpr"); + return -ENOMEM; + } + dev_p->cpr_mmio = ioremap_cache(CPR_BASE_ADDR, 0x100); + if (!dev_p->cpr_mmio) { + DRM_ERROR("failed to ioremap %s registers\n", "CPR"); + release_mem_region(CPR_BASE_ADDR, 100); + return -ENOMEM; + }

+ if (IS_ERR(dev_p->msscam_mmio)) { + DRM_ERROR("failed to map MSSCAM registers\n"); + iounmap(dev_p->lcd_mmio); + iounmap(dev_p->mipi_mmio); + return -ENOMEM; + } + + + +#define KMB_CLOCKS +#ifdef KMB_CLOCKS /* Enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (IS_ERR(clk_lcd)) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } - clk_mipi = clk_get(&pdev->dev, "clk_mipi"); if (IS_ERR(clk_mipi)) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } + clk_pll0out0 = clk_get(&pdev->dev, "clk_pll0_out0"); + if (IS_ERR(clk_pll0out0)) + DRM_ERROR("clk_get() failed clk_pll0_out0\n"); + + if (clk_pll0out0) + DRM_INFO("Get clk_pll0out0 = %ld\n", + clk_get_rate(clk_pll0out0));

clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { @@ -184,8 +213,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

- ret = kmb_display_clk_enable(); - +#ifdef LCD_TEST /* Set LCD clock to 200 Mhz*/ DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK); @@ -196,10 +224,11 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", KMB_LCD_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); - +#endif /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); + DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi to %d\n", KMB_MIPI_DEFAULT_CLK); @@ -210,10 +239,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));

clk = clk_get_rate(clk_mipi_ecfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { /* Set MIPI_ECFG clock to 24 Mhz*/ DRM_INFO("Get clk_mipi_ecfg before set = %ld\n", clk); - ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CLK); + ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); clk = clk_get_rate(clk_mipi_ecfg); if (clk != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi_ecfg to %d\n", @@ -222,27 +251,29 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) } DRM_INFO("Setting MIPI_ECFG clock tp %d Mhz ret = %d\n", KMB_MIPI_DEFAULT_CLK/1000000, ret); - DRM_INFO("Get clk_mipi_ecfg after set = %ld\n", clk); }

clk = clk_get_rate(clk_mipi_cfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { /* Set MIPI_CFG clock to 24 Mhz*/ DRM_INFO("Get clk_mipi_cfg before set = %ld\n", clk); ret = clk_set_rate(clk_mipi_cfg, 24000000); clk = clk_get_rate(clk_mipi_cfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_cfg to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } DRM_INFO("Setting MIPI_CFG clock tp 24Mhz ret = %d\n", ret); DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk); }

+ ret = kmb_display_clk_enable(); + /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ - kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0xfff); - kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xfff); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); +#endif //KMB_CLOCKS #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -292,6 +323,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

+ /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); if (ret) { @@ -320,9 +352,17 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return ret; }

+int kmb_atomic_helper_check(struct drm_device *dev, + struct drm_atomic_state *state) +{ + if (!state) + return 0; + return drm_atomic_helper_check(dev, state); +} + static const struct drm_mode_config_funcs kmb_mode_config_funcs = { .fb_create = drm_gem_fb_create, - .atomic_check = drm_atomic_helper_check, + .atomic_check = kmb_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, };

@@ -484,13 +524,14 @@ static int kmb_probe(struct platform_device *pdev) * afterwards and the bridge can be successfully attached. */ adv_bridge = kmb_dsi_host_bridge_init(dev); +#ifndef FCCTEST if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; else if (IS_ERR(adv_bridge)) { DRM_ERROR("probe failed to initialize DSI host bridge\n"); return PTR_ERR(adv_bridge); } - +#endif /* Create DRM device */ lcd = kzalloc(sizeof(*lcd), GFP_KERNEL); if (!lcd) @@ -520,13 +561,6 @@ static int kmb_probe(struct platform_device *pdev)

/* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); - - ret = drm_vblank_init(drm, drm->mode_config.num_crtc); - if (ret < 0) { - DRM_ERROR("failed to initialize vblank\n"); - goto err_vblank; - } - drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm);

@@ -536,13 +570,13 @@ static int kmb_probe(struct platform_device *pdev) if (ret) goto err_register;

- drm_fbdev_generic_setup(drm, 32); - +#ifndef FCCTEST +// drm_fbdev_generic_setup(drm, 32); +#endif return 0;

err_register: drm_kms_helper_poll_fini(drm); -err_vblank: pm_runtime_disable(drm->dev); err_free: drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index f3f2c34..0bdac1a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -8,16 +8,19 @@

#include "kmb_regs.h"

+/*#define FCCTEST*/ #define KMB_MAX_WIDTH 1920 /*max width in pixels */ #define KMB_MAX_HEIGHT 1080 /*max height in pixels */ -#define KMB_LCD_DEFAULT_CLK 24000000 +#define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 +#define KMB_MIPI_DEFAULT_CFG_CLK 24000000

struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; void __iomem *mipi_mmio; void __iomem *msscam_mmio; + void __iomem *cpr_mmio; unsigned char n_layers; struct clk *clk; struct drm_crtc crtc; @@ -68,12 +71,23 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, reg_val |= (value << offset); writel(reg_val, lcd->mmio + reg); } +static inline void kmb_write(unsigned int reg, u32 value) +{ + writel(value, reg); +} + +static inline u32 kmb_read(unsigned int reg) +{ + return readl(reg); +} #endif

static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 value) { +#ifdef LCD_TEST writel(value, (dev_p->lcd_mmio + reg)); +#endif }

static inline void kmb_write_mipi(struct kmb_drm_private *dev_p, @@ -104,23 +118,30 @@ static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p,

static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) { +#ifdef LCD_TEST return readl(dev_p->lcd_mmio + reg); +#endif + return 0; }

static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { +#ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg);

kmb_write_lcd(dev_p, reg, (reg_val | mask)); +#endif }

static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { +#ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg);

kmb_write_lcd(dev_p, reg, (reg_val & (~mask))); +#endif }

static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 7b42a2fd..9da9d9f 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -3,6 +3,9 @@ * Copyright © 2019-2020 Intel Corporation */

+#include <linux/buffer_head.h> +#include <linux/delay.h> +#include <linux/fs.h> #include <linux/gpio/consumer.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -19,18 +22,25 @@ #include "kmb_dsi.h" #include "kmb_regs.h"

-#define IMG_WIDTH_PX 1920 -#define IMG_HEIGHT_LINES 1080 +static int hw_initialized; +#define IMAGE_PATH "/home/root/1280x720.pnm" +#define MIPI_TX_TEST_PATTERN_GENERATION + +#define IMG_HEIGHT_LINES 720 +#define IMG_WIDTH_PX 1280 #define LCD_BYTESPP 1

/*MIPI TX CFG*/ -#define MIPI_TX_ACTIVE_LANES 4 -#define MIPI_TX_LANE_DATA_RATE_MBPS 888 +#define MIPI_TX_ACTIVE_LANES 2 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 +#define MIPI_TX_LANE_DATA_RATE_MBPS 891 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 #define MIPI_TX_CFG_CLK_KHZ 24000

/*DPHY Tx test codes*/ #define TEST_CODE_FSM_CONTROL 0x03 +#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C #define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E #define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F #define TEST_CODE_PLL_VCO_CTRL 0x12 @@ -44,6 +54,7 @@ #define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 #define PLL_N_OVR_EN (1 << 4) #define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_VOD_LEVEL 0x24 #define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C #define TEST_CODE_PLL_LOCK_DETECTOR 0x1D #define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 @@ -59,6 +70,7 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250

+#define TIMEOUT 600 static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device;

@@ -71,8 +83,9 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, - .data_mode = MIPI_DATA_MODE1, - .dma_packed = 0 + //.data_mode = MIPI_DATA_MODE1, + .data_mode = MIPI_DATA_MODE0, + .dma_packed = 1 };

struct mipi_tx_frame_cfg mipitx_frame0_cfg = { @@ -81,11 +94,11 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[2] = NULL, .sections[3] = NULL, .vsync_width = 5, - .v_backporch = 36, - .v_frontporch = 4, - .hsync_width = 44, - .h_backporch = 148, - .h_frontporch = 88 + .v_backporch = 20, + .v_frontporch = 5, + .hsync_width = 40, + .h_backporch = 220, + .h_frontporch = 110, };

struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { @@ -108,7 +121,8 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS, .ref_clk_khz = MIPI_TX_REF_CLK_KHZ, .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ, - .data_if = MIPI_IF_PARALLEL, +// .data_if = MIPI_IF_PARALLEL, + .data_if = MIPI_IF_DMA, .tx_ctrl_cfg = { .frames[0] = &mipitx_frame0_cfg, .frames[1] = NULL, @@ -118,16 +132,20 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .line_sync_pkt_en = 0, .line_counter_active = 0, .frame_counter_active = 0, + .tx_always_use_hact = 1, + .tx_hact_wait_stop = 1, }

};

-typedef struct{ +u8 *iBuf; + +struct mipi_hs_freq_range_cfg { uint16_t default_bit_rate_mbps; uint8_t hsfreqrange_code; -} mipi_hs_freq_range_cfg; +};

-static mipi_hs_freq_range_cfg +static struct mipi_hs_freq_range_cfg mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00}, {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10}, @@ -210,8 +228,8 @@ static int kmb_dsi_get_modes(struct drm_connector *connector) int num_modes = 0;

num_modes = drm_add_modes_noedid(connector, - connector->dev->mode_config.max_width, - connector->dev->mode_config.max_height); + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); return num_modes; }

@@ -244,6 +262,7 @@ drm_connector_helper_funcs kmb_dsi_connector_helper_funcs = { static const struct drm_connector_funcs kmb_dsi_connector_funcs = { .destroy = kmb_dsi_connector_destroy, .fill_modes = drm_helper_probe_single_connector_modes, + .reset = drm_atomic_helper_connector_reset, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, }; @@ -273,10 +292,11 @@ static const struct mipi_dsi_host_ops kmb_dsi_host_ops = { };

static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, - struct kmb_dsi *kmb_dsi) + struct kmb_dsi *kmb_dsi) { struct kmb_dsi_host *host;

+ DRM_INFO("%s : %d\n", __func__, __LINE__); host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL; @@ -316,7 +336,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) dsi_host->dev = dev; mipi_dsi_host_register(dsi_host); } - +#ifndef FCCTEST /* find ADV7535 node and initialize it */ DRM_INFO("trying to get bridge info %pOF\n", dev->of_node); encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); @@ -333,7 +353,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) DRM_INFO("wait for external bridge driver DT\n"); return ERR_PTR(-EPROBE_DEFER); } - +#endif return bridge; }

@@ -343,7 +363,7 @@ void dsi_host_unregister(void) }

u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { struct mipi_data_type_params data_type_parameters;

@@ -461,17 +481,18 @@ static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) }

static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_id, - u8 section, u32 height_lines, - u32 unpacked_bytes, struct mipi_tx_frame_sect_phcfg *ph_cfg) + u8 frame_id, + u8 section, u32 height_lines, + u32 unpacked_bytes, + struct mipi_tx_frame_sect_phcfg *ph_cfg) { u32 cfg = 0; u32 ctrl_no = MIPI_CTRL6; u32 reg_adr;

- /*frame section packet header*/ - /*word count*/ - cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0]*/ + /*frame section packet header */ + /*word count */ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ /*data type */ cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ @@ -483,9 +504,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg); + __func__, __LINE__, ctrl_no, frame_id, section, cfg); kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + section)), cfg); /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections *there are 2 registers for unpacked bytes - @@ -494,9 +515,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section/2)*4; - kmb_write_bits_mipi(dev_p, reg_adr, (section % 2)*16, 16, - unpacked_bytes); + + (section / 2) * 4; + kmb_write_bits_mipi(dev_p, reg_adr, (section % 2) * 16, 16, + unpacked_bytes);

/* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); @@ -505,9 +526,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, }

static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, - u8 section, - struct mipi_tx_frame_section_cfg *frame_scfg, - u32 *bits_per_pclk, u32 *wc) + u8 section, + struct mipi_tx_frame_section_cfg *frame_scfg, + u32 *bits_per_pclk, u32 *wc) { u32 ret = 0; u32 unpacked_bytes; @@ -515,8 +536,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, struct mipi_tx_frame_sect_phcfg ph_cfg;

ret = mipi_get_datatype_params(frame_scfg->data_type, - frame_scfg->data_mode, - &data_type_parameters); + frame_scfg->data_mode, + &data_type_parameters); if (ret) return ret; /* @@ -524,7 +545,7 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, * (in pixels) set for each data type */ if (frame_scfg->width_pixels % - data_type_parameters.size_constraint_pixels != 0) + data_type_parameters.size_constraint_pixels != 0) return -EINVAL;

*wc = compute_wc(frame_scfg->width_pixels, @@ -540,8 +561,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, ph_cfg.vchannel = frame_id;

mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, - frame_scfg->height_lines, - unpacked_bytes, &ph_cfg); + frame_scfg->height_lines, + unpacked_bytes, &ph_cfg);

/*caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; @@ -549,17 +570,18 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, }

static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) + u8 frame_gen, + struct mipi_tx_frame_timing_cfg *fg_cfg) { u32 sysclk; /*float ppl_llp_ratio; */ u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;

- /*Get system clock for blanking period cnfigurations*/ + /*Get system clock for blanking period cnfigurations */ /*TODO need to get system clock from clock driver */ /* Assume 700 Mhz system clock for now */ - sysclk = 700; + sysclk = 500;

/*ppl-pixel packing layer, llp-low level protocol * frame genartor timing parameters are clocked on the system clock @@ -575,43 +597,42 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active);

- DRM_INFO("%s : %d\n", __func__, __LINE__); /*vsync width */ /* *there are 2 registers for vsync width -VSA in lines for channels 0-3 *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2)*16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); + offset = (frame_gen % 2) * 16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->vsync_width);

- /*v backporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); + /*v backporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_backporch);

- /*v frontporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); + /*v frontporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_frontporch);

- /*v active - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); + /*v active - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_active);

/*hsyc width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + (fg_cfg->hsync_width * ppl_llp_ratio) / 1000);

/*h backporch */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + (fg_cfg->h_backporch * ppl_llp_ratio) / 1000);

/*h frontporch */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000);

/*h active */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); @@ -629,16 +650,15 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8));

- DRM_INFO("%s : %d\n", __func__, __LINE__); /* llp h frontporch */ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); + fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); }

static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, - u8 active_lanes, u32 bpp, u32 wc, - u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) + u8 active_lanes, u32 bpp, u32 wc, + u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) { u32 i, fg_num_lines = 0; struct mipi_tx_frame_timing_cfg fg_t_cfg; @@ -668,20 +688,21 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, }

static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, - u8 active_lanes, u8 vchannel_id) + u8 active_lanes, u8 vchannel_id) { u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6;

- /*clear all mc fifo channel sizes and thresholds*/ + /*clear all mc fifo channel sizes and thresholds */ kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0);

- fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? - MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; + fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ? + MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : + MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; /*MC fifo size for virtual channels 0-3 */ /* *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 @@ -690,21 +711,21 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, SET_MC_FIFO_CHAN_ALLOC(dev_p, ctrl_no, vchannel_id, fifo_size);

/*set threshold to half the fifo size, actual size=size*16 */ - fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; + fifo_rthreshold = ((fifo_size) * 8) & BIT_MASK_16; SET_MC_FIFO_RTHRESHOLD(dev_p, ctrl_no, vchannel_id, fifo_rthreshold);

/*enable the MC FIFO channel corresponding to the Virtual Channel */ kmb_set_bit_mipi(dev_p, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), - vchannel_id); + vchannel_id); }

static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6;

- /*MIPI_TX_HS_SYNC_CFG*/ + /*MIPI_TX_HS_SYNC_CFG */ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -734,7 +755,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= HACT_WAIT_STOP(fg_en);

/* MIPI_TX_HS_CTRL */ - ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) @@ -750,32 +771,30 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id,

#ifdef MIPI_TX_TEST_PATTERN_GENERATION static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, - int tp_sel, u32 stripe_width, u32 color0, u32 color1) + int tp_sel, u32 stripe_width, u32 color0, + u32 color1, u32 ctrl_no) { - u32 ctrl_no = MIPI_CTRL6; - + int val = 0; /* Select test pattern mode on the virtual channel */ - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_SEL_VCm(vc, tp_sel)); + val = TP_SEL_VCm(vc, tp_sel);

if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || - tp_sel == MIPI_TX_HS_TP_H_STRIPES) { - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_STRIPE_WIDTH(stripe_width)); + tp_sel == MIPI_TX_HS_TP_H_STRIPES) { + val |= TP_STRIPE_WIDTH(stripe_width); }

/* Configure test pattern colors */ - kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR0, color0); - kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR1, color1); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR0(ctrl_no), color0); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR1(ctrl_no), color1);

/* Enable test pattern generation on the virtual channel */ - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_EN_VCm(vc)); + val |= TP_EN_VCm(vc); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), val); } #endif

static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; u8 active_vchannels = 0; @@ -802,12 +821,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + == NULL) continue;

ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], - &bits_per_pclk, &word_count); + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + &bits_per_pclk, + &word_count); if (ret) return ret;

@@ -815,14 +835,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,

/* set frame specific parameters */ mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, + word_count, ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]);

active_vchannels++;

/*connect lcd to mipi */ - kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);

/*stop iterating as only one virtual channel shall be used for * LCD connection @@ -832,23 +851,152 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,

if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration*/ + /*Multi-Channel FIFO Configuration */ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id);

-#ifdef MIPI_TX_TEST_PATTERN_GENERATION - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0, 0, - 0xffffffff, 0); -#endif - /*Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); return ret; }

+int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, + int test_code) +{ + u32 reg_wr_data; + u32 reg_rd_data; + int data; + + reg_wr_data = dphy_sel; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = 0; + reg_wr_data = 0; + reg_rd_data = 0; + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = (dphy_sel | dphy_sel << 12); + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel << 12; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = test_code >> 8 & 0xf; + reg_wr_data = 0; + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = test_code & 0xff; + reg_wr_data = 0; + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = (dphy_sel | dphy_sel << 12); + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel << 12; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + if ((dphy_sel >> 0 & 0xf) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT0_3); + if ((dphy_sel >> 4 & 0xf) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT4_7); + if ((dphy_sel >> 8 & 0x3) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT8_9); + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) + data = reg_rd_data >> 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) + data = reg_rd_data >> 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) + data = reg_rd_data >> 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) + data = reg_rd_data >> 24; + + return data; + +} + static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 test_code, u32 test_data) + u32 test_code, u32 test_data) { - /*send the test code first */ +#ifdef DEBUG + if (test_code != TEST_CODE_FSM_CONTROL) + DRM_INFO("test_code = %02x, test_data = %08x\n", test_code, + test_data); +#endif + + /* send the test code first */ /* Steps for code: * - set testclk HIGH * - set testdin with test code @@ -856,55 +1004,77 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, * - set testclk LOW * - set testen LOW */ + + /* Set testclk high */ SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set testdin */ SET_TEST_DIN0_3(dev_p, dphy_no, test_code); + + /* Set testen high */ SET_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + + /* Set testclk low */ CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no);

- /*send the test data next */ + /* Send the test data next */ /* Steps for data: * - set testen LOW * - set testclk LOW * - set testdin with data * - set testclk HIGH */ - CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); - CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); - SET_TEST_DIN0_3(dev_p, dphy_no, test_data); - SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + if (test_code) { + /* Set testen low */ + CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + + /* Set testclk low */ + CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set data in testdin */ + kmb_write_mipi(dev_p, + DPHY_TEST_DIN0_3 + ((dphy_no / 0x4) * 0x4), + test_data << ((dphy_no % 4) * 8)); + + /* Set testclk high */ + SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + } }

static inline void set_test_mode_src_osc_freq_target_low_bits(struct kmb_drm_private - *dev_p, u32 dphy_no, u32 freq) + *dev_p, + u32 dphy_no, + u32 freq) { /*typical rise/fall time=166, * refer Table 1207 databook,sr_osc_freq_target[7:0 */ test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); + TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); }

static inline void - set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, - u32 dphy_no) +set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, u32 dphy_no) { /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range*/ + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - (0x03 | (1 << 6))); + (0x03 | (1 << 6))); }

static inline void - set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, - u32 dphy_no, u32 freq) +set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, + u32 dphy_no, u32 freq) { u32 data; /*typical rise/fall time=166, refer Table 1207 databook, * sr_osc_freq_target[11:7 */ - data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ + data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); }

@@ -941,20 +1111,20 @@ static void mipi_tx_get_vco_params(struct vco_params *vco) }

static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 ref_clk_mhz, u32 target_freq_mhz) + u32 ref_clk_mhz, u32 target_freq_mhz) { /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) * n: - valid range [0 15] * N: - N = n + 1 - * -valid range: [1 16] - * -conditions: - (pll_ref_clk / N) >= 2 MHz - * -(pll_ref_clk / N) <= 8 MHz + * -valid range: [1 16] + * -conditions: - (pll_ref_clk / N) >= 2 MHz + * -(pll_ref_clk / N) <= 8 MHz * m: valid range [62 623] * M: - M = m + 2 - * -valid range [64 625] - * -Fvco = (M/N) * pll_ref_clk + * -valid range [64 625] + * -Fvco = (M/N) * pll_ref_clk */ struct vco_params vco_p = { .range = 0, @@ -972,7 +1142,7 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, * multiply by 1000 for precision - * no floating point, add n for rounding */ - div = ((ref_clk_mhz * 1000) + n)/(n+1); + div = ((ref_clk_mhz * 1000) + n) / (n + 1); /*found a valid n parameter */ if ((div < 2000 || div > 8000)) continue; @@ -983,7 +1153,7 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, */ freq = div * (m + 2); freq /= 1000; - /* trim the potential pll freq to max supported*/ + /* trim the potential pll freq to max supported */ if (freq > PLL_FVCO_MAX) continue;

@@ -1004,37 +1174,39 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range - | (1 << 6))); + | (1 << 6)));

/*Program m, n pll parameters */

+ DRM_INFO("%s : %d m = %d n = %d\n", __func__, __LINE__, best_m, best_n); + /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, - (best_n & 0x0f)); + (best_n & 0x0f));

/* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, - (best_m & 0x1f)); + (best_m & 0x1f));

/*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, - ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); + ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH);

- /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en*/ + /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, - (PLL_N_OVR_EN | PLL_M_OVR_EN)); + (PLL_N_OVR_EN | PLL_M_OVR_EN));

/*Program Charge-Pump parameters */

/*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ t_freq = target_freq_mhz * vco_p.divider; test_mode_send(dev_p, dphy_no, - TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, - ((t_freq > 1150) ? 0x0C : 0x0B)); + TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, + ((t_freq > 1150) ? 0x0C : 0x0B));

/*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, - 0x00); + 0x00);

/*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); @@ -1042,13 +1214,13 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10);

- /*PLL Lock Configuration */ - - /*pll_th1 -Lock Detector Phase error threshold, - * document gives fixed value + /*pll_th1 -Lock Detector Phase error threshold, document gives fixed + * value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02);

+ /*PLL Lock Configuration */ + /*pll_th2 - Lock Filter length, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60);

@@ -1062,24 +1234,37 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, }

static void dphy_init_sequence(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *cfg, u32 dphy_no, enum dphy_mode mode) + struct mipi_ctrl_cfg *cfg, u32 dphy_no, + int active_lanes, enum dphy_mode mode) { u32 test_code = 0; u32 test_data = 0, val; - int i; + int i = 0;

+ /* deassert SHUTDOWNZ signal */ + DRM_INFO("%s : %d MIPI_DPHY_STAT0_4_7 = 0x%x)\n", __func__, __LINE__, + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); /*Set D-PHY in shutdown mode */ /*assert RSTZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - /* assert SHUTDOWNZ signal*/ + /* assert SHUTDOWNZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); + DRM_INFO("%s : %d DPHY_INIT_CTRL0 = 0x%x\n", __func__, __LINE__, val); + /*Init D-PHY_n */ /*Pulse testclear signal to make sure the d-phy configuration starts * from a clean base */ + CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); + ndelay(15); SET_DPHY_TEST_CTRL0(dev_p, dphy_no); - /*TODO may need to add 15ns delay here*/ + /*TODO may need to add 15ns delay here */ + ndelay(15); CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); + val = kmb_read_mipi(dev_p, DPHY_TEST_CTRL0); + DRM_INFO("%s : %d DPHY_TEST_CTRL0 = 0x%x\n", __func__, __LINE__, val); + ndelay(15);

/*Set mastermacro bit - Master or slave mode */ test_code = TEST_CODE_MULTIPLE_PHY_CTRL; @@ -1091,17 +1276,17 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p,

/*send the test code and data */ test_mode_send(dev_p, dphy_no, test_code, test_data); - /*Set the lane data rate */ for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { if (mipi_hs_freq_range[i].default_bit_rate_mbps < cfg->lane_rate_mbps) continue; - /* send the test code and data*/ - /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en*/ - test_mode_send(dev_p, dphy_no, TEST_CODE_HS_FREQ_RANGE_CFG, - (mipi_hs_freq_range[i].hsfreqrange_code - & 0x7f) | (1 << 7)); + /* send the test code and data */ + /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ + test_code = TEST_CODE_HS_FREQ_RANGE_CFG; + test_data = + (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data); break; } /* @@ -1110,78 +1295,136 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, */ if (cfg->lane_rate_mbps > 1500) { /*bypass slew rate calibration algorithm */ - /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, 0x02); + /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = 0x02; + test_mode_send(dev_p, dphy_no, test_code, test_data);

- /* disable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x00); + /* disable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x00; + test_mode_send(dev_p, dphy_no, test_code, test_data); } else if (cfg->lane_rate_mbps > 1000) { /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON * typical rise/fall times: 166 ps */

/*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dev_p, dphy_no); + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = (0x03 | (1 << 6)); + test_mode_send(dev_p, dphy_no, test_code, test_data);

- /* enable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); +// set_test_mode_slew_rate_calib_en(dev_p, dphy_no); + + /* enable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data);

/*set sr_osc_freq_target[6:0] */ - /*typical rise/fall time=166, refer Table 1207 databook*/ - set_test_mode_src_osc_freq_target_low_bits(dev_p, - dphy_no, 0x72f); + /*typical rise/fall time=166, refer Table 1207 databook */ + /*typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[7:0 + */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + test_data = (0x72f & 0x7f); + test_mode_send(dev_p, dphy_no, test_code, test_data); /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, - 0x72f); + /*typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[11:7 + */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + /*flag this as high nibble */ + test_data = ((0x72f >> 6) & 0x1f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data); } else { /*lane_rate_mbps <= 1000 Mbps */ /*BitRate: <= 1 Gbps: * - slew rate control ON * - typical rise/fall times: 225 ps */ + /*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - /* enable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); - - /*typical rise/fall time=255, refer Table 1207 databook*/ - set_test_mode_src_osc_freq_target_low_bits(dev_p, - dphy_no, 0x523); + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = (0x03 | (1 << 6)); + test_mode_send(dev_p, dphy_no, test_code, test_data); + + /* enable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data); + + /*typical rise/fall time=255, refer Table 1207 databook */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + test_data = (0x523 & 0x7f); + test_mode_send(dev_p, dphy_no, test_code, test_data); + /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, - 0x523); - } + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + /*flag this as high nibble */ + test_data = ((0x523 >> 6) & 0x1f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data);

+ } /*Set cfgclkfreqrange */ - val = (((cfg->cfg_clk_khz/1000) - 17) * 4) & 0x3f; + val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; SET_DPHY_FREQ_CTRL0_3(dev_p, dphy_no, val); + val = kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4);

/*Enable config clk for the corresponding d-phy */ kmb_set_bit_mipi(dev_p, DPHY_CFG_CLK_EN, dphy_no); - + val = kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN); /* PLL setup */ if (mode == MIPI_DPHY_MASTER) { /*Set PLL regulator in bypass */ - test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); + test_code = TEST_CODE_PLL_ANALOG_PROG; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data);

/* PLL Parameters Setup */ - mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz/1000, - cfg->lane_rate_mbps/2); + mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz / 1000, + cfg->lane_rate_mbps / 2);

/*Set clksel */ - kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, - 0x01); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, + 2, 0x01); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1);

/*Set pll_shadow_control */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); } +#define MIPI_TX_FORCE_VOD +#ifdef MIPI_TX_FORCE_VOD +#define MIPI_TX_VOD_LVL 450 +#define TEST_CODE_BANDGAP 0x24 + /* Set bandgap/VOD level */ + switch (MIPI_TX_VOD_LVL) { + case 200: + test_data = 0x00; + break; + case 300: + test_data = 0x20; + break; + case 350: + test_data = 0x40; + break; + case 450: + test_data = 0x60; + break; + case 400: + default: + test_data = 0x70; + break; + } + test_mode_send(dev_p, dphy_no, TEST_CODE_BANDGAP, test_data); +#endif

/*Send NORMAL OPERATION test code */ - test_mode_send(dev_p, dphy_no, 0x00, 0x00); + test_code = 0x0; + test_data = 0x0; + test_mode_send(dev_p, dphy_no, test_code, test_data);

/* Configure BASEDIR for data lanes * NOTE: basedir only applies to LANE_0 of each D-PHY. @@ -1190,84 +1433,123 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, * bits[5:0] - BaseDir: 1 = Rx * bits[9:6] - BaseDir: 0 = Tx */ - kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, dphy_no); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL2, 0, 9, 0x03f); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); + ndelay(15);

/* Enable CLOCK LANE - */ /*clock lane should be enabled regardless of the direction set for * the D-PHY (Rx/Tx) */ - kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); + kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2);

/* enable DATA LANES */ kmb_write_bits_mipi(dev_p, DPHY_ENABLE, dphy_no * 2, 2, - ((1 << cfg->active_lanes) - 1)); + ((1 << active_lanes) - 1));

+ val = kmb_read_mipi(dev_p, DPHY_ENABLE); + ndelay(15); /*Take D-PHY out of shutdown mode */ - /* deassert SHUTDOWNZ signal*/ + /* deassert SHUTDOWNZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); + ndelay(15); + /*deassert RSTZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); }

static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, - enum dphy_tx_fsm fsm_state) + enum dphy_tx_fsm fsm_state) { enum dphy_tx_fsm val = DPHY_TX_POWERDWN; int i = 0; + int status = 1;

do { test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); /*TODO-need to add a time out and return failure */ - val = GET_TEST_DOUT0_3(dev_p, dphy_no); + val = GET_TEST_DOUT4_7(dev_p, dphy_no); i++; - if (i > 50000) { - DRM_INFO("%s: timing out\n", __func__); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("%s: timing out fsm_state = %x GET_TEST_DOUT4_7 = %x", + __func__, fsm_state, kmb_read_mipi(dev_p, + DPHY_TEST_DOUT4_7)); break; } } while (val != fsm_state); + DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); + + DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); + DRM_INFO("********** DPHY %d WAIT_FSM %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); }

static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 active_lanes) + u32 active_lanes) { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; - int i = 0; + int i = 0, val; + int status = 1; + + DRM_INFO("%s : %d dphy = %d active_lanes=%d data_lanes=%d\n", + __func__, __LINE__, dphy_no, active_lanes, data_lanes);

do { - stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no); - /*TODO-need to add a time out and return failure */ + val = kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7); + stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no) & data_lanes; i++; - if (i > 50000) { - DRM_INFO("%s: timing out", __func__); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("!WAIT_INIT_DONE: TIMING OUT! (err_stat=%d)n", + kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); break; } + udelay(1); } while (stopstatedata != data_lanes);

+ DRM_INFO("********** DPHY %d INIT - %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); + return 0; }

static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { int i = 0; + int status = 1; + do { ; /*TODO-need to add a time out and return failure */ i++; - if (i > 50000) { - DRM_INFO("wait_pll_lock: timing out\n"); + udelay(1); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("%s: timing out", __func__); + DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); break; } + } while (!GET_PLL_LOCK(dev_p, dphy_no));

+ DRM_INFO("********** PLL Locked for DPHY %d - %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); return 0; }

static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *cfg) + struct mipi_ctrl_cfg *cfg) { u32 dphy_no = MIPI_DPHY6;

+ DRM_INFO("%s : %d active_lanes=%d lane_rate=%d\n", + __func__, __LINE__, cfg->active_lanes, + MIPI_TX_LANE_DATA_RATE_MBPS); /*multiple D-PHYs needed */ if (cfg->active_lanes > MIPI_DPHY_D_LANES) { /* @@ -1286,62 +1568,32 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, *f. poll for PHY1 stopstate */ /*PHY #N+1 ('slave') */ - dphy_init_sequence(dev_p, cfg, dphy_no + 1, MIPI_DPHY_SLAVE);

+ dphy_init_sequence(dev_p, cfg, dphy_no + 1, + (cfg->active_lanes - MIPI_DPHY_D_LANES), + MIPI_DPHY_SLAVE); dphy_wait_fsm(dev_p, dphy_no + 1, DPHY_TX_LOCK);

- /*PHY #N master*/ - dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); + /*PHY #N master */ + dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_D_LANES, + MIPI_DPHY_MASTER); /* wait for DPHY init to complete */ wait_init_done(dev_p, dphy_no, MIPI_DPHY_D_LANES); wait_init_done(dev_p, dphy_no + 1, - cfg->active_lanes - MIPI_DPHY_D_LANES); + cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); - } else { /* Single DPHY */ - dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); + udelay(1000); + dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); + } else { /* Single DPHY */ + dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, + MIPI_DPHY_MASTER); + dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); wait_init_done(dev_p, dphy_no, cfg->active_lanes); wait_pll_lock(dev_p, dphy_no); } - return 0; -} - -static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, - union mipi_irq_cfg *cfg, - struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) -{ - unsigned long irqflags; - uint8_t vc; - - /* clear all interrupts first */ - /*local interrupts */ - SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); - /*global interrupts */ - SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); - - /*enable interrupts */ - spin_lock_irqsave(&dev_p->irq_lock, irqflags); - for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { - if (tx_ctrl_cfg->frames[vc] == NULL) - continue; - /*enable FRAME_DONE interrupt if VC is configured */ - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); - break; /*only one vc for LCD interface */ - } - - /*enable user enabled interrupts */ - if (cfg->irq_cfg.dphy_error) - SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); - if (cfg->irq_cfg.line_compare) - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - MIPI_TX_HS_IRQ_LINE_COMPARE); - if (cfg->irq_cfg.ctrl_error) - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR);

- spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); + return 0; }

void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) @@ -1357,7 +1609,7 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) if (irq_ctrl_stat_0 & MIPI_DPHY_ERR_MASK) { if (irq_ctrl_stat_0 & ((1 << (MIPI_DPHY6 + 1)))) SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, - MIPI_DPHY_ERR_IRQ); + MIPI_DPHY_ERR_IRQ); } else if (irq_ctrl_stat_0 & MIPI_HS_IRQ_MASK) { hs_stat = GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6); hs_enable = GET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6); @@ -1365,9 +1617,9 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) /*look for errors */ if (hs_stat & MIPI_TX_HS_IRQ_ERROR) { CLR_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - (hs_stat & MIPI_TX_HS_IRQ_ERROR) | - MIPI_TX_HS_IRQ_DMA_DONE | - MIPI_TX_HS_IRQ_DMA_IDLE); + (hs_stat & MIPI_TX_HS_IRQ_ERROR) | + MIPI_TX_HS_IRQ_DMA_DONE | + MIPI_TX_HS_IRQ_DMA_IDLE); } /* clear local, then global */ SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, hs_stat); @@ -1376,6 +1628,152 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)

}

+void dma_transfer(struct kmb_drm_private *dev_p, int mipi_number, + u64 dma_start_address, int data_length) +{ + u64 dma_cfg_adr_offset; + u64 dma_start_adr_offset; + u64 dma_length_adr_offset; + u32 reg_wr_data; + int axi_burst_length; + int mipi_fifo_flush; + int dma_pipelined_axi_en; + int dma_en; + int dma_autorestart_mode_0; + int tx_rx; + + DRM_INFO("%s: starting a new DMA transfer for mipi %d ", __func__, + mipi_number); + + if (mipi_number < 6) + tx_rx = 0; + else + tx_rx = 1; + + dma_cfg_adr_offset = + MIPI_TX_HS_DMA_CFG + HS_OFFSET(mipi_number); + dma_start_adr_offset = + MIPI_TX_HS_DMA_START_ADR_CHAN0 + HS_OFFSET(mipi_number); + dma_length_adr_offset = + MIPI_TX_HS_DMA_LEN_CHAN0 + HS_OFFSET(mipi_number); + + reg_wr_data = 0; + reg_wr_data = dma_start_address; + kmb_write_mipi(dev_p, dma_start_adr_offset, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = data_length; + kmb_write_mipi(dev_p, dma_length_adr_offset, reg_wr_data); + + axi_burst_length = 16; + mipi_fifo_flush = 0; + dma_pipelined_axi_en = 1; + dma_en = 1; + dma_autorestart_mode_0 = 0; + + reg_wr_data = 0; + reg_wr_data = + ((axi_burst_length & 0x1ffff) << 0 | (mipi_fifo_flush & 0xf) << 9 | + (dma_pipelined_axi_en & 0x1) << 13 | (dma_en & 0xf) << 16 | + (dma_autorestart_mode_0 & 0x3) << 24); + + kmb_write_mipi(dev_p, dma_cfg_adr_offset, reg_wr_data); +} + +/** + * Reads specified number of bytes from the file. + * + * @param file - file structure. + * @param offset - offset in the file. + * @param addr - address of the buffer. + * @param count - size of the buffer . + * + * @return 0 if success or error code. + */ +int kmb_kernel_read(struct file *file, loff_t offset, + char *addr, unsigned long count) +{ + char __user *buf = (char __user *)addr; + ssize_t ret; + + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + + ret = kernel_read(file, buf, count, &offset); + + return ret; +} + +int kmb_dsi_hw_init(struct drm_device *dev) +{ + struct kmb_drm_private *dev_p = to_kmb(dev); + int i; + + if (hw_initialized) + return 0; + udelay(1000); + kmb_write_mipi(dev_p, DPHY_ENABLE, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL2, 0); + + /* initialize mipi controller */ + mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); + /* irq initialization */ + //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + /*d-phy initialization */ + mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); +#ifdef MIPI_TX_TEST_PATTERN_GENERATION + for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) { + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x05, 0xffffff, 0xff00, i); + } + DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__, + __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); +#else + dma_data_length = image_height * image_width * unpacked_bytes; + file = filp_open(IMAGE_PATH, O_RDWR, 0); + if (IS_ERR(file)) { + DRM_ERROR("filp_open failed\n"); + return -EBADF; + } + + file_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!file_buf) { + DRM_ERROR("file_buf alloc failed\n"); + return -ENOMEM; + } + + i_size = i_size_read(file_inode(file)); + while (offset < i_size) { + + file_buf_len = kmb_kernel_read(file, offset, + file_buf, PAGE_SIZE); + if (file_buf_len < 0) { + rc = file_buf_len; + break; + } + if (file_buf_len == 0) + break; + offset += file_buf_len; + count++; + dma_tx_start_address = file_buf; + dma_transfer(dev_p, MIPI_CTRL6, dma_tx_start_address, + PAGE_SIZE); + + } + DRM_INFO("count = %d\n", count); + kfree(file_buf); + filp_close(file, NULL); + +#endif //MIPI_TX_TEST_PATTERN_GENERATION + + hw_initialized = true; + DRM_INFO("%s : %d mipi hw_initialized = %d\n", __func__, __LINE__, + hw_initialized); + return 0; +} + int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) { struct kmb_dsi *kmb_dsi; @@ -1383,7 +1781,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) struct kmb_connector *kmb_connector; struct drm_connector *connector; struct kmb_dsi_host *host; - struct kmb_drm_private *dev_p = dev->dev_private; int ret = 0;

kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); @@ -1392,6 +1789,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; }

+ DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); @@ -1404,7 +1802,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { DRM_ERROR("Faile to allocate host\n"); -// drm_encoder_cleanup(encoder); +// drm_encoder_cleanup(encoder); kfree(kmb_dsi); kfree(kmb_connector); return -ENOMEM; @@ -1415,34 +1813,34 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) encoder->possible_crtcs = 1; encoder->possible_clones = 0; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, - "MIPI-DSI"); + "MIPI-DSI");

drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, - DRM_MODE_CONNECTOR_DSI); + DRM_MODE_CONNECTOR_DSI); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs);

DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, - __LINE__, connector->name, encoder->name); + __LINE__, connector->name, encoder->name);

+ DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_connector_attach_encoder(connector, encoder);

/* Link drm_bridge to encoder */ +#ifndef FCCTEST ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); drm_encoder_cleanup(encoder); return ret; } - +#endif +#ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); - /* initialize mipi controller */ - mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - - /*d-phy initialization */ - mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); +#endif

- /* irq initialization */ - mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); +#ifdef FCCTEST + kmb_dsi_hw_init(dev); +#endif

return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 3de68de..035ad80 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -43,7 +43,6 @@ struct kmb_connector { #define MIPI_DPHY_DEFAULT_BIT_RATES 63

/*DPHY Tx test codes */ -#define TEST_CODE_MULTIPLE_PHY_CTRL 0x03

enum mipi_ctrl_num { MIPI_CTRL0 = 0, @@ -321,6 +320,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void dsi_host_unregister(void); +int kmb_dsi_hw_init(struct drm_device *dev);

#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 37371e5..1a40ef0 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -113,8 +113,12 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_framebuffer *fb; int ret;

+ fb = state->fb;

+ if (!fb || !state->crtc) + return 0; + ret = check_pixel_format(plane, fb->format->format); if (ret) return ret; @@ -124,6 +128,38 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, return 0; }

+static void kmb_plane_atomic_disable(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct kmb_plane *kmb_plane = to_kmb_plane(plane); + int ctrl = 0; + struct kmb_drm_private *dev_p; + int plane_id; + + dev_p = to_kmb(plane->dev); + plane_id = kmb_plane->id; + + switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_CONTROL, ~ctrl); +} + + unsigned int set_pixel_format(u32 format) { unsigned int val = 0; @@ -237,6 +273,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) return val; }

+#ifdef LCD_TEST static void config_csc(struct kmb_drm_private *dev_p, int plane_id) { /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */ @@ -254,26 +291,36 @@ static void config_csc(struct kmb_drm_private *dev_p, int plane_id) kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN); } +#endif

static void kmb_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *state) { - struct drm_framebuffer *fb = plane->state->fb; +#ifdef LCD_TEST + struct drm_framebuffer *fb; struct kmb_drm_private *dev_p; dma_addr_t addr; unsigned int width; unsigned int height; unsigned int dma_len; - struct kmb_plane *kmb_plane = to_kmb_plane(plane); + struct kmb_plane *kmb_plane; unsigned int dma_cfg; unsigned int ctrl = 0, val = 0, out_format = 0; unsigned int src_w, src_h, crtc_x, crtc_y; - unsigned char plane_id = kmb_plane->id; - int num_planes = fb->format->num_planes; + unsigned char plane_id; + int num_planes; + + if (!plane || !plane->state || !state) + return;

+ fb = plane->state->fb; if (!fb) return;

+ num_planes = fb->format->num_planes; + kmb_plane = to_kmb_plane(plane); + plane_id = kmb_plane->id; + dev_p = to_kmb(plane->dev);

src_w = plane->state->src_w >> 16; @@ -405,11 +452,13 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); +#endif }

static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { .atomic_check = kmb_plane_atomic_check, .atomic_update = kmb_plane_atomic_update, + .atomic_disable = kmb_plane_atomic_disable };

void kmb_plane_destroy(struct drm_plane *plane) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 0c0b146..d2b884c 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -9,6 +9,7 @@ #define ENABLE 1 #define DISABLE 0 /*from Data Book section 12.5.8.1 page 4322 */ +#define CPR_BASE_ADDR (0x20810000) #define MIPI_BASE_ADDR (0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (0x20930000) @@ -524,6 +525,9 @@ #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \ kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) +#define MIPI_TX_HS_DMA_CFG (0x1a8) +#define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac) +#define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4)

/* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 (0x00) @@ -552,6 +556,7 @@ #define MIPI_CTRL_IRQ_CLEAR1 (0x014) #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, M+N) +#define MIPI_CTRL_DIG_LOOPBACK (0x018) #define MIPI_TX_HS_IRQ_STATUS (0x01c) #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ HS_OFFSET(M)) @@ -629,12 +634,16 @@ #define MIPI_TX_HS_TEST_PAT_CTRL (0x230) #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) -#define TP_EN_VCm(M) ((M) * 0x04) +#define TP_EN_VCm(M) (1 << ((M) * 0x04)) #define TP_SEL_VCm(M, N) \ (N << (((M) * 0x04) + 1)) #define TP_STRIPE_WIDTH(M) ((M) << 16) #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) +#define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \ + (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M)) #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) +#define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \ + (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M))

/* D-PHY regs */ #define DPHY_ENABLE (0x100) @@ -650,15 +659,25 @@ #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, (dphy+offset)) #define DPHY_INIT_CTRL2 (0x10c) +#define DPHY_PLL_OBS0 (0x110) +#define DPHY_PLL_OBS1 (0x114) +#define DPHY_PLL_OBS2 (0x118) #define DPHY_FREQ_CTRL0_3 (0x11c) +#define DPHY_FREQ_CTRL4_7 (0x120) #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \ + ((dphy/4)*4), (dphy % 4) * 8, 6, val)

+#define DPHY_FORCE_CTRL0 (0x128) +#define DPHY_FORCE_CTRL1 (0x12C) #define MIPI_DPHY_STAT0_3 (0x134) +#define MIPI_DPHY_STAT4_7 (0x138) #define GET_STOPSTATE_DATA(dev, dphy) \ (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + (dphy/4)*4)) \ >> (((dphy % 4)*8)+4)) & 0x03) + +#define MIPI_DPHY_ERR_STAT6_7 (0x14C) + #define DPHY_TEST_CTRL0 (0x154) #define SET_DPHY_TEST_CTRL0(dev, dphy) \ kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy)) @@ -680,8 +699,15 @@ 4, ((val) << (((dphy)%4)*8))) #define DPHY_TEST_DOUT0_3 (0x168) #define GET_TEST_DOUT0_3(dev, dphy) \ - (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3 + 4) \ + (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3) \ + >> (((dphy)%4)*8) & 0xff) +#define DPHY_TEST_DOUT4_7 (0x16C) +#define GET_TEST_DOUT4_7(dev, dphy) \ + (kmb_read_mipi(dev, DPHY_TEST_DOUT4_7) \ >> (((dphy)%4)*8) & 0xff) +#define DPHY_TEST_DOUT8_9 (0x170) +#define DPHY_TEST_DIN4_7 (0x160) +#define DPHY_TEST_DIN8_9 (0x164) #define DPHY_PLL_LOCK (0x188) #define GET_PLL_LOCK(dev, dphy) \ (kmb_read_mipi(dev, DPHY_PLL_LOCK) \ @@ -694,6 +720,10 @@ #define MIPI_COMMON (1<<2) #define MIPI_TX0 (1<<9) #define MSS_CAM_RSTN_CTRL (0x14) +#define MSS_CAM_RSTN_SET (0x20) +#define MSS_CAM_RSTN_CLR (0x24)

+#define MSSCPU_CPR_CLK_EN (0x0) +#define MSSCPU_CPR_RST_EN (0x10) #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */

To run modetest without ADV driver, enable LCD_TEST and FCC_TEST. Also made front porches 0, and some changes in the plane init.

v2: upclassed dev_private

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++---- drivers/gpu/drm/kmb/kmb_drv.c | 6 +-- drivers/gpu/drm/kmb/kmb_drv.h | 3 +- drivers/gpu/drm/kmb/kmb_dsi.c | 85 +++++++++++++++++++++++++++-------------- drivers/gpu/drm/kmb/kmb_plane.c | 15 ++++++-- 5 files changed, 78 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 21b2d7f..f77e6f5 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -81,14 +81,15 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) struct videomode vm; int vsync_start_offset; int vsync_end_offset; - unsigned int ctrl = 0; struct kmb_drm_private *dev_p = to_kmb(dev); #endif /* initialize mipi */ kmb_dsi_hw_init(dev); #ifdef LCD_TEST - vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; - vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; +// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; + vm.vfront_porch = 0; +// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; + vm.vback_porch = 0; vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; @@ -131,12 +132,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10); } /* enable VL1 layer as default */ - ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_OUTPUT_ENABLED; - kmb_write_lcd(dev_p, LCD_CONTROL, ctrl); - kmb_write_lcd(dev_p, LCD_TIMING_GEN_TRIG, ENABLE); + kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif /* TBD */ /* set clocks here */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 3542de7..8bd3011 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -216,6 +216,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) #endif /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); +//#define MIPI_CLK +#ifdef MIPI_CLK ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { @@ -223,6 +225,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) KMB_MIPI_DEFAULT_CLK); goto setup_fail; } +#endif DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n", KMB_MIPI_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); @@ -319,8 +322,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } - - DRM_INFO("%s : %d\n", __func__, __LINE__); #ifdef WIP ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { @@ -335,7 +336,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) drm_crtc_cleanup(&dev_p->crtc); #endif setup_fail: - DRM_INFO("%s : %d\n", __func__, __LINE__); of_reserved_mem_device_release(drm->dev);

return ret; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 7e44446..89d7845 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -8,7 +8,8 @@

#include "kmb_regs.h"

-/*#define FCCTEST*/ +#define FCCTEST +#define LCD_TEST #define KMB_MAX_WIDTH 1920 /*max width in pixels */ #define KMB_MAX_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 9da9d9f..c23719c 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -24,18 +24,19 @@

static int hw_initialized; #define IMAGE_PATH "/home/root/1280x720.pnm" -#define MIPI_TX_TEST_PATTERN_GENERATION +//#define MIPI_TX_TEST_PATTERN_GENERATION +//#define RTL_TEST +//#define IMG_WIDTH_PX 640 +//#define IMG_HEIGHT_LINES 10

-#define IMG_HEIGHT_LINES 720 -#define IMG_WIDTH_PX 1280 #define LCD_BYTESPP 1

/*MIPI TX CFG*/ -#define MIPI_TX_ACTIVE_LANES 2 //#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 //#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 +//#define MIPI_TX_REF_CLK_KHZ 23809 #define MIPI_TX_CFG_CLK_KHZ 24000

/*DPHY Tx test codes*/ @@ -79,6 +80,18 @@ static struct mipi_dsi_device *dsi_device; * these will eventually go to the device tree sections, * and can be used as a refernce later for device tree additions */ +#ifdef RES_1920x1080 +#define IMG_HEIGHT_LINES 1080 +#define IMG_WIDTH_PX 1920 +#define MIPI_TX_ACTIVE_LANES 4 +#endif + +#define RES_1280x720 +#ifdef RES_1280x720 +#define IMG_HEIGHT_LINES 720 +#define IMG_WIDTH_PX 1280 +#define MIPI_TX_ACTIVE_LANES 2 +#endif struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, @@ -88,6 +101,22 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .dma_packed = 1 };

+#ifdef RES_1920x1080 +struct mipi_tx_frame_cfg mipitx_frame0_cfg = { + .sections[0] = &mipi_tx_frame0_sect_cfg, + .sections[1] = NULL, + .sections[2] = NULL, + .sections[3] = NULL, + .vsync_width = 5, + .v_backporch = 36, + .v_frontporch = 4, + .hsync_width = 44, + .h_backporch = 148, + .h_frontporch = 88 +}; +#endif + +#ifdef RES_1280x720 struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[0] = &mipi_tx_frame0_sect_cfg, .sections[1] = NULL, @@ -100,6 +129,7 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .h_backporch = 220, .h_frontporch = 110, }; +#endif

struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { .hfp_blank_en = 0, @@ -121,8 +151,7 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS, .ref_clk_khz = MIPI_TX_REF_CLK_KHZ, .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ, -// .data_if = MIPI_IF_PARALLEL, - .data_if = MIPI_IF_DMA, + .data_if = MIPI_IF_PARALLEL, .tx_ctrl_cfg = { .frames[0] = &mipitx_frame0_cfg, .frames[1] = NULL, @@ -314,7 +343,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm,

struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { - struct device_node *encoder_node; struct drm_bridge *bridge;

/* Create and register MIPI DSI host */ @@ -593,7 +621,13 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);

- /*frame generator number of lines */ + DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", + __func__, __LINE__, fg_cfg->bpp, sysclk, + fg_cfg->lane_rate_mbps, fg_cfg->active_lanes); + + DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__, + ppl_llp_ratio); + /*frame generator number of lines*/ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active);

@@ -754,8 +788,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) sync_cfg |= HACT_WAIT_STOP(fg_en);

- /* MIPI_TX_HS_CTRL */ - ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */ + /* MIPI_TX_HS_CTRL*/ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) @@ -842,6 +876,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, active_vchannels++;

/*connect lcd to mipi */ + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);

/*stop iterating as only one virtual channel shall be used for * LCD connection @@ -1508,7 +1543,7 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); break; } - udelay(1); +// udelay(1); } while (stopstatedata != data_lanes);

DRM_INFO("********** DPHY %d INIT - %s **********\n", @@ -1523,10 +1558,9 @@ static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) int status = 1;

do { - ; /*TODO-need to add a time out and return failure */ i++; - udelay(1); + // udelay(1); if (i > TIMEOUT) { status = 0; DRM_INFO("%s: timing out", __func__); @@ -1583,7 +1617,7 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); - udelay(1000); +// udelay(1000); dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); } else { /* Single DPHY */ dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, @@ -1707,11 +1741,9 @@ int kmb_kernel_read(struct file *file, loff_t offset, int kmb_dsi_hw_init(struct drm_device *dev) { struct kmb_drm_private *dev_p = to_kmb(dev); - int i;

if (hw_initialized) return 0; - udelay(1000); kmb_write_mipi(dev_p, DPHY_ENABLE, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); @@ -1719,19 +1751,15 @@ int kmb_dsi_hw_init(struct drm_device *dev)

/* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - /* irq initialization */ - //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); /*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); #ifdef MIPI_TX_TEST_PATTERN_GENERATION - for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) { - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, - 0x05, 0xffffff, 0xff00, i); - } - DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__, - __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); -#else - dma_data_length = image_height * image_width * unpacked_bytes; + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff, + 0xff00, MIPI_CTRL6); + DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__, + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); +#elseif MIPI_DMA + dma_data_length = image_height * image_width * unpacked_bytes; file = filp_open(IMAGE_PATH, O_RDWR, 0); if (IS_ERR(file)) { DRM_ERROR("filp_open failed\n"); @@ -1765,7 +1793,6 @@ int kmb_dsi_hw_init(struct drm_device *dev) DRM_INFO("count = %d\n", count); kfree(file_buf); filp_close(file, NULL); - #endif //MIPI_TX_TEST_PATTERN_GENERATION

hw_initialized = true; @@ -1834,13 +1861,15 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return ret; } #endif + #ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); #endif

#ifdef FCCTEST +#ifndef LCD_TEST kmb_dsi_hw_init(dev); #endif - +#endif return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 1a40ef0..c57f06f 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -345,10 +345,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]);

/*TBD check visible? */ - +/* dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1 | LCD_DMA_LAYER_VSTRIDE_EN; +*/ + dma_cfg = LCD_DMA_LAYER_ENABLE + | LCD_DMA_LAYER_AXI_BURST_1 + | LCD_DMA_LAYER_VSTRIDE_EN;

/* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), @@ -425,10 +429,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, break; }

- ctrl |= LCD_CTRL_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; +// ctrl |= LCD_CTRL_ENABLE; +// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE +// | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;

+ ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED; /*LCD is connected to MIPI on kmb * Therefore this bit is required for DSI Tx */ @@ -452,6 +458,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); +// kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif }

Mipi input expects the memory layout to be unpacked with 8 bits per pixel in RGB (BRG) order. If the LCD is not configured properly, corrupted output results, changed dma_unpacked to 0 in mipi FG.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 6 +++--- drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 27 +++++++++++++++++---------- drivers/gpu/drm/kmb/kmb_dsi.h | 1 + drivers/gpu/drm/kmb/kmb_plane.c | 37 +++++++++++++++++++++++++++---------- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 6 files changed, 50 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index cbf998f..a6a0444 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -87,16 +87,16 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_dsi_hw_init(dev); #ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; - vm.vfront_porch = 0; + vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; - vm.vback_porch = 0; + vm.vback_porch = 2; // vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; vm.vsync_len = 1; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; vm.hback_porch = 0; //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; - vm.hsync_len = 1; + vm.hsync_len = 7; // vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;

vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index aa77631..3a1b66c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -30,6 +30,7 @@ struct kmb_drm_private { spinlock_t irq_lock; int irq_lcd; int irq_mipi; + dma_addr_t fb_addr; };

static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index a9f2d78..e01c4f9 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -25,6 +25,7 @@ static int hw_initialized; #define IMAGE_PATH "/home/root/1280x720.pnm" //#define MIPI_TX_TEST_PATTERN_GENERATION +//#define MIPI_DMA //#define RTL_TEST //#define IMG_WIDTH_PX 640 //#define IMG_HEIGHT_LINES 10 @@ -33,6 +34,7 @@ static int hw_initialized;

/*MIPI TX CFG*/ //#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 800 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 //#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 @@ -80,14 +82,14 @@ static struct mipi_dsi_device *dsi_device; * these will eventually go to the device tree sections, * and can be used as a refernce later for device tree additions */ -//#define RES_1920x1080 +#define RES_1920x1080 #ifdef RES_1920x1080 #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 #endif

-#define RES_1280x720 +//#define RES_1280x720 #ifdef RES_1280x720 #define IMG_HEIGHT_LINES 720 #define IMG_WIDTH_PX 1280 @@ -97,9 +99,9 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, - //.data_mode = MIPI_DATA_MODE1, - .data_mode = MIPI_DATA_MODE0, - .dma_packed = 1 + .data_mode = MIPI_DATA_MODE1, +// .data_mode = MIPI_DATA_MODE0, + .dma_packed = 0 };

#ifdef RES_1920x1080 @@ -544,12 +546,15 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, << MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */ /* data mode */ cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) - << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ - cfg |= MIPI_TX_SECT_DMA_PACKED; - DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg); + << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25]*/ + if (ph_cfg->dma_packed) + cfg |= MIPI_TX_SECT_DMA_PACKED; + DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", + __func__, __LINE__, ctrl_no, frame_id, section, cfg, + ph_cfg->dma_packed); kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + section)), cfg); + /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections *there are 2 registers for unpacked bytes - @@ -601,6 +606,7 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, ph_cfg.wc = *wc; ph_cfg.data_mode = frame_scfg->data_mode; ph_cfg.data_type = frame_scfg->data_type; + ph_cfg.dma_packed = frame_scfg->dma_packed; ph_cfg.vchannel = frame_id;

mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, @@ -627,6 +633,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, * mipi clock speed in RTL tests */ sysclk = KMB_SYS_CLK_MHZ - 50; +// sysclk = KMB_SYS_CLK_MHZ;

/*ppl-pixel packing layer, llp-low level protocol * frame genartor timing parameters are clocked on the system clock diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 1ece5c7..912e06d 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -262,6 +262,7 @@ struct mipi_tx_frame_sect_phcfg { enum mipi_data_mode data_mode; enum mipi_dsi_data_type data_type; uint8_t vchannel; + uint8_t dma_packed; };

struct mipi_tx_frame_cfg { diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index fce8dca..f6dfe24 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -96,6 +96,7 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 };

+ static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -244,17 +245,21 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; break; } + DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); return val; }

unsigned int set_bits_per_pixel(const struct drm_format_info *format) { - int i; u32 bpp = 0; unsigned int val = 0;

- for (i = 0; i < format->num_planes; i++) - bpp += 8 * format->cpp[i]; + if (format->num_planes > 1) { + val = LCD_LAYER_8BPP; + return val; + } + + bpp += 8*format->cpp[0];

switch (bpp) { case 8: @@ -270,8 +275,8 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) val = LCD_LAYER_32BPP; break; } - DRM_INFO("%s : %d bpp=0x%x\n", __func__, __LINE__, bpp); - val = LCD_LAYER_24BPP; + + DRM_INFO("%s : %d bpp=%d val=%d\n", __func__, __LINE__, bpp, val); return val; }

@@ -325,11 +330,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,

dev_p = to_kmb(plane->dev);

- src_w = plane->state->src_w >> 16; + src_w = (plane->state->src_w >> 16); src_h = plane->state->src_h >> 16; crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y;

+ DRM_INFO("src_w=%d src_h=%d\n", src_w, src_h); kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); @@ -339,6 +345,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 100 try this for now */ val |= LCD_LAYER_FIFO_100; + val |= LCD_LAYER_BGR_ORDER; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);

/*re-initialize interrupts */ @@ -353,29 +360,33 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_DMA_LAYER_VSTRIDE_EN; */ dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN - | LCD_DMA_LAYER_AXI_BURST_16 | LCD_DMA_LAYER_CONT_UPDATE; + | LCD_DMA_LAYER_AXI_BURST_16 | + LCD_DMA_LAYER_CONT_PING_PONG_UPDATE;

/* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_FIFO_FLUSH + plane_id*0x400, 1);

/* pinpong mode is enabled - at the end of DMA transfer, start new * transfer alternatively using main and shadow register settings. * So update both main and shadow registers */ addr = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dev_p->fb_addr = addr; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr);

width = fb->width; height = fb->height; - dma_len = width * height * 1; + dma_len = width * height * fb->format->cpp[0]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len);

- kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), width); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width)); + (width*fb->format->cpp[0]));

/*program Cb/Cr for planar formats*/ if (num_planes > 1) { @@ -413,6 +424,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,

/* enable DMA */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", __func__, + __LINE__, dma_cfg, + kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id)));

switch (plane_id) { case LAYER_0: @@ -446,6 +460,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, * from the Myriadx tests */ out_format |= LCD_OUTF_FORMAT_RGB888; +// out_format |= LCD_OUTF_BGR_ORDER;

if (val & LCD_LAYER_PLANAR_STORAGE) { /*enable CSC if input is planar and output is RGB */ @@ -457,7 +472,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /*leave RGB order,conversion mode and clip mode to default*/ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; +// out_format |= LCD_OUTF_SYNC_MODE ; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); + // kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index ca7e4be..e95891a 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -350,6 +350,7 @@ #define LCD_OUTF_BGR_ORDER (1 << 5) #define LCD_OUTF_Y_ORDER (1 << 6) #define LCD_OUTF_CRCB_ORDER (1 << 7) +#define LCD_OUTF_SYNC_MODE (1 << 11) #define LCD_OUTF_RGB_CONV_MODE (1 << 14) #define LCD_OUTF_MIPI_RGB_MODE (1 << 18)

Removed hardcoded timings, set timings based on the current mode's input timings. Also calculate and set the lane rate based on the timings.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++- drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++++++++++++++++++++++------------------- drivers/gpu/drm/kmb/kmb_dsi.h | 2 +- 3 files changed, 61 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index a6a0444..1987185e 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -84,7 +84,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) struct kmb_drm_private *dev_p = to_kmb(dev); #endif /* initialize mipi */ - kmb_dsi_hw_init(dev); + kmb_dsi_hw_init(dev, m); + DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", + m->crtc_vsync_start - m->crtc_vdisplay, + m->crtc_vtotal - m->crtc_vsync_end, + m->crtc_vsync_end - m->crtc_vsync_start, + m->crtc_hsync_start - m->crtc_hdisplay, + m->crtc_htotal - m->crtc_hsync_end, + m->crtc_hsync_end - m->crtc_hsync_start); #ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index e01c4f9..e9499cf 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -27,19 +27,12 @@ static int hw_initialized; //#define MIPI_TX_TEST_PATTERN_GENERATION //#define MIPI_DMA //#define RTL_TEST -//#define IMG_WIDTH_PX 640 -//#define IMG_HEIGHT_LINES 10 - -#define LCD_BYTESPP 1

/*MIPI TX CFG*/ -//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 -//#define MIPI_TX_LANE_DATA_RATE_MBPS 800 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 -//#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 -//#define MIPI_TX_REF_CLK_KHZ 23809 #define MIPI_TX_CFG_CLK_KHZ 24000 +#define MIPI_TX_BPP 24

/*DPHY Tx test codes*/ #define TEST_CODE_FSM_CONTROL 0x03 @@ -78,23 +71,12 @@ static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device;

/* - * These are added here only temporarily for testing, - * these will eventually go to the device tree sections, - * and can be used as a refernce later for device tree additions + * Default setting is 1080p, 4 lanes. */ -#define RES_1920x1080 -#ifdef RES_1920x1080 #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 -#endif

-//#define RES_1280x720 -#ifdef RES_1280x720 -#define IMG_HEIGHT_LINES 720 -#define IMG_WIDTH_PX 1280 -#define MIPI_TX_ACTIVE_LANES 2 -#endif struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, @@ -104,7 +86,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .dma_packed = 0 };

-#ifdef RES_1920x1080 struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[0] = &mipi_tx_frame0_sect_cfg, .sections[1] = NULL, @@ -117,22 +98,6 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .h_backporch = 148, .h_frontporch = 88 }; -#endif - -#ifdef RES_1280x720 -struct mipi_tx_frame_cfg mipitx_frame0_cfg = { - .sections[0] = &mipi_tx_frame0_sect_cfg, - .sections[1] = NULL, - .sections[2] = NULL, - .sections[3] = NULL, - .vsync_width = 5, - .v_backporch = 20, - .v_frontporch = 5, - .hsync_width = 40, - .h_backporch = 220, - .h_frontporch = 110, -}; -#endif

struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { .hfp_blank_en = 0, @@ -1720,10 +1685,58 @@ int kmb_kernel_read(struct file *file, loff_t offset, return ret; }

-int kmb_dsi_hw_init(struct drm_device *dev) +int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) { struct kmb_drm_private *dev_p = to_kmb(dev); + u64 data_rate; + + mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES; + if (mode != NULL) { + mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; + mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; + mipitx_frame0_cfg.vsync_width = + mode->crtc_vsync_end - mode->crtc_vsync_start; + mipitx_frame0_cfg.v_backporch = + mode->crtc_vtotal - mode->crtc_vsync_end; + mipitx_frame0_cfg.v_frontporch = + mode->crtc_vsync_start - mode->crtc_vdisplay; + mipitx_frame0_cfg.hsync_width = + mode->crtc_hsync_end - mode->crtc_hsync_start; + mipitx_frame0_cfg.h_backporch = + mode->crtc_htotal - mode->crtc_hsync_end; + mipitx_frame0_cfg.h_frontporch = + mode->crtc_hsync_start - mode->crtc_hdisplay; + /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 + * to convert to Mbps + */ + DRM_INFO("htotal = %d vtotal=%d refresh=%d\n", + mode->crtc_htotal, mode->crtc_vtotal, + drm_mode_vrefresh(mode)); + data_rate = + ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) + * (u32)(drm_mode_vrefresh(mode)) + * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000; + DRM_INFO("data_rate = %llu active_lanes=%d\n", + data_rate, mipi_tx_init_cfg.active_lanes); + + /*when late rate < 800 - modeset fails with 4 lanes - + * so switch to 2 lanes + */ + if (data_rate < 800) { + mipi_tx_init_cfg.active_lanes = 2; + mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2; + } else { + mipi_tx_init_cfg.lane_rate_mbps = data_rate; + } + DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps); + DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n", + mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch, + mipitx_frame0_cfg.vsync_width, + mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch, + mipitx_frame0_cfg.hsync_width, + mipi_tx_init_cfg.lane_rate_mbps);

+ } if (hw_initialized) return 0; kmb_write_mipi(dev_p, DPHY_ENABLE, 0); @@ -1806,15 +1819,13 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) drm_encoder_cleanup(encoder); return ret; } -#endif

-#ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); #endif

#ifdef FCCTEST #ifndef LCD_TEST - kmb_dsi_hw_init(dev); + kmb_dsi_hw_init(dev, NULL); #endif #endif return 0; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 912e06d..7857576 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -321,7 +321,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void kmb_dsi_host_unregister(void); -int kmb_dsi_hw_init(struct drm_device *dev); +int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode);

#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base)

The issue was that spurious interrupts were happening before the LCD controller was enabled and system hangs. Fix is to clear LCD interrupts and disable them before modeset and re enable them after enabling LCD controller.

v2: upclassed dev_private

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 12 +++++++++--- drivers/gpu/drm/kmb/kmb_drv.c | 21 +++------------------ 2 files changed, 12 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 589a841..c390bbe 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -78,6 +78,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) int vsync_start_offset; int vsync_end_offset; struct kmb_drm_private *dev_p = to_kmb(dev); + unsigned int val = 0;

/* initialize mipi */ kmb_dsi_hw_init(dev, m); @@ -88,6 +89,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) m->crtc_hsync_start - m->crtc_hdisplay, m->crtc_htotal - m->crtc_hsync_end, m->crtc_hsync_end - m->crtc_hsync_start); + val = kmb_read_lcd(dev_p, LCD_INT_ENABLE); + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, val); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, ~0x0); // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; @@ -136,9 +140,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, 10); kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10); } - /* enable VL1 layer as default */ kmb_write_lcd(dev_p, LCD_TIMING_GEN_TRIG, ENABLE); kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, val); #endif /* TBD */ /* set clocks here */ @@ -170,8 +174,9 @@ static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct drm_device *dev = crtc->dev; + struct kmb_drm_private *dev_p = to_kmb(dev);

- kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, LCD_INT_VERT_COMP); }

@@ -179,8 +184,9 @@ static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct drm_device *dev = crtc->dev; + struct kmb_drm_private *dev_p = to_kmb(dev);

- kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, LCD_INT_VERT_COMP);

spin_lock_irq(&crtc->dev->event_lock); diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index e6aa32c..308036e 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -37,8 +37,6 @@ static irqreturn_t kmb_isr(int irq, void *arg);

static struct clk *clk_lcd; static struct clk *clk_mipi; -static struct clk *clk_msscam; -static struct clk *clk_pll0out0; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg;

@@ -59,12 +57,6 @@ int kmb_display_clk_enable(void) DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); return ret; } -/* ret = clk_prepare_enable(clk_msscam); - if (ret) { - DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); - return ret; - } - */

ret = clk_prepare_enable(clk_mipi_ecfg); if (ret) { @@ -87,8 +79,6 @@ static int kmb_display_clk_disable(void) clk_disable_unprepare(clk_lcd); if (clk_mipi) clk_disable_unprepare(clk_mipi); - if (clk_msscam) - clk_disable_unprepare(clk_msscam); if (clk_mipi_ecfg) clk_disable_unprepare(clk_mipi_ecfg); if (clk_mipi_cfg) @@ -180,14 +170,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } - clk_pll0out0 = clk_get(&pdev->dev, "clk_pll0_out0"); - if (IS_ERR(clk_pll0out0)) - DRM_ERROR("clk_get() failed clk_pll0_out0\n"); - - if (clk_pll0out0) - DRM_INFO("Get clk_pll0out0 = %ld\n", - clk_get_rate(clk_pll0out0)); - clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); @@ -394,6 +376,9 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) break; } } + + /* clear all interrupts */ + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); return IRQ_HANDLED; }

Set swap bit for the colors to display correctly when the format is RGB and not set when its BGR.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_plane.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 1582ccf..5fd1837 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -198,54 +198,55 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ + /* packed formats */ + /* looks hw requires B & G to be swapped when RGB */ case DRM_FORMAT_RGB332: - val = LCD_LAYER_FORMAT_RGB332; + val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR4444: - val = LCD_LAYER_FORMAT_RGBX4444 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBX4444; break; case DRM_FORMAT_ARGB4444: - val = LCD_LAYER_FORMAT_RGBA4444; + val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR4444: - val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA4444; break; case DRM_FORMAT_XRGB1555: - val = LCD_LAYER_FORMAT_XRGB1555; + val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR1555: - val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_XRGB1555; break; case DRM_FORMAT_ARGB1555: - val = LCD_LAYER_FORMAT_RGBA1555; + val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR1555: - val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA1555; break; case DRM_FORMAT_RGB565: - val = LCD_LAYER_FORMAT_RGB565; + val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_BGR565: - val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGB565; break; case DRM_FORMAT_RGB888: - val = LCD_LAYER_FORMAT_RGB888; + val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_BGR888: - val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGB888; break; case DRM_FORMAT_XRGB8888: - val = LCD_LAYER_FORMAT_RGBX8888; + val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR8888: - val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBX8888; break; case DRM_FORMAT_ARGB8888: - val = LCD_LAYER_FORMAT_RGBA8888; + val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR8888: - val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA8888; break; } DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); @@ -348,7 +349,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 100 try this for now */ val |= LCD_LAYER_FIFO_100; - val |= LCD_LAYER_BGR_ORDER; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);

/*re-initialize interrupts */

The issue was video starts fine, but towards the end, the color disappers. Do the layer initializations only once, but update the DMA registers for every frame. Also changed DRM_INFO to DRM_DEBUG.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_plane.c | 150 ++++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index a1d616a..6be0997 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -97,6 +97,9 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 };

+/*plane initialization status */ +static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; + static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -157,9 +160,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), LCD_DMA_LAYER_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); - DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", - __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), - kmb_read_lcd(dev_p, LCD_INT_ENABLE)); + DRM_DEBUG("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", + __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), + kmb_read_lcd(dev_p, LCD_INT_ENABLE)); }

unsigned int set_pixel_format(u32 format) @@ -317,8 +320,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id; int num_planes; - /*plane initialization status */ - static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; static dma_addr_t addr[MAX_SUB_PLANES] = { 0, 0, 0 };

if (!plane || !plane->state || !state) @@ -339,9 +340,56 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y;

- DRM_INFO + DRM_DEBUG ("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x", __func__, __LINE__, src_w, src_h, fb->format->format, fb->flags); + + width = fb->width; + height = fb->height; + dma_len = (width * height * fb->format->cpp[0]); + DRM_DEBUG("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + + addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dev_p->fb_addr = (dma_addr_t) addr; + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), + addr[Y_PLANE] + fb->offsets[0]); + /*program Cb/Cr for planar formats */ + if (num_planes > 1) { + if (fb->format->format == DRM_FORMAT_YUV420 || + fb->format->format == DRM_FORMAT_YVU420) + width /= 2; + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_1]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, + U_PLANE); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr[U_PLANE]); + if (num_planes == 3) { + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, + plane->state, + V_PLANE); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr[V_PLANE]); + } + } if (plane_init_status[plane_id] != INITIALIZED) { kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); @@ -354,55 +402,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= LCD_LAYER_FIFO_100; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);

- /*re-initialize interrupts */ - kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, - layer_irqs[plane_id]); - kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, layer_irqs[plane_id]); - - dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | - LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; - - width = fb->width; - height = fb->height; - dma_len = (width * height * fb->format->cpp[0]); - DRM_INFO("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), - dma_len); - - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[0]); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); - - /*program Cb/Cr for planar formats */ - if (num_planes > 1) { - if (fb->format->format == DRM_FORMAT_YUV420 || - fb->format->format == DRM_FORMAT_YVU420) - width /= 2; - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_1]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); - if (num_planes == 3) { - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_VSTRIDE - (plane_id), fb->pitches[LAYER_2]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_WIDTH - (plane_id), - (width * fb->format->cpp[0])); - } - } - - /* enable DMA */ - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", - __func__, __LINE__, dma_cfg, - kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); - switch (plane_id) { case LAYER_0: ctrl = LCD_CTRL_VL1_ENABLE; @@ -444,38 +443,18 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); - - kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, - layer_irqs[plane_id]); plane_init_status[plane_id] = INITIALIZED; }

- addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); - dev_p->fb_addr = (dma_addr_t) addr; - if (num_planes > 1) { - addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, - U_PLANE); - if (num_planes == 3) - addr[V_PLANE] = - drm_fb_cma_get_gem_addr(fb, plane->state, V_PLANE); - } - /* disable DMA first */ - kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), - addr[Y_PLANE] + fb->offsets[0]); - if (num_planes > 1) { - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), - addr[U_PLANE]); - if (num_planes == 3) - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_START_CR_ADR(plane_id), - addr[V_PLANE]); - } - /* Enable DMA */ - kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); - DRM_INFO("%s : %d flipping.....\n", __func__, __LINE__); + dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | + LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; + + /* enable DMA */ + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + DRM_DEBUG("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", + __func__, __LINE__, dma_cfg, + kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); + return;

#endif @@ -589,6 +568,9 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) ret); goto cleanup; } + DRM_DEBUG("%s : %d plane=%px\n i=%d type=%d", + __func__, __LINE__, &plane->base_plane, + i, plane_type);

drm_plane_helper_add(&plane->base_plane, &kmb_plane_helper_funcs);

From: Edmund Dea edmund.j.dea@intel.com

to remove compiler warnings and general clean up

v2: minor code review changes v3: upclassed dev_private, corrected spelling

Signed-off-by: Edmund Dea edmund.j.dea@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 46 +- drivers/gpu/drm/kmb/kmb_crtc.h | 6 +- drivers/gpu/drm/kmb/kmb_drv.c | 111 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 107 ++-- drivers/gpu/drm/kmb/kmb_dsi.c | 1074 +++++++++++++++++++++------------------ drivers/gpu/drm/kmb/kmb_dsi.h | 84 ++- drivers/gpu/drm/kmb/kmb_plane.c | 155 ++---- drivers/gpu/drm/kmb/kmb_plane.h | 74 ++- drivers/gpu/drm/kmb/kmb_regs.h | 29 +- 9 files changed, 894 insertions(+), 792 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index c390bbe..aceca94 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -39,10 +39,10 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /*set which interval to generate vertical interrupt */ kmb_write_lcd(dev_p, LCD_VSTATUS_COMPARE, - LCD_VSTATUS_COMPARE_VSYNC); + LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); return 0; }

@@ -83,38 +83,38 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) /* initialize mipi */ kmb_dsi_hw_init(dev, m); DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", - m->crtc_vsync_start - m->crtc_vdisplay, - m->crtc_vtotal - m->crtc_vsync_end, - m->crtc_vsync_end - m->crtc_vsync_start, - m->crtc_hsync_start - m->crtc_hdisplay, - m->crtc_htotal - m->crtc_hsync_end, - m->crtc_hsync_end - m->crtc_hsync_start); + m->crtc_vsync_start - m->crtc_vdisplay, + m->crtc_vtotal - m->crtc_vsync_end, + m->crtc_vsync_end - m->crtc_vsync_start, + m->crtc_hsync_start - m->crtc_hdisplay, + m->crtc_htotal - m->crtc_hsync_end, + m->crtc_hsync_end - m->crtc_hsync_start); val = kmb_read_lcd(dev_p, LCD_INT_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, val); kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, ~0x0); -// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; +// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; -// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; +// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vback_porch = 2; -// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; +// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; vm.vsync_len = 1; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; vm.hback_porch = 0; //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; vm.hsync_len = 7; -// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; +// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;

vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;

- DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d\n", - __func__, __LINE__, m->crtc_vdisplay, - vm.vback_porch, vm.vfront_porch, - vm.vsync_len, m->crtc_hdisplay, - vm.hback_porch, vm.hfront_porch, vm.hsync_len); + DRM_DEBUG + ("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d", + __func__, __LINE__, m->crtc_vdisplay, vm.vback_porch, + vm.vfront_porch, vm.vsync_len, m->crtc_hdisplay, vm.hback_porch, + vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev_p, LCD_V_ACTIVEHEIGHT, - m->crtc_vdisplay - 1); + m->crtc_vdisplay - 1); kmb_write_lcd(dev_p, LCD_V_BACKPORCH, vm.vback_porch); kmb_write_lcd(dev_p, LCD_V_FRONTPORCH, vm.vfront_porch); kmb_write_lcd(dev_p, LCD_VSYNC_WIDTH, vm.vsync_len - 1); @@ -129,14 +129,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)

if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev_p, - LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); + LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); kmb_write_lcd(dev_p, LCD_V_BACKPORCH_EVEN, vm.vback_porch); kmb_write_lcd(dev_p, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch); kmb_write_lcd(dev_p, LCD_V_ACTIVEHEIGHT_EVEN, - m->crtc_vdisplay - 1); - /*this is hardcoded as 10 in the Myriadx code*/ + m->crtc_vdisplay - 1); + /*this is hardcoded as 10 in the Myriadx code */ kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, 10); kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10); } @@ -177,7 +177,7 @@ static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct kmb_drm_private *dev_p = to_kmb(dev);

kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); }

static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, @@ -187,7 +187,7 @@ static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct kmb_drm_private *dev_p = to_kmb(dev);

kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP);

spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h index 6c3efdd..51a0a39 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.h +++ b/drivers/gpu/drm/kmb/kmb_crtc.h @@ -24,6 +24,9 @@ #include <linux/wait.h> #include "kmb_drv.h"

+#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) +#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) + struct kmb_crtc { struct drm_crtc crtc_base; struct kmb_drm_private kmb_dev; @@ -32,8 +35,7 @@ struct kmb_crtc { struct kmb_crtc_state { struct drm_crtc_state crtc_base; }; -#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) -#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) + extern void kmb_plane_destroy(struct drm_plane *plane); extern struct kmb_plane *kmb_plane_init(struct drm_device *drm); #endif /* __KMB_CRTC_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 308036e..f5e1def 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -4,7 +4,7 @@ */

#include <linux/clk.h> -#include <linux/component.h> +//#include <linux/component.h> #include <linux/console.h> #include <linux/list.h> #include <linux/module.h> @@ -30,9 +30,9 @@ #include "kmb_plane.h" #include "kmb_regs.h"

-#define DEBUG +//#define DEBUG

-/*IRQ handler*/ +/* IRQ handler */ static irqreturn_t kmb_isr(int irq, void *arg);

static struct clk *clk_lcd; @@ -108,8 +108,6 @@ static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name) release_mem_region(res->start, size); return ERR_PTR(-ENOMEM); } - DRM_INFO("%s : %d mapped %s mmio size = %d\n", __func__, __LINE__, - name, size); return mem; }

@@ -117,8 +115,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = to_kmb(drm); struct platform_device *pdev = to_platform_device(drm->dev); - /*u32 version;*/ - int irq_lcd;// irq_mipi; + int irq_lcd; int ret = 0; unsigned long clk;

@@ -137,8 +134,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; }

- /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL - * register + /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and + * MSS_CAM_CLK_CTRL register */ dev_p->msscam_mmio = kmb_map_mmio(pdev, "msscam_regs"); if (IS_ERR(dev_p->msscam_mmio)) { @@ -154,22 +151,21 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } - - - #define KMB_CLOCKS #ifdef KMB_CLOCKS - /* Enable display clocks*/ + /* Enable display clocks */ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (IS_ERR(clk_lcd)) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } + clk_mipi = clk_get(&pdev->dev, "clk_mipi"); if (IS_ERR(clk_mipi)) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } + clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); @@ -181,59 +177,63 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi_cfg\n"); goto setup_fail; } - #ifdef LCD_TEST - /* Set LCD clock to 200 Mhz*/ - DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); + /* Set LCD clock to 200 Mhz */ + DRM_DEBUG("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK); if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_lcd to %d\n", - KMB_LCD_DEFAULT_CLK); + KMB_LCD_DEFAULT_CLK); } - DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", - KMB_LCD_DEFAULT_CLK/1000000, ret); + DRM_INFO("Setting LCD clock tp %d Mhz ret = %d\n", + KMB_LCD_DEFAULT_CLK / 1000000, ret); DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); #endif - /* Set MIPI clock to 24 Mhz*/ - DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); + #define MIPI_CLK #ifdef MIPI_CLK + /* Set MIPI clock to 24 Mhz */ + DRM_DEBUG("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CLK); goto setup_fail; } #endif DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n", - KMB_MIPI_DEFAULT_CLK/1000000, ret); + KMB_MIPI_DEFAULT_CLK / 1000000, ret); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi));

clk = clk_get_rate(clk_mipi_ecfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { - /* Set MIPI_ECFG clock to 24 Mhz*/ + /* Set MIPI_ECFG clock to 24 Mhz */ DRM_INFO("Get clk_mipi_ecfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); clk = clk_get_rate(clk_mipi_ecfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_ecfg to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } + DRM_INFO("Setting MIPI_ECFG clock tp %d Mhz ret = %d\n", - KMB_MIPI_DEFAULT_CLK/1000000, ret); + KMB_MIPI_DEFAULT_CFG_CLK / 1000000, ret); + DRM_INFO("Get clk_mipi_ecfg after set = %ld\n", clk); }

clk = clk_get_rate(clk_mipi_cfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { - /* Set MIPI_CFG clock to 24 Mhz*/ + /* Set MIPI_CFG clock to 24 Mhz */ DRM_INFO("Get clk_mipi_cfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_cfg, 24000000); clk = clk_get_rate(clk_mipi_cfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_cfg to %d\n", - KMB_MIPI_DEFAULT_CFG_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } DRM_INFO("Setting MIPI_CFG clock tp 24Mhz ret = %d\n", ret); @@ -242,10 +242,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags)

ret = kmb_display_clk_enable();

- /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ + /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); + #endif //KMB_CLOCKS + /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has redirected 79 to A53 IRQ 33 @@ -292,19 +294,21 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; }

- /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); if (ret) { DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } + ret = drm_irq_install(drm, irq_lcd); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); goto irq_fail; } + dev_p->irq_lcd = irq_lcd; + return 0;

irq_fail: @@ -316,10 +320,11 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) }

int kmb_atomic_helper_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_state *state) { if (!state) return 0; + return drm_atomic_helper_check(dev, state); }

@@ -339,7 +344,6 @@ static void kmb_setup_mode_config(struct drm_device *drm) drm->mode_config.funcs = &kmb_mode_config_funcs; }

- static irqreturn_t handle_lcd_irq(struct drm_device *dev) { unsigned long status, val; @@ -347,8 +351,8 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)

status = kmb_read_lcd(dev_p, LCD_INT_STATUS); if (status & LCD_INT_EOF) { - /*To DO - handle EOF interrupt? */ - kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF); + /*To DO - handle EOF interrupt? */ + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF); } if (status & LCD_INT_LINE_CMP) { /* clear line compare interrupt */ @@ -356,7 +360,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) LCD_INT_LINE_CMP); } if (status & LCD_INT_LAYER) { - /* clear layer interrupts */ + /* Clear layer interrupts */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); }

@@ -377,13 +381,13 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) } }

- /* clear all interrupts */ + /* Clear all interrupts */ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); return IRQ_HANDLED; }

#ifdef MIPI_IRQ -static irqreturn_t handle_mipi_irq(struct drm_device *dev) +static irqreturn_t handle_mipi_irq(struct drm_device *dev) { mipi_tx_handle_irqs(to_kmb(dev)); return IRQ_HANDLED; @@ -409,7 +413,7 @@ DEFINE_DRM_GEM_CMA_FOPS(fops);

static struct drm_driver kmb_driver = { .driver_features = DRIVER_GEM | - DRIVER_MODESET | DRIVER_ATOMIC, + DRIVER_MODESET | DRIVER_ATOMIC, .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, @@ -438,7 +442,9 @@ static void kmb_drm_unload(struct device *dev) struct drm_device *drm = dev_get_drvdata(dev); struct kmb_drm_private *dev_p = to_kmb(drm);

+#ifdef DEBUG dump_stack(); +#endif drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); of_node_put(dev_p->crtc.port); @@ -466,7 +472,7 @@ static void kmb_drm_unload(struct device *dev) of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm);

- /*release clks */ + /* Release clks */ kmb_display_clk_disable(); clk_put(clk_lcd); clk_put(clk_mipi); @@ -493,7 +499,8 @@ static int kmb_probe(struct platform_device *pdev) * and then the rest of the driver initialization can procees * afterwards and the bridge can be successfully attached. */ - adv_bridge = kmb_dsi_host_bridge_init(dev); + adv_bridge = kmb_dsi_host_bridge_init(dev); + #ifndef FCCTEST if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; @@ -502,6 +509,7 @@ static int kmb_probe(struct platform_device *pdev) return PTR_ERR(adv_bridge); } #endif + /* Create DRM device */ lcd = kzalloc(sizeof(*lcd), GFP_KERNEL); if (!lcd) @@ -518,7 +526,7 @@ static int kmb_probe(struct platform_device *pdev) dev_set_drvdata(dev, drm);

kmb_setup_mode_config(drm); - dev_set_drvdata(dev, drm); + dev_set_drvdata(dev, drm);

/* Load driver */ lcd->n_layers = KMB_MAX_PLANES; @@ -537,6 +545,7 @@ static int kmb_probe(struct platform_device *pdev) DRM_ERROR("failed to initialize vblank\n"); goto err_vblank; } + drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm);

@@ -547,7 +556,7 @@ static int kmb_probe(struct platform_device *pdev) goto err_register;

#ifndef FCCTEST -// drm_fbdev_generic_setup(drm, 32); + //drm_fbdev_generic_setup(drm, 32); #endif return 0;

@@ -570,7 +579,7 @@ static int kmb_remove(struct platform_device *pdev) return 0; }

-static const struct of_device_id kmb_of_match[] = { +static const struct of_device_id kmb_of_match[] = { {.compatible = "intel,kmb_display"}, {}, }; @@ -613,13 +622,13 @@ static int __maybe_unused kmb_pm_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume);

static struct platform_driver kmb_platform_driver = { - .probe = kmb_probe, - .remove = kmb_remove, - .driver = { - .name = "kmb-drm", - .pm = &kmb_pm_ops, - .of_match_table = kmb_of_match, - }, + .probe = kmb_probe, + .remove = kmb_remove, + .driver = { + .name = "kmb-drm", + .pm = &kmb_pm_ops, + .of_match_table = kmb_of_match, + }, };

module_platform_driver(kmb_platform_driver); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 3a1b66c..4b97a3d 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -10,27 +10,29 @@

#define FCCTEST #define LCD_TEST -#define KMB_MAX_WIDTH 1920 /*max width in pixels */ -#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MAX_WIDTH 1920 /*max width in pixels */ +#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 #define KMB_SYS_CLK_MHZ 500

+#define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) + struct kmb_drm_private { - struct drm_device drm; - void __iomem *lcd_mmio; - void __iomem *mipi_mmio; - void __iomem *msscam_mmio; - unsigned char n_layers; - struct clk *clk; - struct drm_crtc crtc; - struct kmb_plane *plane; - struct drm_atomic_state *state; - spinlock_t irq_lock; - int irq_lcd; - int irq_mipi; - dma_addr_t fb_addr; + struct drm_device drm; + void __iomem *lcd_mmio; + void __iomem *mipi_mmio; + void __iomem *msscam_mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_crtc crtc; + struct kmb_plane *plane; + struct drm_atomic_state *state; + spinlock_t irq_lock; + int irq_lcd; + int irq_mipi; + dma_addr_t fb_addr; };

static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) @@ -38,54 +40,12 @@ static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) return container_of(dev, struct kmb_drm_private, drm); }

-#define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) - struct blt_layer_config { unsigned char layer_format; }; -/* - * commenting this out to use hardcoded address for registers - * TODO we may need this later if we decide to get the address from - * the device tree - */ -#ifdef KMB_WRITE -static inline void kmb_write(struct kmb_drm_private *lcd, - unsigned int reg, u32 value) -{ - writel(value, lcd->mmio + reg); -} - -static inline u32 kmb_read(struct kmb_drm_private *lcd, unsigned int reg) -{ - return readl(lcd->mmio + reg); -} - -static inline void kmb_write_bits(struct kmb_drm_private *lcd, - unsigned int reg, u32 offset, u32 num_bits, - u32 value) -{ - u32 reg_val = kmb_read(lcd, reg); - u32 mask = (1 << num_bits) - 1; - - value &= mask; - mask <<= offset; - reg_val &= (~mask); - reg_val |= (value << offset); - writel(reg_val, lcd->mmio + reg); -} -static inline void kmb_write(unsigned int reg, u32 value) -{ - writel(value, reg); -} - -static inline u32 kmb_read(unsigned int reg) -{ - return readl(reg); -} -#endif

static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { #ifdef LCD_TEST writel(value, (dev_p->lcd_mmio + reg)); @@ -93,25 +53,25 @@ static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, }

static inline void kmb_write_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { writel(value, (dev_p->mipi_mmio + reg)); }

static inline void kmb_write_msscam(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { writel(value, (dev_p->msscam_mmio + reg)); }

static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p, - unsigned int reg) + unsigned int reg) { return readl(dev_p->msscam_mmio + reg); }

static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_msscam(dev_p, reg);

@@ -127,7 +87,7 @@ static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) }

static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { #ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); @@ -137,7 +97,7 @@ static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, }

static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { #ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); @@ -152,7 +112,8 @@ static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) }

static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset, u32 num_bits, u32 value) + unsigned int reg, u32 offset, + u32 num_bits, u32 value) { u32 reg_val = kmb_read_mipi(dev_p, reg); u32 mask = (1 << num_bits) - 1; @@ -161,11 +122,18 @@ static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, mask <<= offset; reg_val &= (~mask); reg_val |= (value << offset); +#ifdef DEBUG + if (reg == DPHY_FREQ_CTRL0_3 + 4) { + DRM_INFO("%s : %d reg=0x%x offset=%d num_bits=%d val=0x%x\n", + __func__, __LINE__, reg, offset, num_bits, + reg_val); + } +#endif kmb_write_mipi(dev_p, reg, reg_val); }

static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset) + unsigned int reg, u32 offset) { u32 reg_val = kmb_read_mipi(dev_p, reg);

@@ -173,7 +141,7 @@ static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, }

static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset) + unsigned int reg, u32 offset) { u32 reg_val = kmb_read_mipi(dev_p, reg);

@@ -181,7 +149,7 @@ static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, }

static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_mipi(dev_p, reg);

@@ -189,12 +157,13 @@ static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, }

static inline void kmb_clr_bitmask_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_mipi(dev_p, reg);

kmb_write_mipi(dev_p, reg, (reg_val & (~mask))); } + int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index e9499cf..6e38f16 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -3,9 +3,7 @@ * Copyright © 2019-2020 Intel Corporation */

-#include <linux/buffer_head.h> #include <linux/delay.h> -#include <linux/fs.h> #include <linux/gpio/consumer.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -23,56 +21,19 @@ #include "kmb_regs.h"

static int hw_initialized; -#define IMAGE_PATH "/home/root/1280x720.pnm" //#define MIPI_TX_TEST_PATTERN_GENERATION //#define MIPI_DMA //#define RTL_TEST +//#define DPHY_GET_FSM +//#define MIPI_TX_INIT_IRQS +//#define GET_SYS_CLK +//#define DPHY_READ_TESTCODE +//#define MIPI_TX_HANDLE_IRQS

-/*MIPI TX CFG*/ -#define MIPI_TX_LANE_DATA_RATE_MBPS 891 -#define MIPI_TX_REF_CLK_KHZ 24000 -#define MIPI_TX_CFG_CLK_KHZ 24000 -#define MIPI_TX_BPP 24 - -/*DPHY Tx test codes*/ -#define TEST_CODE_FSM_CONTROL 0x03 -#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C -#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E -#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F -#define TEST_CODE_PLL_VCO_CTRL 0x12 -#define TEST_CODE_PLL_GMP_CTRL 0x13 -#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 -#define TEST_CODE_PLL_LOCK_FILTER 0x15 -#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 -#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 -#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 -#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) -#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 -#define PLL_N_OVR_EN (1 << 4) -#define PLL_M_OVR_EN (1 << 5) -#define TEST_CODE_VOD_LEVEL 0x24 -#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C -#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D -#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 -#define TEST_CODE_PLL_ANALOG_PROG 0x1F -#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 -#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 -#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 - -/* D-Phy params */ -#define PLL_N_MIN 0 -#define PLL_N_MAX 15 -#define PLL_M_MIN 62 -#define PLL_M_MAX 623 -#define PLL_FVCO_MAX 1250 - -#define TIMEOUT 600 static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device;

-/* - * Default setting is 1080p, 4 lanes. - */ +/* Default setting is 1080p, 4 lanes */ #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 @@ -82,7 +43,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, .data_mode = MIPI_DATA_MODE1, -// .data_mode = MIPI_DATA_MODE0, .dma_packed = 0 };

@@ -132,18 +92,34 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .tx_always_use_hact = 1, .tx_hact_wait_stop = 1, } - };

-u8 *iBuf; - -struct mipi_hs_freq_range_cfg { +struct mipi_hs_freq_range_cfg { uint16_t default_bit_rate_mbps; uint8_t hsfreqrange_code; };

+struct vco_params { + u32 freq; + u32 range; + u32 divider; +}; + +static struct vco_params vco_table[] = { + {52, 0x3f, 8}, + {80, 0x39, 8}, + {105, 0x2f, 4}, + {160, 0x29, 4}, + {210, 0x1f, 2}, + {320, 0x19, 2}, + {420, 0x0f, 1}, + {630, 0x09, 1}, + {1100, 0x03, 1}, + {0xffff, 0x01, 1}, +}; + static struct mipi_hs_freq_range_cfg - mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { +mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00}, {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10}, {.default_bit_rate_mbps = 100, .hsfreqrange_code = 0x20}, @@ -225,14 +201,19 @@ static int kmb_dsi_get_modes(struct drm_connector *connector) int num_modes = 0;

num_modes = drm_add_modes_noedid(connector, - connector->dev->mode_config.max_width, - connector->dev->mode_config.max_height); + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + + DRM_INFO("width=%d height=%d\n", + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + DRM_INFO("num modes=%d\n", num_modes); + return num_modes; }

void kmb_dsi_host_unregister(void) { - DRM_INFO("%s : %d\n", __func__, __LINE__); mipi_dsi_host_unregister(dsi_host); kfree(dsi_host); } @@ -240,8 +221,6 @@ void kmb_dsi_host_unregister(void) static void kmb_dsi_connector_destroy(struct drm_connector *connector) { struct kmb_connector *kmb_connector = to_kmb_connector(connector); - - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_cleanup(connector); kfree(kmb_connector); } @@ -250,7 +229,6 @@ static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder) { struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder);

- DRM_INFO("%s : %d\n", __func__, __LINE__); if (!kmb_dsi) return;

@@ -312,7 +290,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, { struct kmb_dsi_host *host;

- DRM_INFO("%s : %d\n", __func__, __LINE__); host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL; @@ -331,6 +308,9 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { struct drm_bridge *bridge; +#ifndef FCCTEST + struct device_node *encoder_node; +#endif

/* Create and register MIPI DSI host */ if (!dsi_host) { @@ -352,12 +332,11 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) mipi_dsi_host_register(dsi_host); } #ifndef FCCTEST - /* find ADV7535 node and initialize it */ - DRM_INFO("trying to get bridge info %pOF\n", dev->of_node); + /* Find ADV7535 node and initialize it */ encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); - DRM_INFO("encoder node = %pOF\n", encoder_node); + if (!encoder_node) { - DRM_ERROR("failed to get bridge info from DT\n"); + DRM_ERROR("Failed to get bridge info from DT\n"); return ERR_PTR(-EINVAL); }

@@ -365,7 +344,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) bridge = of_drm_find_bridge(encoder_node); of_node_put(encoder_node); if (!bridge) { - DRM_INFO("wait for external bridge driver DT\n"); + DRM_INFO("Wait for external bridge driver DT\n"); return ERR_PTR(-EPROBE_DEFER); } #endif @@ -373,21 +352,21 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) }

u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { - struct mipi_data_type_params data_type_parameters; + struct mipi_data_type_params data_type_param;

switch (data_type) { case DSI_LP_DT_PPS_YCBCR420_12B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 3; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 3; switch (data_mode) { - /* case 0 not supported according to MDK */ + /* Case 0 not supported according to MDK */ case 1: case 2: case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 24; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -395,17 +374,19 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_YCBCR422_16B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 4; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 4; switch (data_mode) { - /* case 0 and 1 not supported according to MDK */ + /* Case 0 and 1 not supported according + * to MDK + */ case 2: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 16; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 16; break; case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 32; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 32; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -414,15 +395,15 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, break; case DSI_LP_DT_LPPS_YCBCR422_20B: case DSI_LP_DT_PPS_YCBCR422_24B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 6; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 6; switch (data_mode) { - /* case 0 not supported according to MDK */ + /* Case 0 not supported according to MDK */ case 1: case 2: case 3: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 24; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -430,18 +411,18 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_RGB565_16B: - data_type_parameters.size_constraint_pixels = 1; - data_type_parameters.size_constraint_bytes = 2; + data_type_param.size_constraint_pixels = 1; + data_type_param.size_constraint_bytes = 2; switch (data_mode) { case 0: case 1: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 16; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 16; break; case 2: case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 32; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 32; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -449,97 +430,104 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_RGB666_18B: - data_type_parameters.size_constraint_pixels = 4; - data_type_parameters.size_constraint_bytes = 9; - data_type_parameters.bits_per_pclk = 18; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 4; + data_type_param.size_constraint_bytes = 9; + data_type_param.bits_per_pclk = 18; + data_type_param.pixels_per_pclk = 1; break; case DSI_LP_DT_LPPS_RGB666_18B: case DSI_LP_DT_PPS_RGB888_24B: - data_type_parameters.size_constraint_pixels = 1; - data_type_parameters.size_constraint_bytes = 3; - data_type_parameters.bits_per_pclk = 24; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 1; + data_type_param.size_constraint_bytes = 3; + data_type_param.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 1; break; case DSI_LP_DT_PPS_RGB101010_30B: - data_type_parameters.size_constraint_pixels = 4; - data_type_parameters.size_constraint_bytes = 15; - data_type_parameters.bits_per_pclk = 30; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 4; + data_type_param.size_constraint_bytes = 15; + data_type_param.bits_per_pclk = 30; + data_type_param.pixels_per_pclk = 1; break; - default: DRM_ERROR("DSI: Invalid data_type %d\n", data_type); return -EINVAL; - } + };

- *params = data_type_parameters; + *params = data_type_param; return 0; }

static u32 compute_wc(u32 width_px, u8 size_constr_p, u8 size_constr_b) { - /* calculate the word count for each long packet */ + /* Calculate the word count for each long packet */ return (((width_px / size_constr_p) * size_constr_b) & 0xffff); }

static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) { - /*number of PCLK cycles needed to transfer a line */ - /* with each PCLK cycle, 4 Bytes are sent through the PPL module */ + /* Number of PCLK cycles needed to transfer a line + * with each PCLK cycle, 4 Bytes are sent through the PPL module + */ return ((wc * 8) / bits_per_pclk) * 4; }

static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_id, - u8 section, u32 height_lines, - u32 unpacked_bytes, + u8 frame_id, u8 section, + u32 height_lines, u32 unpacked_bytes, struct mipi_tx_frame_sect_phcfg *ph_cfg) { u32 cfg = 0; u32 ctrl_no = MIPI_CTRL6; u32 reg_adr;

- /*frame section packet header */ - /*word count */ - cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ - /*data type */ + /* Frame section packet header */ + /* Word count bits [15:0] */ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; + + /* Data type (bits [21:16]) */ cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) - << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ - /* virtual channel */ + << MIPI_TX_SECT_DT_SHIFT); + + /* Virtual channel (bits [23:22]) */ cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK) - << MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */ - /* data mode */ + << MIPI_TX_SECT_VC_SHIFT); + + /* Data mode (bits [24:25]) */ cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) - << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25]*/ + << MIPI_TX_SECT_DM_SHIFT); if (ph_cfg->dma_packed) cfg |= MIPI_TX_SECT_DMA_PACKED; - DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg, - ph_cfg->dma_packed); - kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); - - /*unpacked bytes */ - /*there are 4 frame generators and each fg has 4 sections - *there are 2 registers for unpacked bytes - - *# bytes each section occupies in memory - *REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 - *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 + + DRM_DEBUG("ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", + ctrl_no, frame_id, section, cfg, ph_cfg->dma_packed); + kmb_write_mipi(dev_p, + (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), + cfg); + + /* Unpacked bytes */ + + /* There are 4 frame generators and each fg has 4 sections + * There are 2 registers for unpacked bytes (# bytes each + * section occupies in memory) + * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 + * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ - reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section / 2) * 4; + reg_adr = + MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, + frame_id) + (section / 2) * 4; kmb_write_bits_mipi(dev_p, reg_adr, (section % 2) * 16, 16, unpacked_bytes); + DRM_DEBUG("unpacked_bytes = %d, wordcount = %d\n", unpacked_bytes, + ph_cfg->wc);

- /* line config */ + /* Line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); kmb_write_mipi(dev_p, reg_adr, height_lines); return 0; }

-static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, - u8 section, +static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, + u8 frame_id, u8 section, struct mipi_tx_frame_section_cfg *frame_scfg, u32 *bits_per_pclk, u32 *wc) { @@ -553,8 +541,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, &data_type_parameters); if (ret) return ret; - /* - * packet width has to be a multiple of the minimum packet width + + /* Packet width has to be a multiple of the minimum packet width * (in pixels) set for each data type */ if (frame_scfg->width_pixels % @@ -564,10 +552,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, *wc = compute_wc(frame_scfg->width_pixels, data_type_parameters.size_constraint_pixels, data_type_parameters.size_constraint_bytes); - - unpacked_bytes = - compute_unpacked_bytes(*wc, data_type_parameters.bits_per_pclk); - + unpacked_bytes = compute_unpacked_bytes(*wc, + data_type_parameters.bits_per_pclk); ph_cfg.wc = *wc; ph_cfg.data_mode = frame_scfg->data_mode; ph_cfg.data_type = frame_scfg->data_type; @@ -578,88 +564,94 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, frame_scfg->height_lines, unpacked_bytes, &ph_cfg);

- /*caller needs bits_per_clk for additional caluclations */ + /* Caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; + return 0; }

-static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_gen, +static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) { u32 sysclk; - /*float ppl_llp_ratio; */ u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;

- /*Get system clock for blanking period cnfigurations */ - /*TODO need to get system clock from clock driver */ - /* 500 Mhz system clock minus 50 - to account for the difference in - * mipi clock speed in RTL tests +#ifdef GET_SYS_CLK + /* Get system clock for blanking period cnfigurations */ + sc = get_clock_frequency(CPR_CLK_SYSTEM, &sysclk); + if (sc) + return sc; + + /* Convert to MHZ */ + sysclk /= 1000; +#else + /* 500 Mhz system clock minus 50 to account for the difference in + * MIPI clock speed in RTL tests */ sysclk = KMB_SYS_CLK_MHZ - 50; -// sysclk = KMB_SYS_CLK_MHZ; +#endif

- /*ppl-pixel packing layer, llp-low level protocol - * frame genartor timing parameters are clocked on the system clock + /* PPL-Pixel Packing Layer, LLP-Low Level Protocol + * Frame genartor timing parameters are clocked on the system clock, * whereas as the equivalent parameters in the LLP blocks are clocked * on LLP Tx clock from the D-PHY - BYTE clock */

- /*multiply by 1000 to keep the precision */ + /* Multiply by 1000 to maintain precision */ ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);

- DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", - __func__, __LINE__, fg_cfg->bpp, sysclk, - fg_cfg->lane_rate_mbps, fg_cfg->active_lanes); + DRM_INFO("ppl_llp_ratio=%d\n", ppl_llp_ratio); + DRM_INFO("bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", + fg_cfg->bpp, sysclk, fg_cfg->lane_rate_mbps, + fg_cfg->active_lanes);

- DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__, - ppl_llp_ratio); - /*frame generator number of lines*/ + /* Frame generator number of lines */ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active);

- /*vsync width */ - /* - *there are 2 registers for vsync width -VSA in lines for channels 0-3 - *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 - *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 + /* vsync width + * There are 2 registers for vsync width (VSA in lines for + * channels 0-3) + * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 + * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ offset = (frame_gen % 2) * 16; reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->vsync_width);

- /*v backporch - same register config like vsync width */ + /* vertical backporch (vbp) */ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_backporch);

- /*v frontporch - same register config like vsync width */ + /* vertical frontporch (vfp) */ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_frontporch);

- /*v active - same register config like vsync width */ + /* vertical active (vactive) */ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_active);

- /*hsyc width */ + /* hsync width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->hsync_width * ppl_llp_ratio) / 1000);

- /*h backporch */ + /* horizontal backporch (hbp) */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->h_backporch * ppl_llp_ratio) / 1000);

- /*h frontporch */ + /* horizontal frontporch (hfp) */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000);

- /*h active */ + /* horizontal active (ha) */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); - /*convert h_active which is wc in bytes to cycles */ + + /* convert h_active which is wc in bytes to cycles */ val = (fg_cfg->h_active * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); val /= 1000; @@ -686,8 +678,8 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, u32 i, fg_num_lines = 0; struct mipi_tx_frame_timing_cfg fg_t_cfg;

- /*calculate the total frame generator number of lines based on it's - * active sections + /* Calculate the total frame generator number of + * lines based on it's active sections */ for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) { if (fg_cfg->sections[i] != NULL) @@ -706,7 +698,7 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, fg_t_cfg.v_active = fg_num_lines; fg_t_cfg.active_lanes = active_lanes;

- /*apply frame generator timing setting */ + /* Apply frame generator timing setting */ mipi_tx_fg_cfg_regs(dev_p, frame_gen, &fg_t_cfg); }

@@ -716,7 +708,7 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6;

- /*clear all mc fifo channel sizes and thresholds */ + /* Clear all mc fifo channel sizes and thresholds */ kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); @@ -726,18 +718,18 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ? MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; - /*MC fifo size for virtual channels 0-3 */ - /* - *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 - *REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 + + /* MC fifo size for virtual channels 0-3 + * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 + * REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 */ SET_MC_FIFO_CHAN_ALLOC(dev_p, ctrl_no, vchannel_id, fifo_size);

- /*set threshold to half the fifo size, actual size=size*16 */ + /* Set threshold to half the fifo size, actual size=size*16 */ fifo_rthreshold = ((fifo_size) * 8) & BIT_MASK_16; SET_MC_FIFO_RTHRESHOLD(dev_p, ctrl_no, vchannel_id, fifo_rthreshold);

- /*enable the MC FIFO channel corresponding to the Virtual Channel */ + /* Enable the MC FIFO channel corresponding to the Virtual Channel */ kmb_set_bit_mipi(dev_p, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); } @@ -748,7 +740,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6;

- /*MIPI_TX_HS_SYNC_CFG */ + /* MIPI_TX_HS_SYNC_CFG */ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -769,22 +761,29 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= DSI_LPM_FIRST_VSA_LINE; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) sync_cfg |= DSI_LPM_LAST_VFP_LINE; - /* enable frame generator */ + + /* Enable frame generator */ fg_en = 1 << fg_id; sync_cfg |= FRAME_GEN_EN(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) sync_cfg |= ALWAYS_USE_HACT(fg_en); if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) sync_cfg |= HACT_WAIT_STOP(fg_en);

- /* MIPI_TX_HS_CTRL*/ - ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + DRM_DEBUG("sync_cfg=%d fg_en=%d\n", sync_cfg, fg_en); + + /* MIPI_TX_HS_CTRL */ + + /* type:DSI, source:LCD */ + ctrl = HS_CTRL_EN | TX_SOURCE; + ctrl |= LCD_VC(fg_id); + ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) ctrl |= DSI_CMD_HFP_EN; - ctrl |= LCD_VC(fg_id); - ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); + /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43);

@@ -798,14 +797,10 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, u32 color1, u32 ctrl_no) { int val = 0; + /* Select test pattern mode on the virtual channel */ val = TP_SEL_VCm(vc, tp_sel);

- if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || - tp_sel == MIPI_TX_HS_TP_H_STRIPES) { - val |= TP_STRIPE_WIDTH(stripe_width); - } - /* Configure test pattern colors */ kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR0(ctrl_no), color0); kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR1(ctrl_no), color1); @@ -813,6 +808,7 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, /* Enable test pattern generation on the virtual channel */ val |= TP_EN_VCm(vc); kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), val); + } #endif

@@ -824,31 +820,33 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, u8 frame_id, sect; u32 bits_per_pclk = 0; u32 word_count = 0; - - /*This is the order in which mipi tx needs to be initialized - * set frame section parameters - * set frame specific parameters - * connect lcd to mipi - * multi channel fifo cfg - * set mipitxcctrlcfg + struct mipi_tx_frame_cfg *frame; + + /* This is the order to initialize MIPI TX: + * 1. set frame section parameters + * 2. set frame specific parameters + * 3. connect lcd to mipi + * 4. multi channel fifo cfg + * 5. set mipitxcctrlcfg */

for (frame_id = 0; frame_id < 4; frame_id++) { - /* find valid frame, assume only one valid frame */ - if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) + frame = ctrl_cfg->tx_ctrl_cfg.frames[frame_id]; + + /* Find valid frame, assume only one valid frame */ + if (frame == NULL) continue;

/* Frame Section configuration */ - /*TODO - assume there is only one valid section in a frame, so - * bits_per_pclk and word_count are only set once + /* TODO - assume there is only one valid section in a frame, + * so bits_per_pclk and word_count are only set once */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { - if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + if (frame->sections[sect] == NULL) continue;

ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + frame->sections[sect], &bits_per_pclk, &word_count); if (ret) @@ -856,30 +854,39 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,

}

- /* set frame specific parameters */ + /* Set frame specific parameters */ mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, word_count, + ctrl_cfg->lane_rate_mbps, frame);

active_vchannels++;

- /*stop iterating as only one virtual channel shall be used for - * LCD connection + /* Stop iterating as only one virtual channel + * shall be used for LCD connection */ break; }

if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration */ + /* Multi-Channel FIFO Configuration */ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id);

- /*Frame Generator Enable */ + /* Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); + +#ifdef MIPI_TX_TEST_PATTERN_GENERATION + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x8, 0xff, 0xff00, MIPI_CTRL6); +#endif + + DRM_DEBUG("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + return ret; }

+#ifdef DPHY_READ_TESTCODE int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, int test_code) { @@ -894,17 +901,17 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, reg_wr_data = 0; reg_rd_data = 0;

- if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24;

if ((dphy_sel >> 0 & 0xf) > 0) @@ -927,17 +934,18 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel,

data = test_code >> 8 & 0xf; reg_wr_data = 0; - if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24;

if ((dphy_sel >> 0 & 0xf) > 0) @@ -953,17 +961,18 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel,

data = test_code & 0xff; reg_wr_data = 0; - if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24;

if ((dphy_sel >> 0 & 0xf) > 0) @@ -1005,20 +1014,16 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, data = reg_rd_data >> 24;

return data; - } +#endif

static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, u32 test_code, u32 test_data) { -#ifdef DEBUG if (test_code != TEST_CODE_FSM_CONTROL) - DRM_INFO("test_code = %02x, test_data = %08x\n", test_code, + DRM_DEBUG("test_code = %02x, test_data = %08x\n", test_code, test_data); -#endif - - /* send the test code first */ - /* Steps for code: + /* Steps to send test code: * - set testclk HIGH * - set testdin with test code * - set testen HIGH @@ -1041,14 +1046,14 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no);

- /* Send the test data next */ - /* Steps for data: - * - set testen LOW - * - set testclk LOW - * - set testdin with data - * - set testclk HIGH - */ if (test_code) { + /* Steps to send test data: + * - set testen LOW + * - set testclk LOW + * - set testdin with data + * - set testclk HIGH + */ + /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no);

@@ -1065,59 +1070,36 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, } }

-static inline void - set_test_mode_src_osc_freq_target_low_bits(struct kmb_drm_private +static inline void set_test_mode_src_osc_freq_target_low_bits(struct + kmb_drm_private *dev_p, u32 dphy_no, u32 freq) { - /*typical rise/fall time=166, - * refer Table 1207 databook,sr_osc_freq_target[7:0 + /* Typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[7:0] */ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); -} - -static inline void -set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, u32 dphy_no) -{ - /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ - test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - (0x03 | (1 << 6))); + test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, + (freq & 0x7f)); }

-static inline void -set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, - u32 dphy_no, u32 freq) +static inline void set_test_mode_src_osc_freq_target_hi_bits(struct + kmb_drm_private + *dev_p, + u32 dphy_no, + u32 freq) { u32 data; - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[11:7 + + /* Flag this as high nibble */ + data = ((freq >> 6) & 0x1f) | (1 << 7); + + /* Typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[11:7] */ - data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); }

-struct vco_params { - u32 freq; - u32 range; - u32 divider; -}; - -static struct vco_params vco_table[] = { - {52, 0x3f, 8}, - {80, 0x39, 8}, - {105, 0x2f, 4}, - {160, 0x29, 4}, - {210, 0x1f, 2}, - {320, 0x19, 2}, - {420, 0x0f, 1}, - {630, 0x09, 1}, - {1100, 0x03, 1}, - {0xffff, 0x01, 1}, -}; - static void mipi_tx_get_vco_params(struct vco_params *vco) { int i; @@ -1128,12 +1110,17 @@ static void mipi_tx_get_vco_params(struct vco_params *vco) return; } } + WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); }

static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) { + u32 best_n = 0, best_m = 0; + u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; + u32 best_freq_delta = 3000; + /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) @@ -1151,35 +1138,37 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, .range = 0, .divider = 1, }; - u32 best_n = 0, best_m = 0; - u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; - u32 best_freq_delta = 3000;

vco_p.freq = target_freq_mhz; mipi_tx_get_vco_params(&vco_p); - /*search pll n parameter */ + + /* Search pll n parameter */ for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) { - /*calculate the pll input frequency division ratio + /* Calculate the pll input frequency division ratio * multiply by 1000 for precision - * no floating point, add n for rounding */ div = ((ref_clk_mhz * 1000) + n) / (n + 1); - /*found a valid n parameter */ + + /* Found a valid n parameter */ if ((div < 2000 || div > 8000)) continue; - /*search pll m parameter */ + + /* Search pll m parameter */ for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) { - /*calculate the Fvco(DPHY PLL output frequency) + /* Calculate the Fvco(DPHY PLL output frequency) * using the current n,m params */ freq = div * (m + 2); freq /= 1000; - /* trim the potential pll freq to max supported */ + + /* Trim the potential pll freq to max supported */ if (freq > PLL_FVCO_MAX) continue;

delta = abs(freq - target_freq_mhz); - /*select the best (closest to target pll freq) + + /* Select the best (closest to target pll freq) * n,m parameters so far */ if (delta < best_freq_delta) { @@ -1190,212 +1179,235 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, } }

- /*Program vco_cntrl parameter - *PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, + /* Program vco_cntrl parameter + * PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range | (1 << 6)));

- /*Program m, n pll parameters */ - - DRM_INFO("%s : %d m = %d n = %d\n", __func__, __LINE__, best_m, best_n); + /* Program m, n pll parameters */ + DRM_INFO("m = %d n = %d\n", best_m, best_n);

- /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ + /* PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, (best_n & 0x0f));

- /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ + /* m - low nibble PLL_Loop_Divider_Ratio[4:0] + * pll_m_ovr[4:0] + */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, (best_m & 0x1f));

- /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ + /* m - high nibble PLL_Loop_Divider_Ratio[4:0] + * pll_m_ovr[9:5] + */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH);

- /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ + /* Enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, (PLL_N_OVR_EN | PLL_M_OVR_EN));

- /*Program Charge-Pump parameters */ + /* Program Charge-Pump parameters */

- /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ + /* pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ t_freq = target_freq_mhz * vco_p.divider; test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, ((t_freq > 1150) ? 0x0C : 0x0B));

- /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ + /* pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, 0x00);

- /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ + /* pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10);

- /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ + /* pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10);

- /*pll_th1 -Lock Detector Phase error threshold, document gives fixed - * value + /* pll_th1 -Lock Detector Phase error threshold, + * document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02);

- /*PLL Lock Configuration */ + /* PLL Lock Configuration */

- /*pll_th2 - Lock Filter length, document gives fixed value */ + /* pll_th2 - Lock Filter length, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60);

- /*pll_th3- PLL Unlocking filter, document gives fixed value */ + /* pll_th3- PLL Unlocking filter, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03);

- /*pll_lock_sel-PLL Lock Detector Selection, document gives - * fixed value + /* pll_lock_sel-PLL Lock Detector Selection, + * document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); }

+#ifdef DPHY_GET_FSM +static void dphy_get_fsm(struct kmb_drm_private *dev_p, u32 dphy_no) +{ + test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); + + DRM_INFO("dphy %d fsm_state = 0%x\n", dphy_no, + kmb_read_mipi(dev_p, DPHY_TEST_DOUT4_7)); +} +#endif + static void dphy_init_sequence(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *cfg, u32 dphy_no, int active_lanes, enum dphy_mode mode) { - u32 test_code = 0; - u32 test_data = 0, val; + u32 test_code = 0, test_data = 0, val; int i = 0;

- /* deassert SHUTDOWNZ signal */ - DRM_INFO("%s : %d MIPI_DPHY_STAT0_4_7 = 0x%x)\n", __func__, __LINE__, - kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); - /*Set D-PHY in shutdown mode */ - /*assert RSTZ signal */ + DRM_INFO("dphy=%d mode=%d active_lanes=%d\n", dphy_no, mode, + active_lanes); + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + + /* Set D-PHY in shutdown mode */ + /* Assert RSTZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - /* assert SHUTDOWNZ signal */ + + /* Assert SHUTDOWNZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); - DRM_INFO("%s : %d DPHY_INIT_CTRL0 = 0x%x\n", __func__, __LINE__, val);

- /*Init D-PHY_n */ - /*Pulse testclear signal to make sure the d-phy configuration starts - * from a clean base + DRM_INFO("DPHY_INIT_CTRL0 = 0x%x\n", val); + + /* Init D-PHY_n + * Pulse testclear signal to make sure the d-phy configuration + * starts from a clean base */ CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); ndelay(15); SET_DPHY_TEST_CTRL0(dev_p, dphy_no); - /*TODO may need to add 15ns delay here */ ndelay(15); CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); - val = kmb_read_mipi(dev_p, DPHY_TEST_CTRL0); - DRM_INFO("%s : %d DPHY_TEST_CTRL0 = 0x%x\n", __func__, __LINE__, val); ndelay(15);

- /*Set mastermacro bit - Master or slave mode */ + DRM_DEBUG("DPHY_TEST_CTRL0=0x%x\n", + kmb_read_mipi(dev_p, DPHY_TEST_CTRL0)); + + /* Set mastermacro bit - Master or slave mode */ test_code = TEST_CODE_MULTIPLE_PHY_CTRL; - /*DPHY has its own clock lane enabled (master) */ + + /* DPHY has its own clock lane enabled (master) */ if (mode == MIPI_DPHY_MASTER) test_data = 0x01; else test_data = 0x00;

- /*send the test code and data */ + /* Send the test code and data */ test_mode_send(dev_p, dphy_no, test_code, test_data); - /*Set the lane data rate */ + + /* Set the lane data rate */ for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { if (mipi_hs_freq_range[i].default_bit_rate_mbps < cfg->lane_rate_mbps) continue; - /* send the test code and data */ - /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ + + /* Send the test code and data */ + /* bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ test_code = TEST_CODE_HS_FREQ_RANGE_CFG; - test_data = - (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | (1 << 7); + test_data = (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | + (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data); break; } - /* - * High-Speed Tx Slew Rate Calibration + + /* High-Speed Tx Slew Rate Calibration * BitRate: > 1.5 Gbps && <= 2.5 Gbps: slew rate control OFF */ if (cfg->lane_rate_mbps > 1500) { - /*bypass slew rate calibration algorithm */ - /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ + /* Bypass slew rate calibration algorithm + * bits[1:0} srcal_en_ovr_en, srcal_en_ovr + */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = 0x02; test_mode_send(dev_p, dphy_no, test_code, test_data);

- /* disable slew rate calibration */ + /* Disable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x00; test_mode_send(dev_p, dphy_no, test_code, test_data); } else if (cfg->lane_rate_mbps > 1000) { - /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON + /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON * typical rise/fall times: 166 ps */

- /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ + /* Do not bypass slew rate calibration algorithm + * bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range + */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = (0x03 | (1 << 6)); test_mode_send(dev_p, dphy_no, test_code, test_data);

-// set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - - /* enable slew rate calibration */ + /* Enable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x01; test_mode_send(dev_p, dphy_no, test_code, test_data);

- /*set sr_osc_freq_target[6:0] */ - /*typical rise/fall time=166, refer Table 1207 databook */ - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[7:0 + /* Set sr_osc_freq_target[6:0] low nibble + * typical rise/fall time=166, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; test_data = (0x72f & 0x7f); test_mode_send(dev_p, dphy_no, test_code, test_data); - /*set sr_osc_freq_target[11:7] */ - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[11:7 + + /* Set sr_osc_freq_target[11:7] high nibble + * Typical rise/fall time=166, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; - /*flag this as high nibble */ test_data = ((0x72f >> 6) & 0x1f) | (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data); } else { - /*lane_rate_mbps <= 1000 Mbps */ - /*BitRate: <= 1 Gbps: + /* lane_rate_mbps <= 1000 Mbps + * BitRate: <= 1 Gbps: * - slew rate control ON * - typical rise/fall times: 225 ps */

- /*do not bypass slew rate calibration algorithm */ + /* Do not bypass slew rate calibration algorithm */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = (0x03 | (1 << 6)); test_mode_send(dev_p, dphy_no, test_code, test_data);

- /* enable slew rate calibration */ + /* Enable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x01; test_mode_send(dev_p, dphy_no, test_code, test_data);

- /*typical rise/fall time=255, refer Table 1207 databook */ + /* Typical rise/fall time=255, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; test_data = (0x523 & 0x7f); test_mode_send(dev_p, dphy_no, test_code, test_data);

- /*set sr_osc_freq_target[11:7] */ + /* Set sr_osc_freq_target[11:7] high nibble */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; - /*flag this as high nibble */ test_data = ((0x523 >> 6) & 0x1f) | (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data);

} - /*Set cfgclkfreqrange */ + + /* Set cfgclkfreqrange */ val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; SET_DPHY_FREQ_CTRL0_3(dev_p, dphy_no, val); - val = kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4);

- /*Enable config clk for the corresponding d-phy */ + DRM_INFO("DPHY_FREQ = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4)); + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + + /* Enable config clk for the corresponding d-phy */ kmb_set_bit_mipi(dev_p, DPHY_CFG_CLK_EN, dphy_no); - val = kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN); + + DRM_INFO("DPHY_CFG_CLK_EN = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN)); + /* PLL setup */ if (mode == MIPI_DPHY_MASTER) { /*Set PLL regulator in bypass */ @@ -1407,16 +1419,21 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz / 1000, cfg->lane_rate_mbps / 2);

- /*Set clksel */ - kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, - 2, 0x01); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); + /* Set clksel */ + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, + PLL_CLKSEL_0, 2, 0x01);

- /*Set pll_shadow_control */ + /* Set pll_shadow_control */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); + + DRM_INFO("DPHY_INIT_CTRL1 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL1)); } -#define MIPI_TX_FORCE_VOD + + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + +//#define MIPI_TX_FORCE_VOD #ifdef MIPI_TX_FORCE_VOD #define MIPI_TX_VOD_LVL 450 #define TEST_CODE_BANDGAP 0x24 @@ -1454,31 +1471,39 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, * bits[5:0] - BaseDir: 1 = Rx * bits[9:6] - BaseDir: 0 = Tx */ + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL2, 0, 9, 0x03f); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); ndelay(15);

- /* Enable CLOCK LANE - */ - /*clock lane should be enabled regardless of the direction set for - * the D-PHY (Rx/Tx) + /* Enable CLOCK LANE + * Clock lane should be enabled regardless of the direction + * set for the D-PHY (Rx/Tx) */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2);

- /* enable DATA LANES */ + DRM_INFO("DPHY_INIT_CTRL2 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL2)); + + /* Enable DATA LANES */ kmb_write_bits_mipi(dev_p, DPHY_ENABLE, dphy_no * 2, 2, ((1 << active_lanes) - 1));

- val = kmb_read_mipi(dev_p, DPHY_ENABLE); + DRM_INFO("DPHY_ENABLE = 0x%x\n", kmb_read_mipi(dev_p, DPHY_ENABLE)); ndelay(15); - /*Take D-PHY out of shutdown mode */ - /* deassert SHUTDOWNZ signal */ + + /* Take D-PHY out of shutdown mode */ + /* Deassert SHUTDOWNZ signal */ + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); SET_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); ndelay(15);

- /*deassert RSTZ signal */ + /* Deassert RSTZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); + DRM_INFO("DPHY_INIT_CTRL0 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL0)); }

static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, @@ -1490,76 +1515,87 @@ static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no,

do { test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); - /*TODO-need to add a time out and return failure */ + + /* TODO - need to add a time out and return failure */ val = GET_TEST_DOUT4_7(dev_p, dphy_no); i++; if (i > TIMEOUT) { status = 0; - DRM_INFO("%s: timing out fsm_state = %x GET_TEST_DOUT4_7 = %x", - __func__, fsm_state, kmb_read_mipi(dev_p, - DPHY_TEST_DOUT4_7)); break; } } while (val != fsm_state); - DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val);

DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); DRM_INFO("********** DPHY %d WAIT_FSM %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); }

-static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 active_lanes) +static void wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, + u32 active_lanes) { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; int i = 0, val; int status = 1;

- DRM_INFO("%s : %d dphy = %d active_lanes=%d data_lanes=%d\n", - __func__, __LINE__, dphy_no, active_lanes, data_lanes); + DRM_INFO("dphy=%d active_lanes=%d data_lanes=%d\n", dphy_no, + active_lanes, data_lanes);

do { val = kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7); stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no) & data_lanes; + + /* TODO-need to add a time out and return failure */ i++; + if (i > TIMEOUT) { status = 0; - DRM_INFO("!WAIT_INIT_DONE: TIMING OUT! (err_stat=%d)n", + + DRM_INFO("! WAIT_INIT_DONE: TIMING OUT!(err_stat=%d)", kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", val); + DRM_INFO("stopdata = 0x%x data_lanes=0x%x\n", + stopstatedata, data_lanes); + break; } -// udelay(1); + + if (i < 3) { + DRM_INFO("stopdata = 0x%x data_lanes=0x%x\n", + stopstatedata, data_lanes); + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", val); + } } while (stopstatedata != data_lanes);

DRM_INFO("********** DPHY %d INIT - %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); - - return 0; }

-static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) +static void wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { int i = 0; int status = 1;

do { - /*TODO-need to add a time out and return failure */ + /* TODO-need to add a time out and return failure */ i++; - // udelay(1); if (i > TIMEOUT) { status = 0; + DRM_INFO("%s: timing out", __func__); - DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + DRM_INFO("%s : PLL_LOCK = 0x%x ", __func__, kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); + break; }

+ if ((i % 100) == 0) + DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); } while (!GET_PLL_LOCK(dev_p, dphy_no));

DRM_INFO("********** PLL Locked for DPHY %d - %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); - return 0; }

static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, @@ -1567,10 +1603,10 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, { u32 dphy_no = MIPI_DPHY6;

- DRM_INFO("%s : %d active_lanes=%d lane_rate=%d\n", - __func__, __LINE__, cfg->active_lanes, + DRM_INFO("active_lanes=%d lane_rate=%d\n", cfg->active_lanes, MIPI_TX_LANE_DATA_RATE_MBPS); - /*multiple D-PHYs needed */ + + /* Multiple D-PHYs needed */ if (cfg->active_lanes > MIPI_DPHY_D_LANES) { /* *Initialization for Tx aggregation mode is done according to @@ -1594,16 +1630,16 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, MIPI_DPHY_SLAVE); dphy_wait_fsm(dev_p, dphy_no + 1, DPHY_TX_LOCK);

- /*PHY #N master */ + /* PHY #N master */ dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_D_LANES, MIPI_DPHY_MASTER); - /* wait for DPHY init to complete */ + + /* Wait for DPHY init to complete */ wait_init_done(dev_p, dphy_no, MIPI_DPHY_D_LANES); wait_init_done(dev_p, dphy_no + 1, cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); -// udelay(1000); dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); } else { /* Single DPHY */ dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, @@ -1616,6 +1652,51 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, return 0; }

+#ifdef MIPI_TX_INIT_IRQS +static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, + union mipi_irq_cfg *cfg, + struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) +{ + unsigned long irqflags; + uint8_t vc; + + /* Clear all interrupts first */ + /* Local interrupts */ + SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); + + /* Global interrupts */ + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); + + /* Enable interrupts */ + spin_lock_irqsave(&dev_p->irq_lock, irqflags); + for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { + if (tx_ctrl_cfg->frames[vc] == NULL) + continue; + + /*enable FRAME_DONE interrupt if VC is configured */ + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); + + /* Only one vc for LCD interface */ + break; + } + + /* Eenable user enabled interrupts */ + if (cfg->irq_cfg.dphy_error) + SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); + if (cfg->irq_cfg.line_compare) + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + MIPI_TX_HS_IRQ_LINE_COMPARE); + if (cfg->irq_cfg.ctrl_error) + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); + + spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); +} +#endif + +#ifdef MIPI_TX_HANDLE_IRQS void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) { uint32_t irq_ctrl_stat_0, hs_stat, hs_enable; @@ -1623,7 +1704,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p)

irq_ctrl_stat_0 = MIPI_GET_IRQ_STAT0(dev_p); irq_ctrl_enabled_0 = MIPI_GET_IRQ_ENABLED0(dev_p); - /*only service enabled interrupts */ + + /* Only service enabled interrupts */ irq_ctrl_stat_0 &= irq_ctrl_enabled_0;

if (irq_ctrl_stat_0 & MIPI_DPHY_ERR_MASK) { @@ -1634,7 +1716,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) hs_stat = GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6); hs_enable = GET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6); hs_stat &= hs_enable; - /*look for errors */ + + /* Check for errors */ if (hs_stat & MIPI_TX_HS_IRQ_ERROR) { CLR_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, (hs_stat & MIPI_TX_HS_IRQ_ERROR) | @@ -1647,43 +1730,21 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) }

} +#endif

+#ifdef LCD_TEST void connect_lcd_to_mipi(struct kmb_drm_private *dev_p) { -#ifdef LCD_TEST - /*connect lcd to mipi */ - /*DISABLE MIPI->CIF CONNECTION*/ + /* DISABLE MIPI->CIF CONNECTION */ kmb_write_msscam(dev_p, MSS_MIPI_CIF_CFG, 0); - /*ENABLE LCD->MIPI CONNECTION */ - kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); - /*DISABLE LCD->CIF LOOPBACK */ - kmb_write_msscam(dev_p, MSS_LOOPBACK_CFG, 0); -#endif -} - -/** - * Reads specified number of bytes from the file. - * - * @param file - file structure. - * @param offset - offset in the file. - * @param addr - address of the buffer. - * @param count - size of the buffer . - * - * @return 0 if success or error code. - */ -int kmb_kernel_read(struct file *file, loff_t offset, - char *addr, unsigned long count) -{ - char __user *buf = (char __user *)addr; - ssize_t ret;

- if (!(file->f_mode & FMODE_READ)) - return -EBADF; - - ret = kernel_read(file, buf, count, &offset); + /* ENABLE LCD->MIPI CONNECTION */ + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);

- return ret; + /* DISABLE LCD->CIF LOOPBACK */ + kmb_write_msscam(dev_p, MSS_LOOPBACK_CFG, 0); } +#endif

int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) { @@ -1691,35 +1752,39 @@ int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) u64 data_rate;

mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES; + if (mode != NULL) { mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; mipitx_frame0_cfg.vsync_width = - mode->crtc_vsync_end - mode->crtc_vsync_start; + mode->crtc_vsync_end - mode->crtc_vsync_start; mipitx_frame0_cfg.v_backporch = - mode->crtc_vtotal - mode->crtc_vsync_end; + mode->crtc_vtotal - mode->crtc_vsync_end; mipitx_frame0_cfg.v_frontporch = - mode->crtc_vsync_start - mode->crtc_vdisplay; + mode->crtc_vsync_start - mode->crtc_vdisplay; mipitx_frame0_cfg.hsync_width = - mode->crtc_hsync_end - mode->crtc_hsync_start; + mode->crtc_hsync_end - mode->crtc_hsync_start; mipitx_frame0_cfg.h_backporch = - mode->crtc_htotal - mode->crtc_hsync_end; + mode->crtc_htotal - mode->crtc_hsync_end; mipitx_frame0_cfg.h_frontporch = - mode->crtc_hsync_start - mode->crtc_hdisplay; - /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 + mode->crtc_hsync_start - mode->crtc_hdisplay; + + /* Lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 * to convert to Mbps */ - DRM_INFO("htotal = %d vtotal=%d refresh=%d\n", - mode->crtc_htotal, mode->crtc_vtotal, - drm_mode_vrefresh(mode)); - data_rate = - ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) - * (u32)(drm_mode_vrefresh(mode)) - * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000; - DRM_INFO("data_rate = %llu active_lanes=%d\n", - data_rate, mipi_tx_init_cfg.active_lanes); - - /*when late rate < 800 - modeset fails with 4 lanes - + data_rate = ((((u32) mode->crtc_vtotal * + (u32) mode->crtc_htotal) * + (u32)(drm_mode_vrefresh(mode)) * + MIPI_TX_BPP) / mipi_tx_init_cfg.active_lanes) / + 1000000; + + DRM_INFO("htotal=%d vtotal=%d refresh=%d\n", + mode->crtc_htotal, mode->crtc_vtotal, + drm_mode_vrefresh(mode)); + DRM_INFO("data_rate=%u active_lanes=%d\n", + (u32) data_rate, mipi_tx_init_cfg.active_lanes); + + /* When late rate < 800, modeset fails with 4 lanes, * so switch to 2 lanes */ if (data_rate < 800) { @@ -1729,36 +1794,62 @@ int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) mipi_tx_init_cfg.lane_rate_mbps = data_rate; } DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps); - DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n", - mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch, - mipitx_frame0_cfg.vsync_width, - mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch, - mipitx_frame0_cfg.hsync_width, - mipi_tx_init_cfg.lane_rate_mbps); + DRM_INFO + ("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d", + mipitx_frame0_cfg.v_frontporch, + mipitx_frame0_cfg.v_backporch, + mipitx_frame0_cfg.vsync_width, + mipitx_frame0_cfg.h_frontporch, + mipitx_frame0_cfg.h_backporch, + mipitx_frame0_cfg.hsync_width, + mipi_tx_init_cfg.lane_rate_mbps);

} + if (hw_initialized) return 0; + kmb_write_mipi(dev_p, DPHY_ENABLE, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL2, 0);

- /* initialize mipi controller */ + /* Initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - /*d-phy initialization */ + + /* Dphy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + +#ifdef LCD_TEST connect_lcd_to_mipi(dev_p); +#endif + +#ifdef MIPI_TX_INIT_IRQS + /* IRQ initialization */ + mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); +#endif + #ifdef MIPI_TX_TEST_PATTERN_GENERATION - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff, - 0xff00, MIPI_CTRL6); - DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__, - GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x15, 0xff, 0xff00, MIPI_CTRL6); + + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); #endif //MIPI_TX_TEST_PATTERN_GENERATION

hw_initialized = true; - DRM_INFO("%s : %d mipi hw_initialized = %d\n", __func__, __LINE__, - hw_initialized); + + DRM_INFO("MIPI_TXm_HS_CTRL = 0x%x\n", + kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); + DRM_INFO("MIPI LOOP BACK = %x\n", + kmb_read_mipi(dev_p, MIPI_CTRL_DIG_LOOPBACK)); + DRM_INFO("mipi hw_initialized = %d\n", hw_initialized); + return 0; }

@@ -1777,7 +1868,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; }

- DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); @@ -1789,38 +1879,42 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge)

host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { - DRM_ERROR("Faile to allocate host\n"); + DRM_ERROR("Failed to allocate host\n"); kfree(kmb_dsi); kfree(kmb_connector); return -ENOMEM; } + kmb_dsi->dsi_host = host; connector = &kmb_connector->base; encoder = &kmb_dsi->base; encoder->possible_crtcs = 1; encoder->possible_clones = 0; + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI");

drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); + drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs);

- DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, - __LINE__, connector->name, encoder->name); + DRM_INFO("connector = %s encoder = %s\n", connector->name, + encoder->name);

ret = drm_connector_attach_encoder(connector, encoder); + DRM_INFO("connector->encoder = 0x%p ret = %d\n", connector->encoder, + ret);

- /* Link drm_bridge to encoder */ #ifndef FCCTEST + /* Link drm_bridge to encoder */ ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); drm_encoder_cleanup(encoder); return ret; } - - DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); + DRM_INFO("Bridge attached : SUCCESS\n"); #endif

#ifdef FCCTEST diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 7857576..d2beaf4 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -11,6 +11,60 @@ #include <drm/drm_modes.h> #include "kmb_drv.h"

+/* MIPI TX CFG*/ +#define MIPI_TX_LANE_DATA_RATE_MBPS 891 +#define MIPI_TX_REF_CLK_KHZ 24000 +#define MIPI_TX_CFG_CLK_KHZ 24000 +#define MIPI_TX_BPP 24 + +/* DPHY Tx test codes*/ +#define TEST_CODE_FSM_CONTROL 0x03 +#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C +#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E +#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F +#define TEST_CODE_PLL_VCO_CTRL 0x12 +#define TEST_CODE_PLL_GMP_CTRL 0x13 +#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 +#define TEST_CODE_PLL_LOCK_FILTER 0x15 +#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 +#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 +#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 +#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) +#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 +#define PLL_N_OVR_EN (1 << 4) +#define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_VOD_LEVEL 0x24 +#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C +#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D +#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 +#define TEST_CODE_PLL_ANALOG_PROG 0x1F +#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 +#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 +#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 + +/* DPHY params */ +#define PLL_N_MIN 0 +#define PLL_N_MAX 15 +#define PLL_M_MIN 62 +#define PLL_M_MAX 623 +#define PLL_FVCO_MAX 1250 + +#define TIMEOUT 600 + +#define MIPI_TX_FRAME_GEN 4 +#define MIPI_TX_FRAME_GEN_SECTIONS 4 +#define MIPI_CTRL_VIRTUAL_CHANNELS 4 +#define MIPI_D_LANES_PER_DPHY 2 +#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 +#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 +/* 2 Data Lanes per D-PHY */ +#define MIPI_DPHY_D_LANES 2 +#define MIPI_DPHY_DEFAULT_BIT_RATES 63 + +#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) +#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) +#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) + struct kmb_connector; struct kmb_dsi_host;

@@ -33,16 +87,7 @@ struct kmb_connector { struct drm_display_mode *fixed_mode; };

-#define MIPI_TX_FRAME_GEN 4 -#define MIPI_TX_FRAME_GEN_SECTIONS 4 -#define MIPI_CTRL_VIRTUAL_CHANNELS 4 -#define MIPI_D_LANES_PER_DPHY 2 -#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 -#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 -#define MIPI_DPHY_D_LANES 2 /* 2 Data Lanes per D-PHY*/ -#define MIPI_DPHY_DEFAULT_BIT_RATES 63 - -/*DPHY Tx test codes */ +/* DPHY Tx test codes */

enum mipi_ctrl_num { MIPI_CTRL0 = 0, @@ -232,7 +277,7 @@ struct mipi_tx_dsi_cfg { struct mipi_tx_frame_section_cfg { uint32_t dma_v_stride; uint16_t dma_v_scale_cfg; - uint16_t width_pixels; /* Frame width */ + uint16_t width_pixels; uint16_t height_lines; uint8_t dma_packed; uint8_t bpp; @@ -304,15 +349,15 @@ struct mipi_ctrl_cfg { struct mipi_tx_ctrl_cfg tx_ctrl_cfg; };

-/*structure for storing user specified interrupts that are enabled */ +/* Structure for storing user specified interrupts that are enabled */ union mipi_irq_cfg { uint8_t value; struct { - uint8_t line_compare : 1; - uint8_t dma_event : 1; - uint8_t frame_done : 1; - uint8_t ctrl_error : 1; - uint8_t dphy_error : 1; + uint8_t line_compare:1; + uint8_t dma_event:1; + uint8_t frame_done:1; + uint8_t ctrl_error:1; + uint8_t dphy_error:1; } irq_cfg; };

@@ -322,9 +367,4 @@ void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void kmb_dsi_host_unregister(void); int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode); - -#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) -#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) -#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) - #endif /* __KMB_DSI_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index bf93986..f92e191 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -21,67 +21,6 @@ #include "kmb_plane.h" #include "kmb_regs.h"

-/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ -static const u32 kmb_formats_g[] = { - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, -}; - -#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) -#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) - -/* video layer ( 0 & 1) formats, packed and planar formats are supported */ -static const u32 kmb_formats_v[] = { - /* packed formats */ - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - /*planar formats */ - DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, - DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, - DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, - DRM_FORMAT_NV12, DRM_FORMAT_NV21, -}; - -#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDERFLOW | \ - LAYER0_DMA_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_UNDERFLOW | \ - LAYER0_DMA_CR_FIFO_OVERFLOW | \ - LAYER0_DMA_CR_FIFO_UNDERFLOW) - -#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ - LAYER1_DMA_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_UNDERFLOW | \ - LAYER1_DMA_CR_FIFO_OVERFLOW | \ - LAYER1_DMA_CR_FIFO_UNDERFLOW) - -#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) - -#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) - -#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) - -#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) - -#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) - -#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) - const uint32_t layer_irqs[] = { LCD_INT_VL0, LCD_INT_VL1, @@ -89,16 +28,6 @@ const uint32_t layer_irqs[] = { LCD_INT_GL1 };

-/*Conversion (yuv->rgb) matrix from myriadx */ -static const u32 csc_coef_lcd[] = { - 1024, 0, 1436, - 1024, -352, -731, - 1024, 1814, 0, - -179, 125, -226 -}; - -/*plane initialization status */ - static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -117,7 +46,6 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, int ret;

fb = state->fb; - if (!fb || !state->crtc) return 0;

@@ -249,7 +177,6 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_RGBA8888; break; } - DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); return val; }

@@ -280,14 +207,14 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) break; }

- DRM_INFO("%s : %d bpp=%d val=%d\n", __func__, __LINE__, bpp, val); + DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val); return val; }

#ifdef LCD_TEST static void config_csc(struct kmb_drm_private *dev_p, int plane_id) { - /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */ + /* YUV to RGB conversion using the fixed matrix csc_coef_lcd */ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); @@ -338,9 +265,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y;

- DRM_DEBUG - ("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x", - __func__, __LINE__, src_w, src_h, fb->format->format, fb->flags); + DRM_DEBUG("src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", + src_w, src_h, fb->format->format, fb->flags);

width = fb->width; height = fb->height; @@ -348,38 +274,41 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, DRM_DEBUG("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), fb->pitches[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), (width * fb->format->cpp[0]));

addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); - dev_p->fb_addr = (dma_addr_t) addr; + dev_p->fb_addr = addr[Y_PLANE]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr[Y_PLANE] + fb->offsets[0]); - /*program Cb/Cr for planar formats */ + /* Program Cb/Cr for planar formats */ if (num_planes > 1) { if (fb->format->format == DRM_FORMAT_YUV420 || fb->format->format == DRM_FORMAT_YVU420) width /= 2; - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), fb->pitches[LAYER_1]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, U_PLANE); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), addr[U_PLANE]); + if (num_planes == 3) { kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); + addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, V_PLANE); @@ -389,8 +318,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, } }

- kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y);

@@ -402,25 +331,25 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, if (val & LCD_LAYER_PLANAR_STORAGE) { val |= LCD_LAYER_CSC_EN;

- /*enable CSC if input is planar and output is RGB */ + /* Enable CSC if input is planar and output is RGB */ config_csc(dev_p, plane_id); }

kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val);

switch (plane_id) { - case LAYER_0: - ctrl = LCD_CTRL_VL1_ENABLE; - break; - case LAYER_1: - ctrl = LCD_CTRL_VL2_ENABLE; - break; - case LAYER_2: - ctrl = LCD_CTRL_GL1_ENABLE; - break; - case LAYER_3: - ctrl = LCD_CTRL_GL2_ENABLE; - break; + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; }

ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE @@ -441,16 +370,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* Leave RGB order,conversion mode and clip mode to default */ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; - // out_format |= LCD_OUTF_SYNC_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format);

dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16;

- /* enable DMA */ + /* Enable DMA */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - DRM_DEBUG("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", - __func__, __LINE__, dma_cfg, + DRM_DEBUG("dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); #endif } @@ -473,7 +400,6 @@ static void kmb_destroy_plane_state(struct drm_plane *plane, struct drm_plane_state *state) { struct kmb_plane_state *kmb_state = to_kmb_plane_state(state); - __drm_atomic_helper_plane_destroy_state(state); kfree(kmb_state); } @@ -484,7 +410,6 @@ struct drm_plane_state *kmb_plane_duplicate_state(struct drm_plane *plane) struct kmb_plane_state *kmb_state;

kmb_state = kmemdup(plane->state, sizeof(*kmb_state), GFP_KERNEL); - if (!kmb_state) return NULL;

@@ -534,7 +459,6 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) int num_plane_formats;

for (i = 0; i < lcd->n_layers; i++) { - plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);

if (!plane) { @@ -553,26 +477,25 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) }

ret = drm_universal_plane_init(drm, &plane->base_plane, - POSSIBLE_CRTCS, - &kmb_plane_funcs, plane_formats, - num_plane_formats, + POSSIBLE_CRTCS, &kmb_plane_funcs, + plane_formats, num_plane_formats, NULL, plane_type, "plane %d", i); if (ret < 0) { - DRM_ERROR - ("drm_universal_plane_init -failed with ret=%d", - ret); + DRM_ERROR("drm_universal_plane_init failed (ret=%d)", + ret); goto cleanup; } DRM_DEBUG("%s : %d plane=%px\n i=%d type=%d", - __func__, __LINE__, &plane->base_plane, - i, plane_type); - + __func__, __LINE__, + &plane->base_plane, i, plane_type); drm_plane_helper_add(&plane->base_plane, &kmb_plane_helper_funcs); if (plane_type == DRM_PLANE_TYPE_PRIMARY) { primary = plane; lcd->plane = plane; } + DRM_DEBUG("%s : %d primary=%px\n", __func__, __LINE__, + &primary->base_plane); plane->id = i; }

diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index b1ac9db..6e4da47 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -8,6 +8,34 @@

#include "kmb_drv.h"

+#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDERFLOW | \ + LAYER0_DMA_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_UNDERFLOW | \ + LAYER0_DMA_CR_FIFO_OVERFLOW | \ + LAYER0_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ + LAYER1_DMA_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_UNDERFLOW | \ + LAYER1_DMA_CR_FIFO_OVERFLOW | \ + LAYER1_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) +#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) +#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) +#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) +#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) +#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) + +#define POSSIBLE_CRTCS 1 +#define INITIALIZED 1 +#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) + +#define to_kmb_plane_state(x) \ + container_of(x, struct kmb_plane_state, base_plane_state) + enum layer_id { LAYER_0, LAYER_1, @@ -34,12 +62,48 @@ struct kmb_plane_state { unsigned char no_planes; };

-#define POSSIBLE_CRTCS 1 -#define INITIALIZED 1 -#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) +/* Graphics layer (layers 2 & 3) formats, only packed formats are supported */ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, +};

-#define to_kmb_plane_state(x) \ - container_of(x, struct kmb_plane_state, base_plane_state) +#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) +#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) + +/* Video layer ( 0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + /*planar formats */ + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +/* Conversion (yuv->rgb) matrix from myriadx */ +static const u32 csc_coef_lcd[] = { + 1024, 0, 1436, + 1024, -352, -731, + 1024, 1814, 0, + -179, 125, -226 +};

struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index f5c1c4d..c5768d5 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -533,9 +533,10 @@ /* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 (0x00) #define MIPI_DPHY_ERR_IRQ 1 -#define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ +#define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ #define MIPI_HS_IRQ 13 -#define MIPI_HS_IRQ_MASK 0x7FE000 /*bits 13-22 */ +/*bits 13-22 */ +#define MIPI_HS_IRQ_MASK 0x7FE000 #define MIPI_LP_EVENT_IRQ 25 #define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \ MIPI_CTRL_IRQ_STATUS0) @@ -715,18 +716,18 @@ & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c)

-#define MSS_MIPI_CIF_CFG (0x00) -#define MSS_LCD_MIPI_CFG (0x04) -#define MSS_CAM_CLK_CTRL (0x10) -#define MSS_LOOPBACK_CFG (0x0C) -#define LCD (1<<1) -#define MIPI_COMMON (1<<2) -#define MIPI_TX0 (1<<9) -#define MSS_CAM_RSTN_CTRL (0x14) -#define MSS_CAM_RSTN_SET (0x20) -#define MSS_CAM_RSTN_CLR (0x24) +#define MSS_MIPI_CIF_CFG (0x00) +#define MSS_LCD_MIPI_CFG (0x04) +#define MSS_CAM_CLK_CTRL (0x10) +#define MSS_LOOPBACK_CFG (0x0C) +#define LCD (1<<1) +#define MIPI_COMMON (1<<2) +#define MIPI_TX0 (1<<9) +#define MSS_CAM_RSTN_CTRL (0x14) +#define MSS_CAM_RSTN_SET (0x20) +#define MSS_CAM_RSTN_CLR (0x24)

-#define MSSCPU_CPR_CLK_EN (0x0) -#define MSSCPU_CPR_RST_EN (0x10) +#define MSSCPU_CPR_CLK_EN (0x0) +#define MSSCPU_CPR_RST_EN (0x10) #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */

general cleaning

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 6e38f16..2599ed2 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -307,7 +307,7 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm,

struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { - struct drm_bridge *bridge; + struct drm_bridge *bridge = NULL; #ifndef FCCTEST struct device_node *encoder_node; #endif @@ -815,7 +815,7 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *ctrl_cfg) { - u32 ret; + u32 ret = 0; u8 active_vchannels = 0; u8 frame_id, sect; u32 bits_per_pclk = 0;

KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only accepts 4-lane input from mipi. With 4-lane mipi, KMB hardware can only support 1080p resolution. Therefore, limit supported mode to 1080p.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 4 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 8 +++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 11 +++++++++++ drivers/gpu/drm/kmb/kmb_plane.c | 2 ++ 4 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 7fcab4b..b844c77 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -337,8 +337,8 @@ static const struct drm_mode_config_funcs kmb_mode_config_funcs = { static void kmb_setup_mode_config(struct drm_device *drm) { drm_mode_config_init(drm); - drm->mode_config.min_width = 0; - drm->mode_config.min_height = 0; + drm->mode_config.min_width = KMB_MIN_WIDTH; + drm->mode_config.min_height = KMB_MIN_HEIGHT; drm->mode_config.max_width = KMB_MAX_WIDTH; drm->mode_config.max_height = KMB_MAX_HEIGHT; drm->mode_config.funcs = &kmb_mode_config_funcs; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 94b62b9..373a059 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -8,10 +8,12 @@

#include "kmb_regs.h"

-#define FCCTEST +//#define FCCTEST #define LCD_TEST -#define KMB_MAX_WIDTH 1920 /*max width in pixels */ -#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MAX_WIDTH 1920 /*max width in pixels */ +#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MIN_WIDTH 1920 /*max width in pixels */ +#define KMB_MIN_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 2599ed2..47798ed 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -193,6 +193,17 @@ static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { + struct drm_device *dev = connector->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + + if (mode->hdisplay < mode_config->min_width || + mode->hdisplay > mode_config->max_width) + return MODE_BAD_HVALUE; + + if (mode->vdisplay < mode_config->min_height || + mode->vdisplay > mode_config->max_height) + return MODE_BAD_VVALUE; + return MODE_OK; }

diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 8b2b202..a6b5969 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -57,6 +57,8 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,

if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) return -EINVAL; + if (state->crtc_w < KMB_MIN_WIDTH || state->crtc_h < KMB_MIN_HEIGHT) + return -EINVAL; return 0; }

System clock is different for A0 and B0 silicons, so get it directly from clk_PLL0 through SCMI calls.

Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 11 +++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 12 +----------- 3 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 559742b8..17d303f 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -39,6 +39,7 @@ static struct clk *clk_lcd; static struct clk *clk_mipi; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg; +static struct clk *clk_pll0;

struct drm_bridge *adv_bridge;

@@ -122,6 +123,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) #ifdef ICAM_LCD_QOS int val = 0; #endif + struct device_node *vpu_dev;

/* Map MIPI MMIO registers */ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); @@ -188,6 +190,15 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi_cfg\n"); goto setup_fail; } + vpu_dev = of_find_node_by_path("/soc/vpu-ipc"); + DRM_INFO("vpu node = %pOF", vpu_dev); + clk_pll0 = of_clk_get_by_name(vpu_dev, "pll_0_out_0"); + if (IS_ERR(clk_pll0)) { + DRM_ERROR("clk_get() failed clk_pll0 "); + goto setup_fail; + } + dev_p->sys_clk_mhz = clk_get_rate(clk_pll0)/1000000; + DRM_INFO("system clk = %d Mhz", dev_p->sys_clk_mhz); #ifdef LCD_TEST /* Set LCD clock to 200 Mhz */ DRM_DEBUG("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 939f8b4..72d0746 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -38,6 +38,7 @@ struct kmb_drm_private { spinlock_t irq_lock; int irq_lcd; int irq_mipi; + int sys_clk_mhz; dma_addr_t fb_addr; };

diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 47798ed..8f8b50c 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -588,20 +588,10 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, u8 frame_gen, u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;

-#ifdef GET_SYS_CLK - /* Get system clock for blanking period cnfigurations */ - sc = get_clock_frequency(CPR_CLK_SYSTEM, &sysclk); - if (sc) - return sc; - - /* Convert to MHZ */ - sysclk /= 1000; -#else /* 500 Mhz system clock minus 50 to account for the difference in * MIPI clock speed in RTL tests */ - sysclk = KMB_SYS_CLK_MHZ - 50; -#endif + sysclk = dev_p->sys_clk_mhz - 50;

/* PPL-Pixel Packing Layer, LLP-Low Level Protocol * Frame genartor timing parameters are clocked on the system clock,