Hi,

Am 28.09.2021 um 11:35 schrieb Paul Cercueil paul@crapouillou.net:

Hi Nikolaus / Paul,

Le lun., sept. 27 2021 at 18:44:20 +0200, H. Nikolaus Schaller hns@goldelico.com a écrit :

...

From: Paul Boddie paul@boddie.org.uk Add support for the LCD controller present on JZ4780 SoCs. This SoC uses 8-byte descriptors which extend the current 4-byte descriptors used for other Ingenic SoCs. Tested on MIPS Creator CI20 board. Signed-off-by: Paul Boddie paul@boddie.org.uk Signed-off-by: Ezequiel Garcia ezequiel@collabora.com Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

---

drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 85 +++++++++++++++++++++-- drivers/gpu/drm/ingenic/ingenic-drm.h | 42 +++++++++++ 2 files changed, 122 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index f73522bdacaa..e2df4b085905 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -6,6 +6,7 @@ #include "ingenic-drm.h" +#include <linux/bitfield.h> #include <linux/component.h> #include <linux/clk.h> #include <linux/dma-mapping.h> @@ -49,6 +50,11 @@ struct ingenic_dma_hwdesc { u32 addr; u32 id; u32 cmd;

• /* extended hw descriptor for jz4780 */
• u32 offsize;
• u32 pagewidth;
• u32 cpos;
• u32 dessize;

} __aligned(16); struct ingenic_dma_hwdescs { @@ -60,9 +66,11 @@ struct jz_soc_info { bool needs_dev_clk; bool has_osd; bool map_noncoherent;

• bool use_extended_hwdesc; unsigned int max_width, max_height; const u32 *formats_f0, *formats_f1; unsigned int num_formats_f0, num_formats_f1;
• unsigned int max_reg;

}; struct ingenic_drm_private_state { @@ -168,12 +176,11 @@ static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) } } -static const struct regmap_config ingenic_drm_regmap_config = { +static struct regmap_config ingenic_drm_regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4,

• .max_register = JZ_REG_LCD_SIZE1, .writeable_reg = ingenic_drm_writeable_reg,

}; @@ -663,6 +670,37 @@ static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); hwdesc->next = dma_hwdesc_addr(priv, next_id);

• if (priv->soc_info->use_extended_hwdesc) {
  

• 	hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE;
  

• 	/* Extended 8-byte descriptor */
  

• 	hwdesc->cpos = 0;
  

• 	hwdesc->offsize = 0;
  

• 	hwdesc->pagewidth = 0;
  

• 	switch (newstate->fb->format->format) {
  

• 	case DRM_FORMAT_XRGB1555:
  

• 		hwdesc->cpos |= JZ_LCD_CPOS_RGB555;
  

• 		fallthrough;
  

• 	case DRM_FORMAT_RGB565:
  

• 		hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16;
  

• 		break;
  

• 	case DRM_FORMAT_XRGB8888:
  

• 		hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24;
  

• 		break;
  

• 	}
  

• 	hwdesc->cpos |= JZ_LCD_CPOS_PREMULTIPLY_LCD |
  

• 			    (JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 <<
  

• 			     JZ_LCD_CPOS_COEFFICIENT_OFFSET);
  

• 	hwdesc->dessize =
  

• 		(0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) |
  

• 		FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK <<
  

• 			   JZ_LCD_DESSIZE_HEIGHT_OFFSET, height - 1) |
  

• 		FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK <<
  

• 			   JZ_LCD_DESSIZE_WIDTH_OFFSET, width - 1);
  

• }
  

• if (drm_atomic_crtc_needs_modeset(crtc_state)) { fourcc = newstate->fb->format->format;

@@ -694,6 +732,10 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; }

• /* set use of the 8-word descriptor and OSD foreground usage. */
• if (priv->soc_info->use_extended_hwdesc)

• cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
  

• if (mode->flags & DRM_MODE_FLAG_NHSYNC) cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; if (mode->flags & DRM_MODE_FLAG_NVSYNC)

@@ -1010,6 +1052,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) struct drm_encoder *encoder; struct ingenic_drm_bridge *ib; struct drm_device *drm;

• struct regmap_config regmap_config; void __iomem *base; long parent_rate; unsigned int i, clone_mask = 0;

@@ -1063,8 +1106,10 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) return PTR_ERR(base); }

• regmap_config = ingenic_drm_regmap_config;
• regmap_config.max_register = soc_info->max_reg; priv->map = devm_regmap_init_mmio(dev, base,

• 			  &ingenic_drm_regmap_config);
  

• 			  &regmap_config);
  

Could you split the code that makes .max_reg configurable per-SoC into its own patch?

Yes.

...

if (IS_ERR(priv->map)) { dev_err(dev, "Failed to create regmap\n"); return PTR_ERR(priv->map); @@ -1274,7 +1319,7 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) /* Enable OSD if available */ if (soc_info->has_osd)

• regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
  

• regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
  

Why?

If I remember we should not assume that all others bits in JZ_REG_LCD_OSDC can be safely overwritten by 0, although their reset state is 0 as well.

These are several alpha-blending bits and interrupt masks in the same register. Apparently only in jz4780.

...

mutex_init(&priv->clk_mutex); priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; @@ -1444,6 +1489,7 @@ static const struct jz_soc_info jz4740_soc_info = { .formats_f1 = jz4740_formats, .num_formats_f1 = ARRAY_SIZE(jz4740_formats), /* JZ4740 has only one plane */

• .max_reg = JZ_REG_LCD_SIZE1,

}; static const struct jz_soc_info jz4725b_soc_info = { @@ -1456,6 +1502,7 @@ static const struct jz_soc_info jz4725b_soc_info = { .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), .formats_f0 = jz4725b_formats_f0, .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0),

• .max_reg = JZ_REG_LCD_SIZE1,

}; static const struct jz_soc_info jz4770_soc_info = { @@ -1468,12 +1515,28 @@ static const struct jz_soc_info jz4770_soc_info = { .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), .formats_f0 = jz4770_formats_f0, .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),

• .max_reg = JZ_REG_LCD_SIZE1,

+};

+static const struct jz_soc_info jz4780_soc_info = {

• .needs_dev_clk = true,
• .has_osd = true,
• .use_extended_hwdesc = true,
• .max_width = 4096,
• .max_height = 2048,
• /* REVISIT: do we support formats different from jz4770? */
• .formats_f1 = jz4770_formats_f1,
• .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
• .formats_f0 = jz4770_formats_f0,
• .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
• .max_reg = JZ_REG_LCD_PCFG,

}; static const struct of_device_id ingenic_drm_of_match[] = { { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },

• { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, { /* sentinel */ },

}; MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); @@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) { int err;

• if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) {

• err = platform_driver_register(ingenic_dw_hdmi_driver_ptr);
  

• if (err)
  

• 	return err;
  

• }

I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver.

Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example).

It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency.

But: what is ingenic_ipu_driver_ptr then good for?

If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely.

Cheers, -Paul

BR, Nikolaus

Hi Paul,

Am 28.09.2021 um 14:06 schrieb H. Nikolaus Schaller hns@goldelico.com:

Hi Paul,

...

Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller hns@goldelico.com:

...

...

@@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) { int err;

• if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) {

• err = platform_driver_register(ingenic_dw_hdmi_driver_ptr);
  

• if (err)
  

• 	return err;
  

• }

I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver.

Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example).

It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency.

But: what is ingenic_ipu_driver_ptr then good for?

If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely.

A quick test shows that it *is* required. At least if I configure everything as modules. But like you I can't explain why.

Well, just a very rough idea (may be wrong): the bridge chain is not like an i2c bus and clients are not automatically loaded/probed if linked in the device tree. Therefore the consumer (ingenic_drm_drv) must register the "clients" like IPU and HDMI.

Any suggestion how to proceed here for v5?

BR, Nikolaus

Hi Paul,

Am 29.09.2021 um 16:30 schrieb Paul Cercueil paul@crapouillou.net:

Hi,

Le mar., sept. 28 2021 at 14:06:03 +0200, H. Nikolaus Schaller hns@goldelico.com a écrit :

...

Hi Paul,

...

Am 28.09.2021 um 12:21 schrieb H. Nikolaus Schaller hns@goldelico.com:

...

...

@@ -1492,10 +1555,16 @@ static int ingenic_drm_init(void) { int err;

• if (IS_ENABLED(CONFIG_DRM_INGENIC_DW_HDMI)) {

• err = platform_driver_register(ingenic_dw_hdmi_driver_ptr);
  

• if (err)
  

• 	return err;
  

• }

I don't see why you need to register the ingenic-dw-hdmi driver here. Just register it in the ingenic-dw-hdmi driver.

Ok, I never though about this (as the code was not from me). We apparently just followed the IPU code pattern (learning by example). It indeed looks not necessary and would also avoid the ingenic_dw_hdmi_driver_ptr dependency. But: what is ingenic_ipu_driver_ptr then good for?

It's done this way because ingenic-drm-drv.c and ingenic-ipu.c are both compiled within the same module ingenic-drm.

Ah, I see. Hadn't checked this.

I'm not sure this is still required, maybe ingenic-ipu.c can be its own module now.

What I have seen is that it has its own compatible record. So there could be load-on-demand by DTS.

...

...

If we can get rid of this as well, we can drop patch 1/10 ("drm/ingenic: Fix drm_init error path if IPU was registered") completely.

A quick test shows that it *is* required. At least if I configure everything as modules. But like you I can't explain why.

Well, a quick test here shows that it is not required, at least when configuring with everything built-in.

IMHO the hdmi driver (module) should be loaded on demand. Not everyone wants to have it.

Well, that is the problem that needs to be solved...

BR and thanks, Nikolaus

Hi,

On Mon, Sep 27, 2021 at 06:44:21PM +0200, H. Nikolaus Schaller wrote:

From: Sam Ravnborg sam@ravnborg.org

Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC. Based on .txt binding from Zubair Lutfullah Kakakhel

Signed-off-by: Sam Ravnborg sam@ravnborg.org Signed-off-by: H. Nikolaus Schaller hns@goldelico.com Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org

---

.../bindings/display/ingenic-jz4780-hdmi.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml

diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml new file mode 100644 index 000000000000..5e60cdac4f63 --- /dev/null +++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: Bindings for Ingenic JZ4780 HDMI Transmitter

+maintainers:

• • H. Nikolaus Schaller hns@goldelico.com

+description: |

• The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
• TX controller IP with accompanying PHY IP.

+allOf:

• • $ref: panel/panel-common.yaml#

Is it a panel though?

+properties:

• compatible:
• items:

•  - const: ingenic,jz4780-dw-hdmi
  

This can just be a const, there's no need for the items

• reg:
• maxItems: 1
• description: the address & size of the LCD controller registers

There's no need for that description, it's obvious enough

• reg-io-width:
• const: 4

If it's fixed, why do you need it in the first place?

• interrupts:
• maxItems: 1
• description: Specifies the interrupt provided by parent

There's no need for that description, it's obvious enough

• clocks:
• maxItems: 2
• description: Clock specifiers for isrf and iahb clocks

This can be defined as

clocks: items: - description: isrf - description: iahb

A better description about what these clocks are would be nice as well

• clock-names:
• items:

•  - const: isfr
  

Is it isfr or isrf?

•  - const: iahb
  

• hdmi-regulator: true
• description: Optional regulator to provide +5V at the connector

regulators need to be suffixed by -supply

You also can just provide the description, you don't need the true there

• ddc-i2c-bus: true

ditto

• description: An I2C interface if the internal DDC I2C driver is not to be used
• ports: true

If there's a single port, you don't need ports

You should also include /schemas/graph.yaml#/$defs/port-base

Maxime

Am 27.09.2021 um 19:00 schrieb Maxime Ripard maxime@cerno.tech:

Hi,

On Mon, Sep 27, 2021 at 06:44:23PM +0200, H. Nikolaus Schaller wrote:

...

It appears that dw-hdmi plugin detection is not properly propagated unless we call drm_kms_helper_hotplug_event().

Maybe drm_bridge_hpd_notify should have been setup to call this.

Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index f082e14320e1..edea04f80576 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3018,6 +3018,8 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) if (hdmi->bridge.dev) { drm_helper_hpd_irq_event(hdmi->bridge.dev); drm_bridge_hpd_notify(&hdmi->bridge, status);

• 	drm_kms_helper_hotplug_event(hdmi->bridge.dev);
  

drm_kms_helper_hotplug_event is already called from drm_helper_hpd_irq_event

Ah, now I see. It should be called but is not for some unkown condition (poll disabled? changed = false?).

It may also be a leftover from the attempt to make it work with the builtin dw-hdmi connector.

Will check for v5.

BR and thanks, Nikolaus

On Mon, Sep 27, 2021 at 06:44:24PM +0200, H. Nikolaus Schaller wrote:

From: Paul Boddie paul@boddie.org.uk

A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 HDMI support. This requires a new driver, plus device tree and configuration modifications.

Signed-off-by: Paul Boddie paul@boddie.org.uk Signed-off-by: Ezequiel Garcia ezequiel@collabora.com Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

---

drivers/gpu/drm/ingenic/Kconfig | 9 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c

diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig index 3b57f8be007c..4c7d311fbeff 100644 --- a/drivers/gpu/drm/ingenic/Kconfig +++ b/drivers/gpu/drm/ingenic/Kconfig @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU

 The Image Processing Unit (IPU) will appear as a second primary plane.

+config DRM_INGENIC_DW_HDMI

• bool "Ingenic specific support for Synopsys DW HDMI"
• depends on MACH_JZ4780
• select DRM_DW_HDMI
• help

•  Choose this option to enable Synopsys DesignWare HDMI based driver.
  

•  If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
  

•  select this option..
  

endif diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile index d313326bdddb..3db9888a6c04 100644 --- a/drivers/gpu/drm/ingenic/Makefile +++ b/drivers/gpu/drm/ingenic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o ingenic-drm-y = ingenic-drm-drv.o ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c new file mode 100644 index 000000000000..dd9c94ae842e --- /dev/null +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.

• • Copyright (C) 2019, 2020 Paul Boddie paul@boddie.org.uk
• • Derived from dw_hdmi-imx.c with i.MX portions removed.
• • Probe and remove operations derived from rcar_dw_hdmi.c.
• */

+#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h>

+#include <drm/bridge/dw_hdmi.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {

• { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } },
• { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } },
• { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } },
• { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } },
• { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } }

+};

+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {

• /*pixelclk bpp8 bpp10 bpp12 */
• { 54000000, { 0x091c, 0x091c, 0x06dc } },
• { 58400000, { 0x091c, 0x06dc, 0x06dc } },
• { 72000000, { 0x06dc, 0x06dc, 0x091c } },
• { 74250000, { 0x06dc, 0x0b5c, 0x091c } },
• { 118800000, { 0x091c, 0x091c, 0x06dc } },
• { 216000000, { 0x06dc, 0x0b5c, 0x091c } },
• { ~0UL, { 0x0000, 0x0000, 0x0000 } },

+};

+/*

• • Resistance term 133Ohm Cfg
• • PREEMP config 0.00
• • TX/CK level 10
• */

+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {

• /*pixelclk symbol term vlev */
• { 216000000, 0x800d, 0x0005, 0x01ad},
• { ~0UL, 0x0000, 0x0000, 0x0000}

+};

+static enum drm_mode_status +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,

• 	   const struct drm_display_info *info,
  

• 	   const struct drm_display_mode *mode)
  

+{

• if (mode->clock < 13500)

• return MODE_CLOCK_LOW;
  

• /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
• if (mode->clock > 216000)

• return MODE_CLOCK_HIGH;
  

• return MODE_OK;

+}

+static bool +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge,

• 	   const struct drm_display_mode *mode,
  

• 	   struct drm_display_mode *adjusted_mode)
  

+{

• adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
• adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
• return true;

+}

+static const struct drm_bridge_timings ingenic_dw_hdmi_timings = {

• .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,

+};

+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {

• .mpll_cfg = ingenic_mpll_cfg,
• .cur_ctr = ingenic_cur_ctr,
• .phy_config = ingenic_phy_config,
• .mode_valid = ingenic_dw_hdmi_mode_valid,
• .mode_fixup = ingenic_dw_hdmi_mode_fixup,
• .timings = &ingenic_dw_hdmi_timings,
• .output_port = 1,

+};

+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {

• { .compatible = "ingenic,jz4780-dw-hdmi" },
• { /* Sentinel */ },

+}; +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);

+static int ingenic_dw_hdmi_probe(struct platform_device *pdev) +{

• struct dw_hdmi *hdmi;
• struct regulator *regulator;
• int ret;
• hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data);
• if (IS_ERR(hdmi))

• return PTR_ERR(hdmi);
  

• platform_set_drvdata(pdev, hdmi);
• regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v");
• if (IS_ERR(regulator)) {

• ret = PTR_ERR(regulator);
  

• DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n",
  

• 	      "hdmi-5v", ret);
  

• return ret;
  

• }

This doesn't match your binding

Maxime

On 27/09/2021 18:44, H. Nikolaus Schaller wrote:

From: Paul Boddie paul@boddie.org.uk

A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 HDMI support. This requires a new driver, plus device tree and configuration modifications.

Signed-off-by: Paul Boddie paul@boddie.org.uk Signed-off-by: Ezequiel Garcia ezequiel@collabora.com Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

---

drivers/gpu/drm/ingenic/Kconfig | 9 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c

diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig index 3b57f8be007c..4c7d311fbeff 100644 --- a/drivers/gpu/drm/ingenic/Kconfig +++ b/drivers/gpu/drm/ingenic/Kconfig @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU

 The Image Processing Unit (IPU) will appear as a second primary plane.

+config DRM_INGENIC_DW_HDMI

• bool "Ingenic specific support for Synopsys DW HDMI"
• depends on MACH_JZ4780
• select DRM_DW_HDMI
• help

•  Choose this option to enable Synopsys DesignWare HDMI based driver.
  

•  If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
  

•  select this option..
  

endif diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile index d313326bdddb..3db9888a6c04 100644 --- a/drivers/gpu/drm/ingenic/Makefile +++ b/drivers/gpu/drm/ingenic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o ingenic-drm-y = ingenic-drm-drv.o ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c new file mode 100644 index 000000000000..dd9c94ae842e --- /dev/null +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.

• • Copyright (C) 2019, 2020 Paul Boddie paul@boddie.org.uk
• • Derived from dw_hdmi-imx.c with i.MX portions removed.
• • Probe and remove operations derived from rcar_dw_hdmi.c.
• */

+#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h>

+#include <drm/bridge/dw_hdmi.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {

• { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } },
• { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } },
• { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } },
• { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } },
• { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } }

+};

+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {

• /*pixelclk bpp8 bpp10 bpp12 */
• { 54000000, { 0x091c, 0x091c, 0x06dc } },
• { 58400000, { 0x091c, 0x06dc, 0x06dc } },
• { 72000000, { 0x06dc, 0x06dc, 0x091c } },
• { 74250000, { 0x06dc, 0x0b5c, 0x091c } },
• { 118800000, { 0x091c, 0x091c, 0x06dc } },
• { 216000000, { 0x06dc, 0x0b5c, 0x091c } },
• { ~0UL, { 0x0000, 0x0000, 0x0000 } },

+};

+/*

• • Resistance term 133Ohm Cfg
• • PREEMP config 0.00
• • TX/CK level 10
• */

+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {

• /*pixelclk symbol term vlev */
• { 216000000, 0x800d, 0x0005, 0x01ad},
• { ~0UL, 0x0000, 0x0000, 0x0000}

+};

+static enum drm_mode_status +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,

• 	   const struct drm_display_info *info,
  

• 	   const struct drm_display_mode *mode)
  

+{

• if (mode->clock < 13500)

• return MODE_CLOCK_LOW;
  

• /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
• if (mode->clock > 216000)

• return MODE_CLOCK_HIGH;
  

• return MODE_OK;

+}

+static bool +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge,

• 	   const struct drm_display_mode *mode,
  

• 	   struct drm_display_mode *adjusted_mode)
  

+{

• adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
• adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
• return true;

+}

+static const struct drm_bridge_timings ingenic_dw_hdmi_timings = {

• .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,

+};

These should go in the intermediate encoder bridge callbacks Paul introduces in his patch at [1].

With that patch 4 can be dropped.

[1] https://lore.kernel.org/r/20210922205555.496871-7-paul@crapouillou.net

Neil

+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {

• .mpll_cfg = ingenic_mpll_cfg,
• .cur_ctr = ingenic_cur_ctr,
• .phy_config = ingenic_phy_config,
• .mode_valid = ingenic_dw_hdmi_mode_valid,
• .mode_fixup = ingenic_dw_hdmi_mode_fixup,
• .timings = &ingenic_dw_hdmi_timings,
• .output_port = 1,

+};

+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {

• { .compatible = "ingenic,jz4780-dw-hdmi" },
• { /* Sentinel */ },

+}; +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);

+static int ingenic_dw_hdmi_probe(struct platform_device *pdev) +{

• struct dw_hdmi *hdmi;
• struct regulator *regulator;
• int ret;
• hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data);
• if (IS_ERR(hdmi))

• return PTR_ERR(hdmi);
  

• platform_set_drvdata(pdev, hdmi);
• regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v");
• if (IS_ERR(regulator)) {

• ret = PTR_ERR(regulator);
  

• DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n",
  

• 	      "hdmi-5v", ret);
  

• return ret;
  

• }
• ret = regulator_enable(regulator);
• if (ret) {

• DRM_DEV_ERROR(&pdev->dev, "Failed to enable hpd regulator: %d\n",
  

• 	      ret);
  

• return ret;
  

• }
• return 0;

+}

+static int ingenic_dw_hdmi_remove(struct platform_device *pdev) +{

• struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
• dw_hdmi_remove(hdmi);
• return 0;

+}

+static struct platform_driver ingenic_dw_hdmi_driver = {

• .probe = ingenic_dw_hdmi_probe,
• .remove = ingenic_dw_hdmi_remove,
• .driver = {

• .name = "dw-hdmi-ingenic",
  

• .of_match_table = ingenic_dw_hdmi_dt_ids,
  

• },

+};

+struct platform_driver *ingenic_dw_hdmi_driver_ptr = &ingenic_dw_hdmi_driver;

Hi Nikolaus & Paul,

Le lun., sept. 27 2021 at 18:44:24 +0200, H. Nikolaus Schaller hns@goldelico.com a écrit :

From: Paul Boddie paul@boddie.org.uk

A specialisation of the generic Synopsys HDMI driver is employed for JZ4780 HDMI support. This requires a new driver, plus device tree and configuration modifications.

Signed-off-by: Paul Boddie paul@boddie.org.uk Signed-off-by: Ezequiel Garcia ezequiel@collabora.com Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

---

drivers/gpu/drm/ingenic/Kconfig | 9 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c

diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig index 3b57f8be007c..4c7d311fbeff 100644 --- a/drivers/gpu/drm/ingenic/Kconfig +++ b/drivers/gpu/drm/ingenic/Kconfig @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU

 The Image Processing Unit (IPU) will appear as a second primary 

plane.

+config DRM_INGENIC_DW_HDMI

• bool "Ingenic specific support for Synopsys DW HDMI"
• depends on MACH_JZ4780
• select DRM_DW_HDMI
• help

•  Choose this option to enable Synopsys DesignWare HDMI based 
  

driver.

•  If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
  

•  select this option..
  

endif diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile index d313326bdddb..3db9888a6c04 100644 --- a/drivers/gpu/drm/ingenic/Makefile +++ b/drivers/gpu/drm/ingenic/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o ingenic-drm-y = ingenic-drm-drv.o ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c new file mode 100644 index 000000000000..dd9c94ae842e --- /dev/null +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.

• • Copyright (C) 2019, 2020 Paul Boddie paul@boddie.org.uk
• • Derived from dw_hdmi-imx.c with i.MX portions removed.
• • Probe and remove operations derived from rcar_dw_hdmi.c.
• */

+#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h>

+#include <drm/bridge/dw_hdmi.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h>

+static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {

• { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2,

0x0000 } } },

• { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142,

0x0005 } } },

• { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2,

0x000a } } },

• { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002,

0x000f } } },

• { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000,

0x0000 } } } +};

+static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {

• /*pixelclk bpp8 bpp10 bpp12 */
• { 54000000, { 0x091c, 0x091c, 0x06dc } },
• { 58400000, { 0x091c, 0x06dc, 0x06dc } },
• { 72000000, { 0x06dc, 0x06dc, 0x091c } },
• { 74250000, { 0x06dc, 0x0b5c, 0x091c } },
• { 118800000, { 0x091c, 0x091c, 0x06dc } },
• { 216000000, { 0x06dc, 0x0b5c, 0x091c } },
• { ~0UL, { 0x0000, 0x0000, 0x0000 } },

+};

+/*

• • Resistance term 133Ohm Cfg
• • PREEMP config 0.00
• • TX/CK level 10
• */

+static const struct dw_hdmi_phy_config ingenic_phy_config[] = {

• /*pixelclk symbol term vlev */
• { 216000000, 0x800d, 0x0005, 0x01ad},
• { ~0UL, 0x0000, 0x0000, 0x0000}

+};

+static enum drm_mode_status +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,

• 	   const struct drm_display_info *info,
  

• 	   const struct drm_display_mode *mode)
  

+{

• if (mode->clock < 13500)

• return MODE_CLOCK_LOW;
  

• /* FIXME: Hardware is capable of 270MHz, but setup data is missing.

*/

• if (mode->clock > 216000)

• return MODE_CLOCK_HIGH;
  

• return MODE_OK;

+}

+static bool +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge,

• 	   const struct drm_display_mode *mode,
  

• 	   struct drm_display_mode *adjusted_mode)
  

+{

• adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC |

DRM_MODE_FLAG_PVSYNC);

• adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC |

DRM_MODE_FLAG_NVSYNC);

Why do these flags need to be cleared? The LCDC can work with negative v/h sync, does the HDMI core not work with that?

• return true;

+}

+static const struct drm_bridge_timings ingenic_dw_hdmi_timings = {

• .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,

That info should be provided in the EDID, is this really needed here?

Cheers, -Paul

+};

+static struct dw_hdmi_plat_data ingenic_dw_hdmi_plat_data = {

• .mpll_cfg = ingenic_mpll_cfg,
• .cur_ctr = ingenic_cur_ctr,
• .phy_config = ingenic_phy_config,
• .mode_valid = ingenic_dw_hdmi_mode_valid,
• .mode_fixup = ingenic_dw_hdmi_mode_fixup,
• .timings = &ingenic_dw_hdmi_timings,
• .output_port = 1,

+};

+static const struct of_device_id ingenic_dw_hdmi_dt_ids[] = {

• { .compatible = "ingenic,jz4780-dw-hdmi" },
• { /* Sentinel */ },

+}; +MODULE_DEVICE_TABLE(of, ingenic_dw_hdmi_dt_ids);

+static int ingenic_dw_hdmi_probe(struct platform_device *pdev) +{

• struct dw_hdmi *hdmi;
• struct regulator *regulator;
• int ret;
• hdmi = dw_hdmi_probe(pdev, &ingenic_dw_hdmi_plat_data);
• if (IS_ERR(hdmi))

• return PTR_ERR(hdmi);
  

• platform_set_drvdata(pdev, hdmi);
• regulator = devm_regulator_get_optional(&pdev->dev, "hdmi-5v");
• if (IS_ERR(regulator)) {

• ret = PTR_ERR(regulator);
  

• DRM_DEV_ERROR(&pdev->dev, "failed to get hpd regulator: %s (%d)\n",
  

• 	      "hdmi-5v", ret);
  

• return ret;
  

• }
• ret = regulator_enable(regulator);
• if (ret) {

• DRM_DEV_ERROR(&pdev->dev, "Failed to enable hpd regulator: %d\n",
  

• 	      ret);
  

• return ret;
  

• }
• return 0;

+}

+static int ingenic_dw_hdmi_remove(struct platform_device *pdev) +{

• struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
• dw_hdmi_remove(hdmi);
• return 0;

+}

+static struct platform_driver ingenic_dw_hdmi_driver = {

• .probe = ingenic_dw_hdmi_probe,
• .remove = ingenic_dw_hdmi_remove,
• .driver = {

• .name = "dw-hdmi-ingenic",
  

• .of_match_table = ingenic_dw_hdmi_dt_ids,
  

• },

+};

+struct platform_driver *ingenic_dw_hdmi_driver_ptr = &ingenic_dw_hdmi_driver; -- 2.31.1

Hi Paul,

Am 28.09.2021 um 11:58 schrieb Paul Cercueil paul@crapouillou.net:

Hi,

Le lun., sept. 27 2021 at 18:44:28 +0200, H. Nikolaus Schaller hns@goldelico.com a écrit :

...

From: Paul Boddie paul@boddie.org.uk The jz4780 has some features which need initialization according to the vendor kernel. Signed-off-by: Paul Boddie paul@boddie.org.uk Signed-off-by: H. Nikolaus Schaller hns@goldelico.com

---

drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index e2df4b085905..605549b316b5 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -66,6 +66,10 @@ struct jz_soc_info { bool needs_dev_clk; bool has_osd; bool map_noncoherent;

• bool has_alpha;
• bool has_pcfg;
• bool has_recover;
• bool has_rgbc; bool use_extended_hwdesc; unsigned int max_width, max_height; const u32 *formats_f0, *formats_f1;

@@ -732,6 +736,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; }

• if (priv->soc_info->has_recover)

• cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN;
  

Did you actually test this? I know that in theory it sounds like something we'd want, but unless there is a proven use for it, it's better to keep it disabled.

...

• /* set use of the 8-word descriptor and OSD foreground usage. */ if (priv->soc_info->use_extended_hwdesc) cfg |= JZ_LCD_CFG_DESCRIPTOR_8;

@@ -1321,6 +1328,25 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) if (soc_info->has_osd) regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);

• if (soc_info->has_alpha)

• regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN);
  

I remember you saying that OSD mode was not yet working on the JZ4780. So I can't see how you could have tested this.

Basically this is all stuff from the vendor kernel under the assumption that they know better than everyone of us. On the other hand this whole patch is sort of optional and we know that the basic milestone to get HDMI working is reached without it. So if you prefer we can drop it for the moment in v5 and leave it for further analysis later.

...

• /* Magic values from the vendor kernel for the priority thresholds. */
• if (soc_info->has_pcfg)

• regmap_write(priv->map, JZ_REG_LCD_PCFG,
  

• 	     JZ_LCD_PCFG_PRI_MODE |
  

• 	     JZ_LCD_PCFG_HP_BST_16 |
  

• 	     (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) |
  

• 	     (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) |
  

• 	     (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET));
  

Unless you add a big comment that explains what these values do and why we do want them, I don't want magic values in here. The fact that the kernel vendor sets this doesn't mean it's needed and/or wanted.

Well, who has a contact within Ingenic?

...

• /* RGB output control may be superfluous. */
• if (soc_info->has_rgbc)

• regmap_write(priv->map, JZ_REG_LCD_RGBC,
  

• 	     JZ_LCD_RGBC_RGB_FORMAT_ENABLE |
  

• 	     JZ_LCD_RGBC_ODD_RGB |
  

• 	     JZ_LCD_RGBC_EVEN_RGB);
  

ingenic-drm only supports RGB output right now, so I guess the RGB_FORMAT_ENABLE bit needs to be set in patch [2/10], otherwise patch [2/10] cannot state that it adds support for the JZ4780, if it doesn't actually work.

The other two bits can be dropped, they are already set in ingenic_drm_encoder_atomic_mode_set().

Ok.

...

• mutex_init(&priv->clk_mutex); priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;

@@ -1484,6 +1510,9 @@ static const struct jz_soc_info jz4740_soc_info = { .needs_dev_clk = true, .has_osd = false, .map_noncoherent = false,

• .has_pcfg = false,
• .has_recover = false,
• .has_rgbc = false, .max_width = 800, .max_height = 600, .formats_f1 = jz4740_formats,

@@ -1496,6 +1525,9 @@ static const struct jz_soc_info jz4725b_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = false,

• .has_pcfg = false,
• .has_recover = false,
• .has_rgbc = false,

This is wrong, the JZ4725B and JZ4770 SoCs both have the RGBC register and the RECOVER bit.

Ok, good to know! Will change.

BR and thanks, Nikolaus

Cheers, -Paul

...

.max_width = 800, .max_height = 600, .formats_f1 = jz4725b_formats_f1, @@ -1509,6 +1541,9 @@ static const struct jz_soc_info jz4770_soc_info = { .needs_dev_clk = false, .has_osd = true, .map_noncoherent = true,

• .has_pcfg = false,
• .has_recover = false,
• .has_rgbc = false, .max_width = 1280, .max_height = 720, .formats_f1 = jz4770_formats_f1,

@@ -1521,6 +1556,10 @@ static const struct jz_soc_info jz4770_soc_info = { static const struct jz_soc_info jz4780_soc_info = { .needs_dev_clk = true, .has_osd = true,

• .has_alpha = true,
• .has_pcfg = true,
• .has_recover = true,
• .has_rgbc = true, .use_extended_hwdesc = true, .max_width = 4096, .max_height = 2048,

-- 2.31.1