v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped.
Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode drm/i915/dp: add helper for checking for UHBR link rate drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates drm/i915/dp: select 128b/132b channel encoding for UHBR rates drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 drm/i915/dp: add HAS_DP20 macro drm/i915/dg2: use 128b/132b transcoder DDI mode drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b drm/i915/dg2: update link training for 128b/132b
drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- include/drm/drm_dp_helper.h | 6 ++ 9 files changed, 180 insertions(+), 49 deletions(-)
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty.
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 6d0f2c447f3b..9b2a2961fca8 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
u8 drm_dp_link_rate_to_bw_code(int link_rate) { - /* Spec says link_bw = link_rate / 0.27Gbps */ - return link_rate / 27000; + switch (link_rate) { + case 1000000: + return DP_LINK_BW_10; + case 1350000: + return DP_LINK_BW_13_5; + case 2000000: + return DP_LINK_BW_20; + default: + /* Spec says link_bw = link_rate / 0.27Gbps */ + return link_rate / 27000; + } } EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
int drm_dp_bw_code_to_link_rate(u8 link_bw) { - /* Spec says link_rate = link_bw * 0.27Gbps */ - return link_bw * 27000; + switch (link_bw) { + case DP_LINK_BW_10: + return 1000000; + case DP_LINK_BW_13_5: + return 1350000; + case DP_LINK_BW_20: + return 2000000; + default: + /* Spec says link_rate = link_bw * 0.27Gbps */ + return link_bw * 27000; + } } EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
On Thu, Sep 09, 2021 at 03:51:53PM +0300, Jani Nikula wrote:
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty.
Cc: dri-devel@lists.freedesktop.org Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 6d0f2c447f3b..9b2a2961fca8 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
u8 drm_dp_link_rate_to_bw_code(int link_rate) {
- /* Spec says link_bw = link_rate / 0.27Gbps */
- return link_rate / 27000;
- switch (link_rate) {
- case 1000000:
return DP_LINK_BW_10;- case 1350000:
return DP_LINK_BW_13_5;- case 2000000:
return DP_LINK_BW_20;- default:
/* Spec says link_bw = link_rate / 0.27Gbps */return link_rate / 27000;- }
} EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
int drm_dp_bw_code_to_link_rate(u8 link_bw) {
- /* Spec says link_rate = link_bw * 0.27Gbps */
- return link_bw * 27000;
- switch (link_bw) {
- case DP_LINK_BW_10:
return 1000000;- case DP_LINK_BW_13_5:
return 1350000;- case DP_LINK_BW_20:
return 2000000;- default:
/* Spec says link_rate = link_bw * 0.27Gbps */return link_bw * 27000;- }
} EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
-- 2.30.2
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap.
v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
Cc: Lyude Paul lyude@redhat.com Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare manasi.d.navare@intel.com Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9b2a2961fca8..2e74b02ed96b 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - u8 dpcd_ext[6]; + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; int ret;
/*
I thought I remembered an issue with this but looked up the previous emails, and it looks like that this change actually should be safe!
Signed-off-by: Lyude Paul lyude@redhat.com
On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap.
v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
Cc: Lyude Paul lyude@redhat.com Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare manasi.d.navare@intel.com Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9b2a2961fca8..2e74b02ed96b 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - u8 dpcd_ext[6]; + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; int ret; /*
…whoops, that was supposed to be:
Reviewed-by: Lyude Paul lyude@redhat.com
On Thu, 2021-09-09 at 12:18 -0400, Lyude Paul wrote:
I thought I remembered an issue with this but looked up the previous emails, and it looks like that this change actually should be safe!
Signed-off-by: Lyude Paul lyude@redhat.com
On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap.
v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
Cc: Lyude Paul lyude@redhat.com Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare manasi.d.navare@intel.com Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9b2a2961fca8..2e74b02ed96b 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - u8 dpcd_ext[6]; + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; int ret; /*
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy { DP_PHY_DPRX,
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
This patch causes a build failure in -next when combined with the AMD tree:
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 ^ 1 error generated.
Perhaps something like this should be applied during the merge of the second tree or maybe this patch should be in a branch that could be shared between the Intel and AMD trees so that this diff could be applied to the AMD tree directly? Not sure what the standard procedure for this is.
Cheers, Nathan
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 234dfbea926a..279863b5c650 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES - + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..8caf9af5ffa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -878,8 +878,6 @@ struct psr_caps { # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) # define DP_DSC_DECODER_COUNT_SHIFT 5 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* TODO - Use DRM header to replace above once available */
Hi Nathan,
On Tue, 21 Sep 2021 15:58:23 -0700 Nathan Chancellor nathan@kernel.org wrote:
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
This patch causes a build failure in -next when combined with the AMD tree:
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 ^ 1 error generated.
Perhaps something like this should be applied during the merge of the second tree or maybe this patch should be in a branch that could be shared between the Intel and AMD trees so that this diff could be applied to the AMD tree directly? Not sure what the standard procedure for this is.
Cheers, Nathan
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 234dfbea926a..279863b5c650 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..8caf9af5ffa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -878,8 +878,6 @@ struct psr_caps { # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) # define DP_DSC_DECODER_COUNT_SHIFT 5 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* TODO - Use DRM header to replace above once available */
Thanks for the heads up. I have applied the above as a merge fix patch until something else happens.
On Tue, 21 Sep 2021, Nathan Chancellor nathan@kernel.org wrote:
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
This patch causes a build failure in -next when combined with the AMD tree:
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 ^ 1 error generated.
Perhaps something like this should be applied during the merge of the second tree or maybe this patch should be in a branch that could be shared between the Intel and AMD trees so that this diff could be applied to the AMD tree directly? Not sure what the standard procedure for this is.
What's in the drm-intel-next branch is changing DRM DP helpers in include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's where this stuff is supposed to land, not in a driver specific file, and especially not if added with just a DP_ prefix.
BR, Jani.
Cheers, Nathan
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 234dfbea926a..279863b5c650 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..8caf9af5ffa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -878,8 +878,6 @@ struct psr_caps { # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) # define DP_DSC_DECODER_COUNT_SHIFT 5 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* TODO - Use DRM header to replace above once available */
+ Harry, Leo
Can you guys get someone to clean this up?
Alex
On Wed, Sep 22, 2021 at 7:10 AM Jani Nikula jani.nikula@intel.com wrote:
On Tue, 21 Sep 2021, Nathan Chancellor nathan@kernel.org wrote:
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare manasi.d.navare@intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com
include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
This patch causes a build failure in -next when combined with the AMD tree:
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 ^ 1 error generated.
Perhaps something like this should be applied during the merge of the second tree or maybe this patch should be in a branch that could be shared between the Intel and AMD trees so that this diff could be applied to the AMD tree directly? Not sure what the standard procedure for this is.
What's in the drm-intel-next branch is changing DRM DP helpers in include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's where this stuff is supposed to land, not in a driver specific file, and especially not if added with just a DP_ prefix.
BR, Jani.
Cheers, Nathan
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 234dfbea926a..279863b5c650 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..8caf9af5ffa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -878,8 +878,6 @@ struct psr_caps { # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) # define DP_DSC_DECODER_COUNT_SHIFT 5 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* TODO - Use DRM header to replace above once available */
-- Jani Nikula, Intel Open Source Graphics Center
[Why] For some reason we're defining DP 2.0 definitions inside our driver. Now that patches to introduce relevant definitions are slated to be merged into drm-next this is causing conflicts.
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here ^ 1 error generated.
[How] Guard all display driver defines with #ifndef for now. Once we pull in the new definitions into amd-staging-drm-next we will follow up and drop definitions from our driver and provide follow-up header updates for any addition DP 2.0 definitions required by our driver.
Signed-off-by: Harry Wentland harry.wentland@amd.com --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 53 ++++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..74b8de616dcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -860,28 +860,71 @@ struct psr_caps { };
#if defined(CONFIG_DRM_AMD_DC_DCN) +#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 +#endif +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 #define DP_FEC_CAPABILITY_1 0x091 +#endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_DSC_CONFIGURATION #define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN #define DP_PHY_SQUARE_PATTERN 0x249 +#endif +#ifndef DP_128b_132b_SUPPORTED_LINK_RATES #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 +#endif +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif +#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 +#endif +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 -# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 -# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) -# define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_PHY_REPEATER_128b_132b_RATES #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif /* TODO - Use DRM header to replace above once available */
union dp_main_line_channel_coding_cap {
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of vswing and pre-emphasis.
Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++ include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 2e74b02ed96b..4d0d1e8e51fa 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI } EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+/* DP 2.0 128b/132b */ +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? + DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : + DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); + u8 l = dp_link_status(link_status, i); + + return (l >> s) & 0xf; +} +EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); + u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index f3a61341011d..3ee0b3ffb8a5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane);
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register conflicts with FDI. Since we have to deal with both meanings in the same code, for different platforms, clarify the macro name so we don't forget.
Bspec: 50493 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 23ef291f7b30..2361f48537b5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { - temp |= TRANS_DDI_MODE_SELECT_FDI; + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { temp |= TRANS_DDI_MODE_SELECT_DP_MST; @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) ret = false; break;
- case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: ret = type == DRM_MODE_CONNECTOR_VGA; break;
@@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); break; case TRANS_DDI_MODE_SELECT_DP_SST: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c2853cc005ee..03a94389c514 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10202,7 +10202,7 @@ enum skl_power_gate { #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) #define TRANS_DDI_BPC_MASK (7 << 20) #define TRANS_DDI_BPC_8 (0 << 20) #define TRANS_DDI_BPC_10 (1 << 20)
On Thu, Sep 09, 2021 at 03:51:57PM +0300, Jani Nikula wrote:
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register conflicts with FDI. Since we have to deal with both meanings in the same code, for different platforms, clarify the macro name so we don't forget.
Bspec: 50493 Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 23ef291f7b30..2361f48537b5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
temp |= TRANS_DDI_MODE_SELECT_FDI;
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;@@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) ret = false; break;
- case TRANS_DDI_MODE_SELECT_FDI:
- case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: ret = type == DRM_MODE_CONNECTOR_VGA; break;
@@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break;
- case TRANS_DDI_MODE_SELECT_FDI:
- case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); break; case TRANS_DDI_MODE_SELECT_DP_SST:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c2853cc005ee..03a94389c514 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10202,7 +10202,7 @@ enum skl_power_gate { #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) #define TRANS_DDI_BPC_MASK (7 << 20) #define TRANS_DDI_BPC_8 (0 << 20)
#define TRANS_DDI_BPC_10 (1 << 20)
2.30.2
Helpful abstraction to avoid duplication.
Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d28bd8c4a8a5..d189d95e4450 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+/* Is link rate UHBR and thus 128b/132b? */ +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->port_clock >= 1000000; +} + /* update sink rates from dpcd */ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a28fff286c21..94b568704b22 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd);
On Thu, Sep 09, 2021 at 03:51:58PM +0300, Jani Nikula wrote:
Helpful abstraction to avoid duplication.
Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d28bd8c4a8a5..d189d95e4450 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+/* Is link rate UHBR and thus 128b/132b? */ +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) +{
- return crtc_state->port_clock >= 1000000;
+}
/* update sink rates from dpcd */ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a28fff286c21..94b568704b22 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); -- 2.30.2
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization.
v2: Use intel_dp_is_uhbr
Reviewed-by: Manasi Navare manasi.d.navare@intel.com # v1 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 508a514c5e37..36b35239da83 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, }
/* - * Pick training pattern for channel equalization. Training pattern 4 for HBR3 - * or for 1.4 devices that support it, training Pattern 3 for HBR2 - * or 1.2 devices that support it, Training Pattern 2 otherwise. + * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 + * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or + * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, { bool source_tps3, sink_tps3, source_tps4, sink_tps4;
+ /* UHBR+ use separate 128b/132b TPS2 */ + if (intel_dp_is_uhbr(crtc_state)) + return DP_TRAINING_PATTERN_2; + /* * Intel platforms that support HBR3 also support TPS4. It is mandatory * for all downstream devices that support HBR3. There are no known eDP
UHBR rates and 128b/132b channel encoding go hand in hand.
v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville)
Reviewed-by: Manasi Navare manasi.d.navare@intel.com # v1 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 36b35239da83..4f116cd32846 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -495,7 +495,8 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, &rate_select, 1);
link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; - link_config[1] = DP_SET_ANSI_8B10B; + link_config[1] = intel_dp_is_uhbr(crtc_state) ? + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
intel_dp->DP |= DP_PORT_EN;
Set the DP 2.0 128b/132b channel encoding for UHBR rates.
v2: Fix UHBR port clock check, use intel_dp_is_uhbr()
Bspec: 54128 Reviewed-by: Manasi Navare manasi.d.navare@intel.com # v1 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2361f48537b5..a7b7e4fafcb3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -408,6 +408,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) return master_transcoder + 1; }
+static void +intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 val = 0; + + if (intel_dp_is_uhbr(crtc_state)) + val = TRANS_DP2_128B132B_CHANNEL_CODING; + + intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); +} + /* * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. * @@ -2376,7 +2390,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_pipe_clock(encoder, crtc_state);
- /* 5.b Not relevant to i915 for now */ + /* 5.b Configure transcoder for DP 2.0 128b/132b */ + intel_ddi_config_transcoder_dp2(encoder, crtc_state);
/* * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
Let's abstract the DP 2.0 feature. Initially just DG2.
Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcd..14416bd789b6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
On Thu, Sep 09, 2021 at 03:52:02PM +0300, Jani Nikula wrote:
Let's abstract the DP 2.0 feature. Initially just DG2.
Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcd..14416bd789b6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2.30.2
128b/132b has a separate transcoder DDI mode, which also requires the MST transport select to be set. Note that we'll use DP MST also for single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value complicates things a bit.
v2: - Use HAS_DP20 abstraction for 128b/132b mode (Ville) - Use intel_dp_is_uhbr() helper
Bspec: 50493 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a7b7e4fafcb3..d2b96b2efdfe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { - temp |= TRANS_DDI_MODE_SELECT_DP_MST; + if (intel_dp_is_uhbr(crtc_state)) + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; + else + temp |= TRANS_DDI_MODE_SELECT_DP_MST; temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
if (DISPLAY_VER(dev_priv) >= 12) { @@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) break;
case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - ret = type == DRM_MODE_CONNECTOR_VGA; + if (HAS_DP20(dev_priv)) + /* 128b/132b */ + ret = false; + else + /* FDI */ + ret = type == DRM_MODE_CONNECTOR_VGA; break;
default: @@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if ((tmp & port_mask) != ddi_select) continue;
- if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == - TRANS_DDI_MODE_SELECT_DP_MST) + if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || + (HAS_DP20(dev_priv) && + (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) mst_pipe_mask |= BIT(p);
*pipe_mask |= BIT(p); @@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); - break; case TRANS_DDI_MODE_SELECT_DP_SST: if (encoder->type == INTEL_OUTPUT_EDP) pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); @@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); break; + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: + if (!HAS_DP20(dev_priv)) { + /* FDI */ + pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); + break; + } + fallthrough; /* 128b/132b */ case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); pipe_config->lane_count =
On Thu, Sep 09, 2021 at 03:52:03PM +0300, Jani Nikula wrote:
128b/132b has a separate transcoder DDI mode, which also requires the MST transport select to be set. Note that we'll use DP MST also for single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value complicates things a bit.
v2:
- Use HAS_DP20 abstraction for 128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper
Bspec: 50493 Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a7b7e4fafcb3..d2b96b2efdfe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
if (intel_dp_is_uhbr(crtc_state))temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;elsetemp |= TRANS_DDI_MODE_SELECT_DP_MST;temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) break;
case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
ret = type == DRM_MODE_CONNECTOR_VGA;
if (HAS_DP20(dev_priv))/* 128b/132b */ret = false;else/* FDI */ret = type == DRM_MODE_CONNECTOR_VGA;break;
default:
@@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if ((tmp & port_mask) != ddi_select) continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==TRANS_DDI_MODE_SELECT_DP_MST)
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||(HAS_DP20(dev_priv) &&(tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) mst_pipe_mask |= BIT(p);*pipe_mask |= BIT(p);
@@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break;
- case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);break;@@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); break;
- case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
if (!HAS_DP20(dev_priv)) {/* FDI */pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);break;}fallthrough; /* 128b/132b */-- 2.30.2
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128 Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
clear_act_sent(encoder, pipe_config);
+ if (intel_dp_is_uhbr(pipe_config)) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); + + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); + } + intel_ddi_enable_transcoder_func(encoder, pipe_config);
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote:
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128 Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
clear_act_sent(encoder, pipe_config);
if (intel_dp_is_uhbr(pipe_config)) {
const struct drm_display_mode *adjusted_mode =&pipe_config->hw.adjusted_mode;u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));}
intel_ddi_enable_transcoder_func(encoder, pipe_config);
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
-- 2.30.2
On Fri, 17 Sep 2021, Ville Syrjälä ville.syrjala@linux.intel.com wrote:
On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote:
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128 Signed-off-by: Jani Nikula jani.nikula@intel.com
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Thanks for the reviews, pushed up to and including this one.
BR, Jani.
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
clear_act_sent(encoder, pipe_config);
if (intel_dp_is_uhbr(pipe_config)) {
const struct drm_display_mode *adjusted_mode =&pipe_config->hw.adjusted_mode;u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));}
intel_ddi_enable_transcoder_func(encoder, pipe_config);
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
-- 2.30.2
The 128b/132b channel coding link training uses more straightforward TX FFE preset values.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
Signed-off-by: Jani Nikula jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++- .../drm/i915/display/intel_dp_link_training.c | 86 +++++++++++++------ 2 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d2b96b2efdfe..5805bdd6e1f2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1398,11 +1398,16 @@ static int translate_signal_level(struct intel_dp *intel_dp, static int intel_ddi_dp_level(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - u8 train_set = intel_dp->train_set[0]; - u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | - DP_TRAIN_PRE_EMPHASIS_MASK); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK; + } else { + u8 train_set = intel_dp->train_set[0]; + u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | + DP_TRAIN_PRE_EMPHASIS_MASK);
- return translate_signal_level(intel_dp, signal_levels); + return translate_signal_level(intel_dp, signal_levels); + } }
static void diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4f116cd32846..c10f165d1aa2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,6 +301,24 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; }
+static void intel_dp_128b132b_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + u8 tx_ffe = 0; + + /* + * FIXME: We'll want independent presets for each lane. See also + * intel_ddi_dp_level() and intel_snps_phy_ddi_vswing_sequence(). + */ + for (lane = 0; lane < crtc_state->lane_count; lane++) + tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); + + for (lane = 0; lane < crtc_state->lane_count; lane++) + intel_dp->train_set[lane] = tx_ffe; +} + void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -313,6 +331,11 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, u8 voltage_max; u8 preemph_max;
+ if (intel_dp_is_uhbr(crtc_state)) { + intel_dp_128b132b_adjust_train(intel_dp, crtc_state, link_status); + return; + } + for (lane = 0; lane < crtc_state->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -402,14 +425,21 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, u8 train_set = intel_dp->train_set[0]; char phy_name[10];
- drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + drm_dbg_kms(&dev_priv->drm, "%s: Using 128b/132b TX FFE preset %u\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TX_FFE_PRESET_VALUE_MASK); + } else { + drm_dbg_kms(&dev_priv->drm, "%s: Using 8b/10b vswing level %d%s, pre-emphasis level %d%s\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); + }
if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) intel_dp->set_signal_levels(intel_dp, crtc_state); @@ -565,18 +595,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return true; }
- if (voltage_tries == 5) { - drm_dbg_kms(&i915->drm, - "Same voltage tried 5 times\n"); - return false; - } + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if (voltage_tries == 5) { + drm_dbg_kms(&i915->drm, + "Same voltage tried 5 times\n"); + return false; + }
- if (max_vswing_reached) { - drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); - return false; - } + if (max_vswing_reached) { + drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); + return false; + }
- voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + }
/* Update training set as requested by target */ intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, @@ -587,14 +620,17 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return false; }
- if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == - voltage) - ++voltage_tries; - else - voltage_tries = 1; + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == + voltage) + ++voltage_tries; + else + voltage_tries = 1;
- if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) - max_vswing_reached = true; + if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) + max_vswing_reached = true; + }
} drm_err(&i915->drm,
On Thu, 09 Sep 2021, Jani Nikula jani.nikula@intel.com wrote:
v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped.
Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
Maarten, Maxime, Thomas, can I get an ack to merge these four patches via drm-intel please, or would you prefer a topic branch instead?
Thanks, Jani.
drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode drm/i915/dp: add helper for checking for UHBR link rate drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates drm/i915/dp: select 128b/132b channel encoding for UHBR rates drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 drm/i915/dp: add HAS_DP20 macro drm/i915/dg2: use 128b/132b transcoder DDI mode drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b drm/i915/dg2: update link training for 128b/132b
drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- include/drm/drm_dp_helper.h | 6 ++ 9 files changed, 180 insertions(+), 49 deletions(-)
On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote:
On Thu, 09 Sep 2021, Jani Nikula jani.nikula@intel.com wrote:
v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped.
Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
Maarten, Maxime, Thomas, can I get an ack to merge these four patches via drm-intel please, or would you prefer a topic branch instead?
Yes, you can merge them through drm-intel
Maxime
On Fri, 17 Sep 2021, Maxime Ripard maxime@cerno.tech wrote:
On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote:
On Thu, 09 Sep 2021, Jani Nikula jani.nikula@intel.com wrote:
v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped.
Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
Maarten, Maxime, Thomas, can I get an ack to merge these four patches via drm-intel please, or would you prefer a topic branch instead?
Yes, you can merge them through drm-intel
Thanks, I've done that.
BR, Jani.
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