So far, the binding and driver have relied on the fact that the H6 clocks are both a prefix and a subset of the R40 clocks. This allows them to share the clocks/clock-names items and the clock-output-names order between the hardware variants.

However, the D1 hardware has TCON TV0 and DSI, but no TCON TV1. This cannot be supported by the existing scheme because it puts a gap in the middle of the item lists. To prepare for adding D1 support, use separate lists for variants with different combinations of clocks.

Reviewed-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org Signed-off-by: Samuel Holland samuel@sholland.org ---

(no changes since v1)

.../display/allwinner,sun8i-r40-tcon-top.yaml | 111 +++++++++++------- 1 file changed, 67 insertions(+), 44 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 61ef7b337218..784b267635fb 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -48,31 +48,15 @@ properties:

clocks: minItems: 2 - items: - - description: The TCON TOP interface clock - - description: The TCON TOP TV0 clock - - description: The TCON TOP TVE0 clock - - description: The TCON TOP TV1 clock - - description: The TCON TOP TVE1 clock - - description: The TCON TOP MIPI DSI clock + maxItems: 6

clock-names: minItems: 2 - items: - - const: bus - - const: tcon-tv0 - - const: tve0 - - const: tcon-tv1 - - const: tve1 - - const: dsi + maxItems: 6

clock-output-names: minItems: 1 maxItems: 3 - description: > - The first item is the name of the clock created for the TV0 - channel, the second item is the name of the TCON TV1 channel - clock and the third one is the name of the DSI channel clock.

resets: maxItems: 1 @@ -129,32 +113,71 @@ required:

additionalProperties: false

-if: - properties: - compatible: - contains: - const: allwinner,sun50i-h6-tcon-top - -then: - properties: - clocks: - maxItems: 2 - - clock-output-names: - maxItems: 1 - -else: - properties: - clocks: - minItems: 6 - - clock-output-names: - minItems: 3 - - ports: - required: - - port@2 - - port@3 +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-r40-tcon-top + + then: + properties: + clocks: + minItems: 6 + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + - description: The TCON TOP TVE0 clock + - description: The TCON TOP TV1 clock + - description: The TCON TOP TVE1 clock + - description: The TCON TOP MIPI DSI clock + + clock-names: + minItems: 6 + items: + - const: bus + - const: tcon-tv0 + - const: tve0 + - const: tcon-tv1 + - const: tve1 + - const: dsi + + clock-output-names: + minItems: 3 + items: + - description: TCON TV0 output clock name + - description: TCON TV1 output clock name + - description: DSI output clock name + + ports: + required: + - port@2 + - port@3 + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-tcon-top + + then: + properties: + clocks: + maxItems: 2 + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + + clock-names: + maxItems: 2 + items: + - const: bus + - const: tcon-tv0 + + clock-output-names: + maxItems: 1 + items: + - description: TCON TV0 output clock name

examples: - |

readsb/writesb are unavailable on some architectures. In preparation for removing the Kconfig architecture dependency, switch to the equivalent but more portable ioread/write8_rep helpers.

Reported-by: kernel test robot lkp@intel.com Signed-off-by: Samuel Holland samuel@sholland.org ---

Changes in v2: - New patch: I/O helper portability

drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c index b66fa27fe6ea..c7d7e9fff91c 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c @@ -56,9 +56,9 @@ static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) return -EIO;

if (read) - readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); + ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); else - writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); + iowrite8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);

/* Clear FIFO request bit by forcing a write to that bit */ regmap_field_force_write(hdmi->field_ddc_int_status,

From: Jernej Skrabec jernej.skrabec@gmail.com

This optional callback is useful for setting properties which depends only on current mode. Such properties are width, height and interlaced output.

These properties are currently set in update layer callback for primary plane which is less than ideal. More about that in follow up patches, which will migrate that code to this newly defined callback.

Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com Signed-off-by: Samuel Holland samuel@sholland.org ---

Changes in v2: - Use Jernej's patches for mixer mode setting.

drivers/gpu/drm/sun4i/sun4i_crtc.c | 1 + drivers/gpu/drm/sun4i/sunxi_engine.h | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c index 45d9eb552d86..c06d7cd45388 100644 --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c @@ -146,6 +146,7 @@ static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc) struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);

sun4i_tcon_mode_set(scrtc->tcon, encoder, mode); + sunxi_engine_mode_set(scrtc->engine, mode); }

static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h index 548710a936d5..ec8cf9b2bda4 100644 --- a/drivers/gpu/drm/sun4i/sunxi_engine.h +++ b/drivers/gpu/drm/sun4i/sunxi_engine.h @@ -9,6 +9,7 @@ struct drm_plane; struct drm_device; struct drm_crtc_state; +struct drm_display_mode;

struct sunxi_engine;

@@ -108,6 +109,17 @@ struct sunxi_engine_ops { * This function is optional. */ void (*vblank_quirk)(struct sunxi_engine *engine); + + /** + * @mode_set + * + * This callback is used to set mode related parameters + * like interlacing, screen size, etc. once per mode set. + * + * This function is optional. + */ + void (*mode_set)(struct sunxi_engine *engine, + const struct drm_display_mode *mode); };

/** @@ -181,4 +193,19 @@ sunxi_engine_disable_color_correction(struct sunxi_engine *engine) if (engine->ops && engine->ops->disable_color_correction) engine->ops->disable_color_correction(engine); } + +/** + * sunxi_engine_mode_set - Inform engine of a new mode + * @engine: pointer to the engine + * @mode: new mode + * + * Engine can use this functionality to set specifics once per mode change. + */ +static inline void +sunxi_engine_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) +{ + if (engine->ops && engine->ops->mode_set) + engine->ops->mode_set(engine, mode); +} #endif /* _SUNXI_ENGINE_H_ */

From: Jernej Skrabec jernej.skrabec@gmail.com

Newly introduced mode_set callback in engine structure is a much better place for setting mixer output size and interlace mode for the following reasons: 1. Aforementioned properties change only when mode changes, so it's enough to be set only once per mode set. Currently it's done whenever properties of primary plane are changed. 2. It's assumed that primary plane will always cover whole screen. While this is true most of the time, it's not always. DE2/3 planes are universal and mostly equal in functionality. There is no reason to add artificial limitation to primary planes. 3. The current code only works for UI layers, but some mixers do not have any UI layers.

Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com [Samuel: update commit message] Signed-off-by: Samuel Holland samuel@sholland.org ---

Changes in v2: - Use Jernej's patches for mixer mode setting.

drivers/gpu/drm/sun4i/sun8i_mixer.c | 30 ++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 30 -------------------------- 2 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index f5e8aeaa3cdf..6b1711a9a71f 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -298,9 +298,39 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, return planes; }

+static void sun8i_mixer_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) +{ + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); + u32 bld_base, size, val; + bool interlaced; + + bld_base = sun8i_blender_base(mixer); + interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); + + DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", + mode->hdisplay, mode->vdisplay); + + regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + + if (interlaced) + val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; + else + val = 0; + + regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), + SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); + + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", + interlaced ? "on" : "off"); +} + static const struct sunxi_engine_ops sun8i_engine_ops = { .commit = sun8i_mixer_commit, .layers_init = sun8i_layers_init, + .mode_set = sun8i_mixer_mode_set, };

static const struct regmap_config sun8i_mixer_regmap_config = { diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 7845c2a53a7f..4632dea2dc1e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -120,36 +120,6 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, insize = SUN8I_MIXER_SIZE(src_w, src_h); outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);

- if (plane->type == DRM_PLANE_TYPE_PRIMARY) { - bool interlaced = false; - u32 val; - - DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", - dst_w, dst_h); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_GLOBAL_SIZE, - outsize); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize); - - if (state->crtc) - interlaced = state->crtc->state->adjusted_mode.flags - & DRM_MODE_FLAG_INTERLACE; - - if (interlaced) - val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; - else - val = 0; - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTCTL(bld_base), - SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, - val); - - DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", - interlaced ? "on" : "off"); - } - /* Set height and width */ DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", state->src.x1 >> 16, state->src.y1 >> 16);

D1 changes the MMIO offsets for the CSC blocks in the first mixer. The mixers' ccsc property is used as an index into the ccsc_base array. Use an enumeration to describe this index, and add the new set of offsets.

Signed-off-by: Samuel Holland samuel@sholland.org ---

Changes in v2: - Use an enumeration for the ccsc value.

drivers/gpu/drm/sun4i/sun8i_csc.c | 7 ++++--- drivers/gpu/drm/sun4i/sun8i_csc.h | 1 + drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +++++++++--------- drivers/gpu/drm/sun4i/sun8i_mixer.h | 14 ++++++++++---- 4 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c index 9bd62de0c288..58480d8e4f70 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -8,9 +8,10 @@ #include "sun8i_csc.h" #include "sun8i_mixer.h"

-static const u32 ccsc_base[2][2] = { - {CCSC00_OFFSET, CCSC01_OFFSET}, - {CCSC10_OFFSET, CCSC11_OFFSET}, +static const u32 ccsc_base[][2] = { + [CCSC_MIXER0_LAYOUT] = {CCSC00_OFFSET, CCSC01_OFFSET}, + [CCSC_MIXER1_LAYOUT] = {CCSC10_OFFSET, CCSC11_OFFSET}, + [CCSC_D1_MIXER0_LAYOUT] = {CCSC00_OFFSET, CCSC01_D1_OFFSET}, };

/* diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h index 022cafa6c06c..828b86fd0cab 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.h +++ b/drivers/gpu/drm/sun4i/sun8i_csc.h @@ -13,6 +13,7 @@ struct sun8i_mixer; /* VI channel CSC units offsets */ #define CCSC00_OFFSET 0xAA050 #define CCSC01_OFFSET 0xFA050 +#define CCSC01_D1_OFFSET 0xFA000 #define CCSC10_OFFSET 0xA0000 #define CCSC11_OFFSET 0xF0000

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 6b1711a9a71f..4ce593c99807 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -564,7 +564,7 @@ static int sun8i_mixer_remove(struct platform_device *pdev) }

static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .scaler_mask = 0xf, .scanline_yuv = 2048, .ui_num = 3, @@ -572,7 +572,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { };

static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { - .ccsc = 1, + .ccsc = CCSC_MIXER1_LAYOUT, .scaler_mask = 0x3, .scanline_yuv = 2048, .ui_num = 1, @@ -580,7 +580,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { };

static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .mod_rate = 432000000, .scaler_mask = 0xf, .scanline_yuv = 2048, @@ -589,7 +589,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { };

static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 2048, @@ -598,7 +598,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { };

static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { - .ccsc = 1, + .ccsc = CCSC_MIXER1_LAYOUT, .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, @@ -611,12 +611,12 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { .ui_num = 1, .scaler_mask = 0x3, .scanline_yuv = 2048, - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .mod_rate = 150000000, };

static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 4096, @@ -625,7 +625,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { };

static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { - .ccsc = 1, + .ccsc = CCSC_MIXER1_LAYOUT, .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, @@ -634,7 +634,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { };

static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { - .ccsc = 0, + .ccsc = CCSC_MIXER0_LAYOUT, .is_de3 = true, .mod_rate = 600000000, .scaler_mask = 0xf, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index 5b3fbee18671..85c94884fb9a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -141,6 +141,15 @@ #define SUN50I_MIXER_CDC0_EN 0xd0000 #define SUN50I_MIXER_CDC1_EN 0xd8000

+enum { + /* First mixer or second mixer with VEP support. */ + CCSC_MIXER0_LAYOUT, + /* Second mixer without VEP support. */ + CCSC_MIXER1_LAYOUT, + /* First mixer with the MMIO layout found in the D1 SoC. */ + CCSC_D1_MIXER0_LAYOUT, +}; + /** * struct sun8i_mixer_cfg - mixer HW configuration * @vi_num: number of VI channels @@ -149,10 +158,7 @@ * First, scaler supports for VI channels is defined and after that, scaler * support for UI channels. For example, if mixer has 2 VI channels without * scaler and 2 UI channels with scaler, bitmask would be 0xC. - * @ccsc: select set of CCSC base addresses - * Set value to 0 if this is first mixer or second mixer with VEP support. - * Set value to 1 if this is second mixer without VEP support. Other values - * are invalid. + * @ccsc: select set of CCSC base addresses from the enumeration above. * @mod_rate: module clock rate that needs to be set in order to have * a functional block. * @is_de3: true, if this is next gen display engine 3.0, false otherwise.

D1 has a TCON TOP with TCON TV0 and DSI, but no TCON TV1. This puts the DSI clock name at index 1 in clock-output-names. Support this by only incrementing the index for clocks that are actually supported.

Signed-off-by: Samuel Holland samuel@sholland.org ---

(no changes since v1)

drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index 1b9b8b48f4a7..da97682b6835 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -189,22 +189,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, * if TVE is active on each TCON TV. If it is, mux should be switched * to TVE clock parent. */ + i = 0; clk_data->hws[CLK_TCON_TOP_TV0] = sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV0_GATE, 0); + TCON_TOP_TCON_TV0_GATE, i++);

if (quirks->has_tcon_tv1) clk_data->hws[CLK_TCON_TOP_TV1] = sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV1_GATE, 1); + TCON_TOP_TCON_TV1_GATE, i++);

if (quirks->has_dsi) clk_data->hws[CLK_TCON_TOP_DSI] = sun8i_tcon_top_register_gate(dev, "dsi", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_DSI_GATE, 2); + TCON_TOP_TCON_DSI_GATE, i++);

for (i = 0; i < CLK_NUM; i++) if (IS_ERR(clk_data->hws[i])) { @@ -272,6 +273,10 @@ static const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = { .has_dsi = true, };

+static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks = { + .has_dsi = true, +}; + static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = { /* Nothing special */ }; @@ -282,6 +287,10 @@ const struct of_device_id sun8i_tcon_top_of_table[] = { .compatible = "allwinner,sun8i-r40-tcon-top", .data = &sun8i_r40_tcon_top_quirks }, + { + .compatible = "allwinner,sun20i-d1-tcon-top", + .data = &sun20i_d1_tcon_top_quirks + }, { .compatible = "allwinner,sun50i-h6-tcon-top", .data = &sun50i_h6_tcon_top_quirks

Now that the various blocks in the D1 display engine pipeline are supported, we can enable the overall engine.

Acked-by: Jernej Skrabec jernej.skrabec@gmail.com Signed-off-by: Samuel Holland samuel@sholland.org ---

(no changes since v1)

drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 6a9ba8a77c77..275f7e4a03ae 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -418,6 +418,7 @@ static const struct of_device_id sun4i_drv_of_table[] = { { .compatible = "allwinner,sun8i-r40-display-engine" }, { .compatible = "allwinner,sun8i-v3s-display-engine" }, { .compatible = "allwinner,sun9i-a80-display-engine" }, + { .compatible = "allwinner,sun20i-d1-display-engine" }, { .compatible = "allwinner,sun50i-a64-display-engine" }, { .compatible = "allwinner,sun50i-h6-display-engine" }, { }