On Fri, Jul 23, 2021 at 05:10:45PM -0700, Lucas De Marchi wrote:

We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we were not handling GLK correctly since that has GRAPHICS_VER == 9, but DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER which makes it more in line with Bspec.

Even though the Bspec has an exception for RKL in TGL_DFSM_PIPE_D_DISABLE, we don't have to do anything as the bit has disable semantic and RKL doesn't have pipe D.

Bspec: 50075, 7548 Fixes: 2b5a4562edd0 ("drm/i915/display: Simplify GLK display version tests") Cc: Matt Roper matthew.d.roper@intel.com Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Matt Roper matthew.d.roper@intel.com

---

drivers/gpu/drm/i915/intel_device_info.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d5cf5977938a..99b51c292942 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -335,7 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->pipe_mask &= ~BIT(PIPE_C); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); }

• } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {

• } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);

  if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {

@@ -350,7 +350,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->pipe_mask &= ~BIT(PIPE_C); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); }

• if (GRAPHICS_VER(dev_priv) >= 12 &&
  

• if (DISPLAY_VER(dev_priv) >= 12 &&
  

  (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { info->pipe_mask &= ~BIT(PIPE_D); info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);

@@ -362,10 +363,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) info->display.has_fbc = 0;

• if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
  

• if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
  info->display.has_dmc = 0;
  
  

• if (GRAPHICS_VER(dev_priv) >= 10 &&
  

• if (DISPLAY_VER(dev_priv) >= 10 &&
  

  (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) info->display.has_dsc = 0; }

-- 2.31.1

On Sat, Jul 24, 2021 at 11:12:07AM -0700, Matt Roper wrote:

On Fri, Jul 23, 2021 at 05:10:48PM -0700, Lucas De Marchi wrote:

...

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need any checks and supporting code for CNL. Remove code and rename functions/macros accordingly.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++----------------- drivers/gpu/drm/i915/i915_reg.h | 4 +- 2 files changed, 18 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index ff35c29508d5..34fa4130d5c4 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = { {} };

-static const struct intel_cdclk_vals cnl_cdclk_table[] = {

• { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
• { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
• { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
• { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
• { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
• { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
• {}

-};

static const struct intel_cdclk_vals icl_cdclk_table[] = { { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, @@ -1339,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk) return DIV_ROUND_UP(cdclk, 25000); }

-static u8 cnl_calc_voltage_level(int cdclk) -{

• if (cdclk > 336000)

• return 2;
  

• else if (cdclk > 168000)

• return 1;
  

• else

• return 0;
  

-}

static u8 icl_calc_voltage_level(int cdclk) { if (cdclk > 556800) @@ -1383,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk) return 0; }

-static void cnl_readout_refclk(struct drm_i915_private *dev_priv,

• 	       struct intel_cdclk_config *cdclk_config)
  

-{

• if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)

• cdclk_config->ref = 24000;
  

• else

• cdclk_config->ref = 19200;
  

-}

static void icl_readout_refclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { @@ -1422,8 +1392,6 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, cdclk_config->ref = 38400; else if (DISPLAY_VER(dev_priv) >= 11) icl_readout_refclk(dev_priv, cdclk_config);

• else if (IS_CANNONLAKE(dev_priv))

• cnl_readout_refclk(dev_priv, cdclk_config);
  

  else cdclk_config->ref = 19200;

@@ -1439,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, }

/*

• * CNL+ have the ratio directly in the PLL enable register, gen9lp had
  

• * it in a separate PLL control register.
  

• * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
  

• * gen9lp had it in a separate PLL control register.
  

  */

• if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

• ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
  

• if (DISPLAY_VER(dev_priv) >= 11)

• ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
  

  else ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;

@@ -1530,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) dev_priv->cdclk.hw.vco = vco; }

-static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) +static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) { intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE, 0); @@ -1542,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco = 0; }

-static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) +static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) { int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); u32 val;

• val = CNL_CDCLK_PLL_RATIO(ratio);

• val = ICL_CDCLK_PLL_RATIO(ratio); intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);

  val |= BXT_DE_PLL_PLL_ENABLE;

@@ -1566,7 +1534,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) u32 val;

/* Write PLL ratio without disabling */

• val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;

• val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);

  /* Submit freq change request */

@@ -1635,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int ret;

/* Inform power controller of upcoming frequency change. */

• if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

• if (DISPLAY_VER(dev_priv) >= 11) ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE,

@@ -1659,13 +1627,13 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { if (dev_priv->cdclk.hw.vco != vco) adlp_cdclk_pll_crawl(dev_priv, vco);

• } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {

• } else if (DISPLAY_VER(dev_priv) >= 11) { if (dev_priv->cdclk.hw.vco != 0 && dev_priv->cdclk.hw.vco != vco)

• 	cnl_cdclk_pll_disable(dev_priv);
  

• 	icl_cdclk_pll_disable(dev_priv);
  
  

  if (dev_priv->cdclk.hw.vco != vco)

• 	cnl_cdclk_pll_enable(dev_priv, vco);
  

• 	icl_cdclk_pll_enable(dev_priv, vco);
  

  } else { if (dev_priv->cdclk.hw.vco != 0 && dev_priv->cdclk.hw.vco != vco)

@@ -1691,7 +1659,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, if (pipe != INVALID_PIPE) intel_wait_for_vblank(dev_priv, pipe);

• if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {

• if (DISPLAY_VER(dev_priv) >= 11) { ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, cdclk_config->voltage_level); } else {

@@ -1716,7 +1684,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,

intel_update_cdclk(dev_priv);

• if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

• if (DISPLAY_VER(dev_priv) >= 11) /*
  • Can't read out the voltage level :(
  • Let's just assume everything is as expected.

@@ -2125,7 +2093,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) crtc_state->port_clock >= 540000 && crtc_state->lane_count == 4) { if (DISPLAY_VER(dev_priv) == 10) {

• 	/* Display WA #1145: glk,cnl */
  

• 	/* Display WA #1145: glk */
  min_cdclk = max(316800, min_cdclk);
  

  } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { /* Display WA #1144: skl,bxt */

@@ -2246,7 +2214,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)

/*

• Account for port clock min voltage level requirements.

• • This only really does something on CNL+ but can be

• • This only really does something on DISPLA_VER >= 11 but can be
  • called on earlier platforms as well.
  • Note that this functions assumes that 0 is

@@ -2660,8 +2628,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv->max_cdclk_freq = 648000; else dev_priv->max_cdclk_freq = 652800;

• } else if (IS_CANNONLAKE(dev_priv)) {

• dev_priv->max_cdclk_freq = 528000;
  

  } else if (IS_GEMINILAKE(dev_priv)) { dev_priv->max_cdclk_freq = 316800; } else if (IS_BROXTON(dev_priv)) {

@@ -2925,12 +2891,6 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = icl_calc_voltage_level; dev_priv->cdclk.table = icl_cdclk_table;

• } else if (IS_CANNONLAKE(dev_priv)) {

• dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
  

• dev_priv->display.set_cdclk = bxt_set_cdclk;
  

• dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
  

• dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
  

• dev_priv->cdclk.table = cnl_cdclk_table;
  

  } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.set_cdclk = bxt_set_cdclk;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e1392028184..6a894ffd91e1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11016,8 +11016,8 @@ enum skl_power_gate { #define BXT_DE_PLL_LOCK (1 << 30) #define BXT_DE_PLL_FREQ_REQ (1 << 23) #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) -#define CNL_CDCLK_PLL_RATIO(x) (x) -#define CNL_CDCLK_PLL_RATIO_MASK 0xff +#define ICL_CDCLK_PLL_RATIO(x) (x) +#define ICL_CDCLK_PLL_RATIO_MASK 0xff

We could take this opportunity to switch to REG_GENMASK, REG_FIELD_PREP here. Otherwise,

Reviewed-by: Matt Roper matthew.d.roper@intel.com

I'd rather have a single big patch converting all of i915_reg.h

We are doing this conversion piece by piece for a long time and it seems we are never going to achieve the desired end result.

todo++

thanks Lucas De Marchi

...

/* GEN9 DC */

#define DC_STATE_EN _MMIO(0x45504)

2.31.1

-- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795

On Fri, Jul 23, 2021 at 05:10:49PM -0700, Lucas De Marchi wrote:

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need any checks and supporting code for CNL. For DISPLAY_VER >= 11, ilk_load_csc_matrix() is not used, so make it handle GLK only.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Matt Roper matthew.d.roper@intel.com

---

drivers/gpu/drm/i915/display/intel_color.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dab892d2251b..afcb4bf3826c 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -305,13 +305,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) ilk_csc_postoff_limited_range); } else if (crtc_state->csc_enable) { /*

•  * On GLK+ both pipe CSC and degamma LUT are controlled
  

•  * On GLK both pipe CSC and degamma LUT are controlled
  

  • by csc_enable. Hence for the cases where the degama
  • LUT is needed but CSC is not we need to load an
  • identity matrix.
  */

• drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
  

• 	    !IS_GEMINILAKE(dev_priv));
  

• drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
  
  

  ilk_update_pipe_csc(crtc, ilk_csc_off_zero, ilk_csc_coeff_identity,

-- 2.31.1

On Fri, Jul 23, 2021 at 05:10:50PM -0700, Lucas De Marchi wrote:

The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have combo phys. We don't need to handle CNL explicitly in intel_combo_phy.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Matt Roper matthew.d.roper@intel.com

---

.../gpu/drm/i915/display/intel_combo_phy.c | 106 ++++-------------- 1 file changed, 20 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 487c54cd5982..bacdf8a16bcb 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -23,9 +23,9 @@ enum { PROCMON_1_05V_DOT_1, };

-static const struct cnl_procmon { +static const struct icl_procmon { u32 dw1, dw9, dw10; -} cnl_procmon_values[] = { +} icl_procmon_values[] = { [PROCMON_0_85V_DOT_0] = { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, [PROCMON_0_95V_DOT_0] = @@ -38,15 +38,10 @@ static const struct cnl_procmon { { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, };

-/*

• • CNL has just one set of registers, while gen11 has a set for each combo PHY.
• • The CNL registers are equivalent to the gen11 PHY A registers, that's why we
• • call the ICL macros even though the function has CNL on its name.
• */

-static const struct cnl_procmon * -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) +static const struct icl_procmon * +icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) {

• const struct cnl_procmon *procmon;

• const struct icl_procmon *procmon; u32 val;

  val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));

@@ -55,32 +50,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) MISSING_CASE(val); fallthrough; case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:

• procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
  

• procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
  

  break; case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:

• procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
  

• procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
  

  break; case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:

• procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
  

• procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
  

  break; case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:

• procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
  

• procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
  

  break; case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:

• procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
  

• procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
  

  break; }

  return procmon;

}

-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, +static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) {

• const struct cnl_procmon *procmon;

• const struct icl_procmon *procmon; u32 val;

• procmon = cnl_get_procmon_ref_values(dev_priv, phy);

• procmon = icl_get_procmon_ref_values(dev_priv, phy);

  val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); val &= ~((0xff << 16) | 0xff);

@@ -109,13 +104,13 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv, return true; }

-static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, +static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) {

• const struct cnl_procmon *procmon;

• const struct icl_procmon *procmon; bool ret;

• procmon = cnl_get_procmon_ref_values(dev_priv, phy);

• procmon = icl_get_procmon_ref_values(dev_priv, phy);

  ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), (0xff << 16) | 0xff, procmon->dw1);

@@ -127,61 +122,6 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, return ret; }

-static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) -{

• return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&

• (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
  

-}

-static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) -{

• enum phy phy = PHY_A;
• bool ret;
• if (!cnl_combo_phy_enabled(dev_priv))

• return false;
  

• ret = cnl_verify_procmon_ref_values(dev_priv, phy);
• ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,

• 	     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
  

• return ret;

-}

-static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) -{

• u32 val;
• val = intel_de_read(dev_priv, CHICKEN_MISC_2);
• val &= ~CNL_COMP_PWR_DOWN;
• intel_de_write(dev_priv, CHICKEN_MISC_2, val);
• /* Dummy PORT_A to get the correct CNL register from the ICL macro */
• cnl_set_procmon_ref_values(dev_priv, PHY_A);
• val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
• val |= COMP_INIT;
• intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
• val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
• val |= CL_POWER_DOWN_ENABLE;
• intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);

-}

-static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) -{

• u32 val;
• if (!cnl_combo_phy_verify_state(dev_priv))

• drm_warn(&dev_priv->drm,
  

• 	 "Combo PHY HW state changed unexpectedly.\n");
  

• val = intel_de_read(dev_priv, CHICKEN_MISC_2);
• val |= CNL_COMP_PWR_DOWN;
• intel_de_write(dev_priv, CHICKEN_MISC_2, val);

-}

static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) { /* @@ -291,7 +231,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, DCC_MODE_SELECT_CONTINUOSLY); }

• ret &= cnl_verify_procmon_ref_values(dev_priv, phy);

• ret &= icl_verify_procmon_ref_values(dev_priv, phy);

  if (phy_is_master(dev_priv, phy)) { ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),

@@ -415,7 +355,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); }

• cnl_set_procmon_ref_values(dev_priv, phy);
  

• icl_set_procmon_ref_values(dev_priv, phy);
  
  

  if (phy_is_master(dev_priv, phy)) { val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));

@@ -474,16 +414,10 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)

void intel_combo_phy_init(struct drm_i915_private *i915) {

• if (DISPLAY_VER(i915) >= 11)

• icl_combo_phys_init(i915);
  

• else if (IS_CANNONLAKE(i915))

• cnl_combo_phys_init(i915);
  

• icl_combo_phys_init(i915);

}

void intel_combo_phy_uninit(struct drm_i915_private *i915) {

• if (DISPLAY_VER(i915) >= 11)

• icl_combo_phys_uninit(i915);
  

• else if (IS_CANNONLAKE(i915))

• cnl_combo_phys_uninit(i915);
  

• icl_combo_phys_uninit(i915);

}

2.31.1

On Fri, Jul 23, 2021 at 05:10:51PM -0700, Lucas De Marchi wrote:

No need for special CNL handling as there is no real platform with that configuration.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Matt Roper matthew.d.roper@intel.com

---

drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 448c4d99ac35..254e67141a77 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; }

• if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))

• if (DISPLAY_VER(dev_priv) >= 11) drm_crtc_create_scaling_filter_property(&crtc->base, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));

-- 2.31.1

On Fri, Jul 23, 2021 at 05:10:52PM -0700, Lucas De Marchi wrote:

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_ddi.c.

Remove code and rename functions/macros accordingly to use ICL prefix. There's one leftover reference to cnl that comes from the struct intel_ddi_buf_trans. This will be renamed later when we get rid of the additional CNL tables.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/display/intel_ddi.c | 254 ++--------------------- 1 file changed, 20 insertions(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 26a3aa73fcc4..8367462842fa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -822,7 +822,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, static enum intel_display_power_domain intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) {

• /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with

• /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
  • DC states enabled at the same time, while for driver initiated AUX
  • transfers we need the same AUX IOs to be powered but with DC states
  • disabled. Accordingly use the AUX power domain here which leaves DC

@@ -1017,126 +1017,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) return DP_TRAIN_PRE_EMPH_LEVEL_3; }

-static void cnl_ddi_vswing_program(struct intel_encoder *encoder,

• 		   const struct intel_crtc_state *crtc_state,
  

• 		   int level)
  

-{

• struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
• const struct intel_ddi_buf_trans *ddi_translations;
• enum port port = encoder->port;
• int n_entries, ln;
• u32 val;
• ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
• if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))

• return;
  

• if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))

• level = n_entries - 1;
  

• /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
• val &= ~SCALING_MODE_SEL_MASK;
• val |= SCALING_MODE_SEL(2);
• intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
• /* Program PORT_TX_DW2 */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
• val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

•  RCOMP_SCALAR_MASK);
  

• val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
• val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
• /* Rcomp scalar is fixed as 0x98 for every table entry */
• val |= RCOMP_SCALAR(0x98);
• intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
• /* Program PORT_TX_DW4 */
• /* We cannot write to GRP. It would overrite individual loadgen */
• for (ln = 0; ln < 4; ln++) {

• val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
  

• val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
  

• 	 CURSOR_COEFF_MASK);
  

• val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
  

• val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
  

• val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
  

• intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
  

• }
• /* Program PORT_TX_DW5 */
• /* All DW5 values are fixed for every table entry */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
• val &= ~RTERM_SELECT_MASK;
• val |= RTERM_SELECT(6);
• val |= TAP3_DISABLE;
• intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
• /* Program PORT_TX_DW7 */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
• val &= ~N_SCALAR_MASK;
• val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
• intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);

-}

-static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,

• 		    const struct intel_crtc_state *crtc_state,
  

• 		    int level)
  

-{

• struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
• enum port port = encoder->port;
• int width, rate, ln;
• u32 val;
• width = crtc_state->lane_count;
• rate = crtc_state->port_clock;
• /*

• * 1. If port type is eDP or DP,
  

• * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
  

• * else clear to 0b.
  

• */
  

• val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
• if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

• val &= ~COMMON_KEEPER_EN;
  

• else

• val |= COMMON_KEEPER_EN;
  

• intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
• /* 2. Program loadgen select */
• /*

• * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
  

• * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
  

• * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
  

• * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
  

• */
  

• for (ln = 0; ln <= 3; ln++) {

• val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
  

• val &= ~LOADGEN_SELECT;
  

• if ((rate <= 600000 && width == 4 && ln >= 1)  ||
  

•     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
  

• 	val |= LOADGEN_SELECT;
  

• }
  

• intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
  

• }
• /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
• val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
• val |= SUS_CLOCK_CONFIG;
• intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
• /* 4. Clear training enable to change swing values */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
• val &= ~TX_TRAINING_EN;
• intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
• /* 5. Program swing and de-emphasis */
• cnl_ddi_vswing_program(encoder, crtc_state, level);
• /* 6. Set training enable to trigger update */
• val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
• val |= TX_TRAINING_EN;
• intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);

-}

static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int level) @@ -1515,16 +1395,6 @@ icl_set_signal_levels(struct intel_dp *intel_dp, icl_ddi_vswing_sequence(encoder, crtc_state, level); }

-static void -cnl_set_signal_levels(struct intel_dp *intel_dp,

•       const struct intel_crtc_state *crtc_state)
  

-{

• struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
• int level = intel_ddi_dp_level(intel_dp);
• cnl_ddi_vswing_sequence(encoder, crtc_state, level);

-}

static void bxt_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) @@ -1560,7 +1430,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); }

-static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { mutex_lock(&i915->dpll.lock); @@ -1576,7 +1446,7 @@ static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, mutex_unlock(&i915->dpll.lock); }

-static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_off) { mutex_lock(&i915->dpll.lock); @@ -1586,14 +1456,14 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg mutex_unlock(&i915->dpll.lock); }

-static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, +static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_off) { return !(intel_de_read(i915, reg) & clk_off); }

static struct intel_shared_dpll * -_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, +_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { enum intel_dpll_id id; @@ -1613,7 +1483,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder, if (drm_WARN_ON(&i915->drm, !pll)) return;

• _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),

• _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

@@ -1624,7 +1494,7 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),

• _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1633,7 +1503,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),

• return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1642,7 +1512,7 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),

• return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));

} @@ -1657,7 +1527,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, if (drm_WARN_ON(&i915->drm, !pll)) return;

• _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,

• _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

@@ -1668,7 +1538,7 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,

• _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1677,7 +1547,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,

• return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1686,7 +1556,7 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,

• return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));

} @@ -1710,7 +1580,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) return;

• _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),

• _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

@@ -1721,7 +1591,7 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),

• _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1730,7 +1600,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),

• return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1767,7 +1637,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, if (drm_WARN_ON(&i915->drm, !pll)) return;

• _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,

• _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

@@ -1778,7 +1648,7 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,

• _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1787,7 +1657,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,

• return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}

@@ -1796,7 +1666,7 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(i915, encoder->port);

• return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,

• return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));

} @@ -1929,50 +1799,6 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode return intel_get_shared_dpll_by_id(i915, id); }

-static void cnl_ddi_enable_clock(struct intel_encoder *encoder,

• 		 const struct intel_crtc_state *crtc_state)
  

-{

• struct drm_i915_private *i915 = to_i915(encoder->base.dev);
• const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
• enum port port = encoder->port;
• if (drm_WARN_ON(&i915->drm, !pll))

• return;
  

• _cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,

• 	      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
  

• 	      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
  

• 	      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
  

-}

-static void cnl_ddi_disable_clock(struct intel_encoder *encoder) -{

• struct drm_i915_private *i915 = to_i915(encoder->base.dev);
• enum port port = encoder->port;
• _cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,

• 	       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
  

-}

-static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder) -{

• struct drm_i915_private *i915 = to_i915(encoder->base.dev);
• enum port port = encoder->port;
• return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,

• 			 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
  

-}

-static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder) -{

• struct drm_i915_private *i915 = to_i915(encoder->base.dev);
• enum port port = encoder->port;
• return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,

• 		DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
  

• 		DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
  

-}

static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -2657,8 +2483,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,

if (DISPLAY_VER(dev_priv) >= 11) icl_ddi_vswing_sequence(encoder, crtc_state, level);

• else if (IS_CANNONLAKE(dev_priv))

• cnl_ddi_vswing_sequence(encoder, crtc_state, level);
  

  else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else

@@ -3105,8 +2929,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, tgl_ddi_vswing_sequence(encoder, crtc_state, level); else if (DISPLAY_VER(dev_priv) == 11) icl_ddi_vswing_sequence(encoder, crtc_state, level);

• else if (IS_CANNONLAKE(dev_priv))

• cnl_ddi_vswing_sequence(encoder, crtc_state, level);
  

  else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else

@@ -3470,8 +3292,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, crtc_state->min_voltage_level = 3; else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) crtc_state->min_voltage_level = 1;

• else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)

• crtc_state->min_voltage_level = 2;
  

}

static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, @@ -3812,13 +3632,6 @@ static void icl_ddi_tc_get_config(struct intel_encoder *encoder, intel_ddi_get_config(encoder, crtc_state); }

-static void cnl_ddi_get_config(struct intel_encoder *encoder,

• 	       struct intel_crtc_state *crtc_state)
  

-{

• intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
• intel_ddi_get_config(encoder, crtc_state);

-}

static void bxt_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -4069,8 +3882,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) dig_port->dp.set_signal_levels = tgl_set_signal_levels; else if (DISPLAY_VER(dev_priv) >= 11) dig_port->dp.set_signal_levels = icl_set_signal_levels;

• else if (IS_CANNONLAKE(dev_priv))

• dig_port->dp.set_signal_levels = cnl_set_signal_levels;
  

  else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) dig_port->dp.set_signal_levels = bxt_set_signal_levels; else

@@ -4317,15 +4128,6 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) return true;

• /* Cannonlake: Most of SKUs don't support DDI_E, and the only

• *             one who does also have a full A/E split called
  

• *             DDI_F what makes DDI_E useless. However for this
  

• *             case let's trust VBT info.
  

• */
  

• if (IS_CANNONLAKE(dev_priv) &&

•    !intel_bios_is_port_present(dev_priv, PORT_E))
  

• return true;
  

• return false;

}

@@ -4430,15 +4232,6 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; }

-static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,

• 		enum port port)
  

-{

• if (port == PORT_F)

• return HPD_PORT_E;
  

• return HPD_PORT_A + port - PORT_A;

-}

static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) { if (HAS_PCH_TGP(dev_priv)) @@ -4645,11 +4438,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; encoder->get_config = icl_ddi_combo_get_config; }

• } else if (IS_CANNONLAKE(dev_priv)) {

• encoder->enable_clock = cnl_ddi_enable_clock;
  

• encoder->disable_clock = cnl_ddi_disable_clock;
  

• encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
  

• encoder->get_config = cnl_ddi_get_config;
  

  } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { /* BXT/GLK have fixed PLL->port mapping */ encoder->get_config = bxt_ddi_get_config;

@@ -4679,8 +4467,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); else if (DISPLAY_VER(dev_priv) == 11) encoder->hpd_pin = icl_hpd_pin(dev_priv, port);

• else if (IS_CANNONLAKE(dev_priv))

• encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
  

  else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) encoder->hpd_pin = skl_hpd_pin(dev_priv, port); else

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:10:53PM -0700, Lucas De Marchi wrote:

Only one reference to CNL that is not needed, but code is the same for DISPLAY_VER >= 11, so leave the code around and just remove the special case for CNL.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2cf742a0b957..8fdacb252bb1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2500,7 +2500,7 @@ int intel_connector_debugfs_add(struct drm_connector *connector) connector, &i915_hdcp_sink_capability_fops); }

• if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&

• if (DISPLAY_VER(dev_priv) >= 11 && ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && !to_intel_connector(connector)->mst_port) || connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:

Remove DMC firmware for CNL.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Cc: Anusha Srivatsa anusha.srivatsa@intel.com

We need to remove the binary from linux-firmware.git as well

---

drivers/gpu/drm/i915/display/intel_dmc.c | 9 --------- 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 9895fd957df9..3c3c6cb5c0df 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH); #define ICL_DMC_MAX_FW_SIZE 0x6000 MODULE_FIRMWARE(ICL_DMC_PATH);

-#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) -#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) -#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE -MODULE_FIRMWARE(CNL_DMC_PATH);

#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) #define GLK_DMC_MAX_FW_SIZE 0x4000 @@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) dmc->fw_path = ICL_DMC_PATH; dmc->required_version = ICL_DMC_VERSION_REQUIRED; dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;

• } else if (IS_CANNONLAKE(dev_priv)) {

• dmc->fw_path = CNL_DMC_PATH;
  

• dmc->required_version = CNL_DMC_VERSION_REQUIRED;
  

• dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
  

  } else if (IS_GEMINILAKE(dev_priv)) { dmc->fw_path = GLK_DMC_PATH; dmc->required_version = GLK_DMC_VERSION_REQUIRED;

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Mon, Jul 26, 2021 at 06:59:35AM -0400, Rodrigo Vivi wrote:

On Fri, Jul 23, 2021 at 05:11:02PM -0700, Lucas De Marchi wrote:

...

Remove special handling of PORT_F in i915_irq.c and only do it for DISPLAY_VER == 11.

oh! ignore my previous thought about removing the port F...

of course I only saw this after replying to your comment :)

thanks Lucas De Marchi

...

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

...

---

drivers/gpu/drm/i915/i915_irq.c | 7 +++---- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e2171bd2820e..17d336218b67 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D;

• if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)

• mask |= CNL_AUX_CHANNEL_F;
  

• if (DISPLAY_VER(dev_priv) == 11)

• if (DISPLAY_VER(dev_priv) == 11) {

• mask |= ICL_AUX_CHANNEL_F;
  

  mask |= ICL_AUX_CHANNEL_E;

• }

  return mask;

} diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d198b1a2d4b5..fdc8fd424d36 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7945,7 +7945,7 @@ enum { #define DSI1_NON_TE (1 << 31) #define DSI0_NON_TE (1 << 30) #define ICL_AUX_CHANNEL_E (1 << 29) -#define CNL_AUX_CHANNEL_F (1 << 28) +#define ICL_AUX_CHANNEL_F (1 << 28) #define GEN9_AUX_CHANNEL_D (1 << 27) #define GEN9_AUX_CHANNEL_C (1 << 26)

#define GEN9_AUX_CHANNEL_B (1 << 25)

2.31.1

On Fri, Jul 23, 2021 at 05:11:03PM -0700, Lucas De Marchi wrote:

Remove support for CNL as it's highly untested, probably broken, and there is no real platform that requires this code. This is part of CNL removal from i915.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 41 +-------------------------------- 2 files changed, 2 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fdc8fd424d36..f032a4c8b26d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8239,7 +8239,7 @@ enum {

#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) -#define CNL_DELAY_PMRSP (1 << 22) +#define ICL_DELAY_PMRSP (1 << 22) #define MASK_WAKEMEM (1 << 13) #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aa64b2ef2efb..65bc3709f54c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7465,7 +7465,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)

/*Wa_14010594013:icl, ehl */ intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,

• 	 0, CNL_DELAY_PMRSP);
  

• 	 0, ICL_DELAY_PMRSP);
  

}

static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) @@ -7515,43 +7515,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) CNP_PWM_CGE_GATING_DISABLE); }

-static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) -{

• u32 val;
• cnp_init_clock_gating(dev_priv);
• /* This is not an Wa. Enable for better image quality */
• intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,

•    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
  

• /* WaEnableChickenDCPR:cnl */
• intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,

•    intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  

• /*

• * WaFbcWakeMemOn:cnl
  

• * Display WA #0859: cnl
  

• */
  

• intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |

•    DISP_FBC_MEMORY_WAKE);
  

• val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
• /* ReadHitWriteOnlyDisable:cnl */
• val |= RCCUNIT_CLKGATE_DIS;
• intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
• /* Wa_2201832410:cnl */
• val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
• val |= GWUNIT_CLKGATE_DIS;
• intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
• /* WaDisableVFclkgate:cnl */
• /* WaVFUnitClockGatingDisable:cnl */
• val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
• val |= VFUNIT_CLKGATE_DIS;
• intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);

-}

static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) { cnp_init_clock_gating(dev_priv); @@ -7980,8 +7943,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = gen12lp_init_clock_gating; else if (GRAPHICS_VER(dev_priv) == 11) dev_priv->display.init_clock_gating = icl_init_clock_gating;

• else if (IS_CANNONLAKE(dev_priv))

• dev_priv->display.init_clock_gating = cnl_init_clock_gating;
  

  else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) dev_priv->display.init_clock_gating = cfl_init_clock_gating; else if (IS_SKYLAKE(dev_priv))

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:11:04PM -0700, Lucas De Marchi wrote:

Only one reference to CNL that is not needed, but code is the same for GEN9_BC, so leave the code around and just remove the special case for CNL.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 17848807f111..582c4423b95d 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->size = ARRAY_SIZE(icl_mocs_table); table->table = icl_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES;

• } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {

• } else if (IS_GEN9_BC(i915)) { table->size = ARRAY_SIZE(skl_mocs_table); table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->table = skl_mocs_table;

-- 2.31.1

On Fri, Jul 23, 2021 at 05:11:05PM -0700, Lucas De Marchi wrote:

Remove references for CNL from pch detection.

for a moment I almost thought you were removing the CNP support...

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/intel_pch.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index cc44164e242b..d1d4b97b86f5 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_CNP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); drm_WARN_ON(&dev_priv->drm,

• 	    !IS_CANNONLAKE(dev_priv) &&
      !IS_COFFEELAKE(dev_priv) &&
      !IS_COMETLAKE(dev_priv));
  

  return PCH_CNP;

@@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake LP PCH (CNP-LP)\n"); drm_WARN_ON(&dev_priv->drm,

• 	    !IS_CANNONLAKE(dev_priv) &&
      !IS_COFFEELAKE(dev_priv) &&
      !IS_COMETLAKE(dev_priv));
  

  return PCH_CNP;

@@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE;

• else if (IS_CANNONLAKE(dev_priv) ||

•  IS_COFFEELAKE(dev_priv) ||
  

• else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) id = INTEL_PCH_CNP_DEVICE_ID_TYPE; else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:11:06PM -0700, Lucas De Marchi wrote:

Consider the new WOPCM size as starting in ICL rather than CNL since the latter is being removed from the driver.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/intel_wopcm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 8309455f13ea..5e511bb891f9 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -56,8 +56,8 @@

/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */ #define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K) -/* 36KB WOPCM reserved at the end of WOPCM on CNL. */ -#define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K) +/* 36KB WOPCM reserved at the end of WOPCM on ICL. */ +#define ICL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)

/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */ #define GEN9_GUC_FW_RESERVED SZ_128K @@ -93,8 +93,8 @@ static u32 context_reserved_size(struct drm_i915_private *i915) { if (IS_GEN9_LP(i915)) return BXT_WOPCM_RC6_CTX_RESERVED;

• else if (GRAPHICS_VER(i915) >= 10)

• return CNL_WOPCM_HW_CTX_RESERVED;
  

• else if (GRAPHICS_VER(i915) >= 11)

• return ICL_WOPCM_HW_CTX_RESERVED;
  

  else return 0;

} @@ -126,7 +126,7 @@ static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915, u32 guc_wopcm_size, u32 huc_fw_size) { /*

• * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
  

• * On Gen9, hardware requires the total available GuC WOPCM
  

  • size to be larger than or equal to HuC firmware size. Otherwise,
  • firmware uploading would fail.
  */

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:11:07PM -0700, Lucas De Marchi wrote:

CNL is the only platform with GRAPHICS_VER == 10. With its removal we don't need to handle that version anymore.

Also we can now reduce the max number of slices: the call to intel_sseu_set_info() with the highest number of slices comes from SKL and BDW with 3 slices. Recent platforms actually increase the number of subslices so the number of slices remain 1.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Matt Roper matthew.d.roper@intel.com

---

drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ---------------------------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- 2 files changed, 1 insertion(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 367fd44b81c8..9542c3f3822a 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -188,83 +188,6 @@ static void gen11_sseu_info_init(struct intel_gt *gt) sseu->has_eu_pg = 1; }

-static void gen10_sseu_info_init(struct intel_gt *gt) -{

• struct intel_uncore *uncore = gt->uncore;
• struct sseu_dev_info *sseu = &gt->info.sseu;
• const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
• const int eu_mask = 0xff;
• u32 subslice_mask, eu_en;
• int s, ss;
• intel_sseu_set_info(sseu, 6, 4, 8);
• sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>

• GEN10_F2_S_ENA_SHIFT;
  

• /* Slice0 */
• eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
• for (ss = 0; ss < sseu->max_subslices; ss++)

• sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
  

• /* Slice1 */
• sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
• eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
• sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
• /* Slice2 */
• sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
• sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
• /* Slice3 */
• sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
• eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
• sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
• /* Slice4 */
• sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
• sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
• /* Slice5 */
• sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
• eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
• sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
• subslice_mask = (1 << 4) - 1;
• subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>

• 	   GEN10_F2_SS_DIS_SHIFT);
  

• for (s = 0; s < sseu->max_slices; s++) {

• u32 subslice_mask_with_eus = subslice_mask;
  

• for (ss = 0; ss < sseu->max_subslices; ss++) {
  

• 	if (sseu_get_eus(sseu, s, ss) == 0)
  

• 		subslice_mask_with_eus &= ~BIT(ss);
  

• }
  

• /*
  

•  * Slice0 can have up to 3 subslices, but there are only 2 in
  

•  * slice1/2.
  

•  */
  

• intel_sseu_set_subslices(sseu, s, s == 0 ?
  

• 			 subslice_mask_with_eus :
  

• 			 subslice_mask_with_eus & 0x3);
  

• }
• sseu->eu_total = compute_eu_total(sseu);
• /*

• * CNL is expected to always have a uniform distribution
  

• * of EU across subslices with the exception that any one
  

• * EU in any one subslice may be fused off for die
  

• * recovery.
  

• */
  

• sseu->eu_per_subslice =

• intel_sseu_subslice_total(sseu) ?
  

• DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
  

• 0;
  

• /* No restrictions on Power Gating */
• sseu->has_slice_pg = 1;
• sseu->has_subslice_pg = 1;
• sseu->has_eu_pg = 1;

-}

static void cherryview_sseu_info_init(struct intel_gt *gt) { struct sseu_dev_info *sseu = &gt->info.sseu; @@ -592,8 +515,6 @@ void intel_sseu_info_init(struct intel_gt *gt) bdw_sseu_info_init(gt); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_info_init(gt);

• else if (GRAPHICS_VER(i915) == 10)

• gen10_sseu_info_init(gt);
  

  else if (GRAPHICS_VER(i915) == 11) gen11_sseu_info_init(gt); else if (GRAPHICS_VER(i915) >= 12)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 4cd1a8a7298a..8d85ec05f610 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -15,7 +15,7 @@ struct drm_i915_private; struct intel_gt; struct drm_printer;

-#define GEN_MAX_SLICES (6) /* CNL upper bound */ +#define GEN_MAX_SLICES (3) /* SKL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)

#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)

2.31.1

On Fri, Jul 23, 2021 at 05:11:08PM -0700, Lucas De Marchi wrote:

With the removal of CNL, let's consider ICL as the first platform using those constants.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/i915_reg.h | 24 +++++++++++------------ drivers/gpu/drm/i915/intel_dram.c | 32 +++++++++++++++---------------- 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f032a4c8b26d..8782d1723254 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11082,18 +11082,18 @@ enum skl_power_gate { #define SKL_DRAM_RANK_1 (0x0 << 10) #define SKL_DRAM_RANK_2 (0x1 << 10) #define SKL_DRAM_RANK_MASK (0x1 << 10) -#define CNL_DRAM_SIZE_MASK 0x7F -#define CNL_DRAM_WIDTH_MASK (0x3 << 7) -#define CNL_DRAM_WIDTH_SHIFT 7 -#define CNL_DRAM_WIDTH_X8 (0x0 << 7) -#define CNL_DRAM_WIDTH_X16 (0x1 << 7) -#define CNL_DRAM_WIDTH_X32 (0x2 << 7) -#define CNL_DRAM_RANK_MASK (0x3 << 9) -#define CNL_DRAM_RANK_SHIFT 9 -#define CNL_DRAM_RANK_1 (0x0 << 9) -#define CNL_DRAM_RANK_2 (0x1 << 9) -#define CNL_DRAM_RANK_3 (0x2 << 9) -#define CNL_DRAM_RANK_4 (0x3 << 9) +#define ICL_DRAM_SIZE_MASK 0x7F +#define ICL_DRAM_WIDTH_MASK (0x3 << 7) +#define ICL_DRAM_WIDTH_SHIFT 7 +#define ICL_DRAM_WIDTH_X8 (0x0 << 7) +#define ICL_DRAM_WIDTH_X16 (0x1 << 7) +#define ICL_DRAM_WIDTH_X32 (0x2 << 7) +#define ICL_DRAM_RANK_MASK (0x3 << 9) +#define ICL_DRAM_RANK_SHIFT 9 +#define ICL_DRAM_RANK_1 (0x0 << 9) +#define ICL_DRAM_RANK_2 (0x1 << 9) +#define ICL_DRAM_RANK_3 (0x2 << 9) +#define ICL_DRAM_RANK_4 (0x3 << 9)

#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2) diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 9675bb94b70b..34d6cf440352 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val) }

/* Returns total Gb for the whole DIMM */ -static int cnl_get_dimm_size(u16 val) +static int icl_get_dimm_size(u16 val) {

• return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;

• return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;

}

-static int cnl_get_dimm_width(u16 val) +static int icl_get_dimm_width(u16 val) {

• if (cnl_get_dimm_size(val) == 0)

• if (icl_get_dimm_size(val) == 0) return 0;

• switch (val & CNL_DRAM_WIDTH_MASK) {
• case CNL_DRAM_WIDTH_X8:
• case CNL_DRAM_WIDTH_X16:
• case CNL_DRAM_WIDTH_X32:

• val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
  

• switch (val & ICL_DRAM_WIDTH_MASK) {
• case ICL_DRAM_WIDTH_X8:
• case ICL_DRAM_WIDTH_X16:
• case ICL_DRAM_WIDTH_X32:

• val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
  

  return 8 << val; default: MISSING_CASE(val);

@@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val) } }

-static int cnl_get_dimm_ranks(u16 val) +static int icl_get_dimm_ranks(u16 val) {

• if (cnl_get_dimm_size(val) == 0)

• if (icl_get_dimm_size(val) == 0) return 0;

• val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;

• val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;

  return val + 1;

} @@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915, struct dram_dimm_info *dimm, int channel, char dimm_name, u16 val) {

• if (GRAPHICS_VER(i915) >= 10) {

• dimm->size = cnl_get_dimm_size(val);
  

• dimm->width = cnl_get_dimm_width(val);
  

• dimm->ranks = cnl_get_dimm_ranks(val);
  

• if (GRAPHICS_VER(i915) >= 11) {

• dimm->size = icl_get_dimm_size(val);
  

• dimm->width = icl_get_dimm_width(val);
  

• dimm->ranks = icl_get_dimm_ranks(val);
  

  } else { dimm->size = skl_get_dimm_size(val); dimm->width = skl_get_dimm_width(val);

-- 2.31.1

On Fri, Jul 23, 2021 at 05:11:09PM -0700, Lucas De Marchi wrote:

With the removal of CNL, let's consider ICL as the first platform using that index.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

( I got myself thinking that some patches like this could be squashed into others, and a few of them made with coccinele, but in the end I like the approach you took. It's been very easy to review this series... )

---

drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index f911c1224ab2..dfb400766db5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)

#define I915_HWS_CSB_BUF0_INDEX 0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f -#define CNL_HWS_CSB_WRITE_INDEX 0x2f +#define ICL_HWS_CSB_WRITE_INDEX 0x2f

void intel_engine_stop(struct intel_engine_cs *engine); void intel_engine_cleanup(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d118834a4ed9..dd2d196050d4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1959,8 +1959,8 @@ int remap_io_sg(struct vm_area_struct *vma,

static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) {

• if (GRAPHICS_VER(i915) >= 10)

• return CNL_HWS_CSB_WRITE_INDEX;
  

• if (GRAPHICS_VER(i915) >= 11)

• return ICL_HWS_CSB_WRITE_INDEX;
  

  else return I915_HWS_CSB_WRITE_INDEX;

}

2.31.1

On Fri, Jul 23, 2021 at 05:11:10PM -0700, Lucas De Marchi wrote:

With all the users removed, finish removing the CNL platform definitions. We will leave the PCI IDs around as those are exposed to userspace. Even if mesa doesn't support CNL anymore, let's avoid build breakages due to changing the headers.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/i915_drv.h | 7 +------ drivers/gpu/drm/i915/i915_pci.c | 23 +++++------------------ drivers/gpu/drm/i915/i915_perf.c | 1 - drivers/gpu/drm/i915/intel_device_info.c | 2 -- drivers/gpu/drm/i915/intel_device_info.h | 2 -- 5 files changed, 6 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dd2d196050d4..e3c8283d770c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1437,7 +1437,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) -#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) @@ -1503,8 +1502,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 2)

-#define IS_CNL_WITH_PORT_F(dev_priv) \

• IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)

#define IS_ICL_WITH_PORT_F(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)

@@ -1649,9 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,

/* WaRsDisableCoarsePowerGating:skl,cnl */ #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \

• (IS_CANNONLAKE(dev_priv) || \

• IS_SKL_GT3(dev_priv) ||					\
  

• IS_SKL_GT4(dev_priv))
  

• (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))

#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4) #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 48ea23dd3b5b..aea2c2d82fbf 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = { .gt = 2, };

-#define GEN10_FEATURES \

• GEN9_FEATURES, \
• GEN(10), \
• .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
• .display.has_dsc = 1, \
• .has_coherent_ggtt = false, \
• GLK_COLORS

-static const struct intel_device_info cnl_info = {

• GEN10_FEATURES,
• PLATFORM(INTEL_CANNONLAKE),
• .gt = 2,

-};

#define GEN11_DEFAULT_PAGE_SIZES \ .page_sizes = I915_GTT_PAGE_SIZE_4K | \ I915_GTT_PAGE_SIZE_64K | \ I915_GTT_PAGE_SIZE_2M

#define GEN11_FEATURES \

• GEN10_FEATURES, \

• GEN9_FEATURES, \ GEN11_DEFAULT_PAGE_SIZES, \ .abox_mask = BIT(0), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

@@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = { [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ }, \ GEN(11), \

• .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \ .dbuf.size = 2048, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \

• .has_logical_ring_elsq = 1, \
• .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }

• .display.has_dsc = 1, \
• .has_coherent_ggtt = false, \
• .has_logical_ring_elsq = 1

static const struct intel_device_info icl_info = { GEN11_FEATURES, @@ -1123,7 +1111,6 @@ static const struct pci_device_id pciidlist[] = { INTEL_CML_GT2_IDS(&cml_gt2_info), INTEL_CML_U_GT1_IDS(&cml_gt1_info), INTEL_CML_U_GT2_IDS(&cml_gt2_info),

• INTEL_CNL_IDS(&cnl_info), INTEL_ICL_11_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), INTEL_JSL_IDS(&jsl_info),

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 838cc14c2f24..108774d651d9 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -4319,7 +4319,6 @@ static void oa_init_supported_formats(struct i915_perf *perf) case INTEL_GEMINILAKE: case INTEL_COFFEELAKE: case INTEL_COMETLAKE:

• case INTEL_CANNONLAKE: case INTEL_ICELAKE: case INTEL_ELKHARTLAKE: case INTEL_JASPERLAKE:

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 99b51c292942..2893a8659a8b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -59,7 +59,6 @@ static const char * const platform_names[] = { PLATFORM_NAME(GEMINILAKE), PLATFORM_NAME(COFFEELAKE), PLATFORM_NAME(COMETLAKE),

• PLATFORM_NAME(CANNONLAKE), PLATFORM_NAME(ICELAKE), PLATFORM_NAME(ELKHARTLAKE), PLATFORM_NAME(JASPERLAKE),

@@ -175,7 +174,6 @@ static const u16 subplatform_ulx_ids[] = { };

static const u16 subplatform_portf_ids[] = {

• INTEL_CNL_PORT_F_IDS(0), INTEL_ICL_PORT_F_IDS(0),

};

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 616ccec41d76..057c9aa6f9c6 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -76,8 +76,6 @@ enum intel_platform { INTEL_GEMINILAKE, INTEL_COFFEELAKE, INTEL_COMETLAKE,

• /* gen10 */
• INTEL_CANNONLAKE, /* gen11 */ INTEL_ICELAKE, INTEL_ELKHARTLAKE,

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:11:11PM -0700, Lucas De Marchi wrote:

Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 - drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 -- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +-- drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +------------------ drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +-- drivers/gpu/drm/i915/gvt/gtt.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 6 +-- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_perf.c | 21 ++++------ drivers/gpu/drm/i915/intel_device_info.c | 4 +- 15 files changed, 37 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index 90708de27684..ddd37ccb1362 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem) break; case 8: case 9:

• case 10: if (IS_LP(i915)) chv_get_stolen_reserved(i915, uncore, &reserved_base, &reserved_size);

diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index 4270b5a34a83..d6f5836396f8 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused) max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (IS_GEN9_BC(i915) ||

• 	     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq));

  max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (IS_GEN9_BC(i915) ||

• 	     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq));

  max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (IS_GEN9_BC(i915) ||

• 	     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n",

@@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)

min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq;

• if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {

• if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER;

@@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data) intel_gpu_freq(rps, (gpu_freq * (IS_GEN9_BC(i915) ||

• 			    GRAPHICS_VER(i915) >= 10 ?
  

• 			    GRAPHICS_VER(i915) >= 11 ?
  		    GEN9_FREQ_SCALER : 1))),
     ((ia_freq >> 0) & 0xff) * 100,
     ((ia_freq >> 8) & 0xff) * 100);
  

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4168b9fc59e1..152b5493a455 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -35,7 +35,6 @@ #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) -#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)

#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) @@ -149,8 +148,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) case 12: case 11: return GEN11_LR_CONTEXT_RENDER_SIZE;

• case 10:
  

• 	return GEN10_LR_CONTEXT_RENDER_SIZE;
  

  case 9: return GEN9_LR_CONTEXT_RENDER_SIZE; case 8:

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 9d445ad9a342..de3ac58fceec 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;

/*

• * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
  

• * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
  

  • will be dropped. For WC mappings in general we have 64 byte burst
  • writes when the WC buffer is flushed, so we can't use it, but have to
  • resort to an uncached mapping. The WC issue is easily caught by the
  • readback check when writing GTT PTE entries.
  */

• if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)

• if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11) ggtt->gsm = ioremap(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size);

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 9f0e729d2d15..3513d6f90747 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -24,8 +24,8 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore) return base_freq + frac_freq; }

-static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore,

• 			u32 rpm_config_reg)
  

+static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,

• 		       u32 rpm_config_reg)
  

{ u32 f19_2_mhz = 19200000; u32 f24_mhz = 24000000; @@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore) } else { u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);

• 	if (GRAPHICS_VER(uncore->i915) <= 10)
  

• 		freq = gen10_get_crystal_clock_freq(uncore, c0);
  

• 	else
  

• 	if (GRAPHICS_VER(uncore->i915) >= 11)
  	freq = gen11_get_crystal_clock_freq(uncore, c0);
  

• 	else
  

• 		freq = gen9_get_crystal_clock_freq(uncore, c0);
  
  /*
   * Now figure out how the command stream's timestamp
  

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index f7e0352edb62..e137dd32b5b8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore) intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); }

-static void cnl_setup_private_ppat(struct intel_uncore *uncore) +static void icl_setup_private_ppat(struct intel_uncore *uncore) { intel_uncore_write(uncore, GEN10_PAT_INDEX(0), @@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore)

if (GRAPHICS_VER(i915) >= 12) tgl_setup_private_ppat(uncore);

• else if (GRAPHICS_VER(i915) >= 10)

• cnl_setup_private_ppat(uncore);
  

• else if (GRAPHICS_VER(i915) >= 11)

• icl_setup_private_ppat(uncore);
  

  else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) chv_setup_private_ppat(uncore); else

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c3f5bec8ae15..bb4af4977920 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs, if (close) { /* Close the batch; used mainly by live_lrc_layout() */ *regs = MI_BATCH_BUFFER_END;

• if (GRAPHICS_VER(engine->i915) >= 10)
  

• if (GRAPHICS_VER(engine->i915) >= 11)
  *regs |= BIT(0);
  

  }

} @@ -653,8 +653,6 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine) return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 11: return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

• case 10:

• return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
  

  case 9: return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 8:

@@ -1448,40 +1446,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) return batch; }

-static u32 * -gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) -{

• int i;
• /*

• * WaPipeControlBefore3DStateSamplePattern: cnl
  

• *
  

• * Ensure the engine is idle prior to programming a
  

• * 3DSTATE_SAMPLE_PATTERN during a context restore.
  

• */
  

• batch = gen8_emit_pipe_control(batch,

• 		       PIPE_CONTROL_CS_STALL,
  

• 		       0);
  

• /*

• * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
  

• * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
  

• * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
  

• * confusing. Since gen8_emit_pipe_control() already advances the
  

• * batch by 6 dwords, we advance the other 10 here, completing a
  

• * cacheline. It's not clear if the workaround requires this padding
  

• * before other commands, or if it's just the regular padding we would
  

• * already have for the workaround bb, so leave it here for now.
  

• */
  

• for (i = 0; i < 10; i++)

• *batch++ = MI_NOOP;
  

• /* Pad to end of cacheline */
• while ((unsigned long)batch % CACHELINE_BYTES)

• *batch++ = MI_NOOP;
  

• return batch;

-}

#define CTX_WA_BB_SIZE (PAGE_SIZE)

static int lrc_create_wa_ctx(struct intel_engine_cs *engine) @@ -1534,10 +1498,6 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine) case 12: case 11: return;

• case 10:

• wa_bb_fn[0] = gen10_init_indirectctx_bb;
  

• wa_bb_fn[1] = NULL;
  

• break;
  

  case 9: wa_bb_fn[0] = gen9_init_indirectctx_bb; wa_bb_fn[1] = NULL;

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 259d7eb4e165..a7d13fe35b2e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) enum intel_engine_id id;

/* 2b: Program RC6 thresholds.*/

• if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {

• if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 06e9a8ed4e03..2e03ad80f3cf 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)

rps->efficient_freq = rps->rp1_freq; if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||

•    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
  

•    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
  

  u32 ddcc_status = 0;

  if (sandybridge_pcode_read(i915,

@@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps) rps->max_freq); }

• if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {

• if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Store the frequency values in 16.66 MHZ units, which is
  • the natural hardware unit for SKL
  */

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c index 714fe8495775..5e7b09c5e36f 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c @@ -50,7 +50,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt, #undef SS_MAX }

-static void gen10_sseu_device_status(struct intel_gt *gt, +static void gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) { #define SS_MAX 6 @@ -267,8 +267,8 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt) bdw_sseu_device_status(gt, &sseu); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_device_status(gt, &sseu);

• else if (GRAPHICS_VER(i915) >= 10)
  

• 	gen10_sseu_device_status(gt, &sseu);
  

• else if (GRAPHICS_VER(i915) >= 11)
  

• 	gen11_sseu_device_status(gt, &sseu);
  

  }

  i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu);

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index cc2c05e18206..e5c2fdfc20e3 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

• if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {

• if (GRAPHICS_VER(dev_priv) == 9) { u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & GAMW_ECO_ENABLE_64K_IPS_FIELD;

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 0529576f069c..44969f5dde50 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (IS_GEN9_BC(dev_priv) ||

• 	     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq));

  max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (IS_GEN9_BC(dev_priv) ||

• 	     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq));

  max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (IS_GEN9_BC(dev_priv) ||

• 	     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
  

• 	     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
  

  seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n",

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e3c8283d770c..f9671686bf62 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1649,7 +1649,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))

#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4) -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \ +#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv))

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 108774d651d9..2f01b8c0284c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)

case 8: case 9:

• case 10: if (intel_engine_uses_guc(ce->engine)) { /* * When using GuC, the context descriptor we write in

@@ -2589,7 +2588,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream) intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0); }

-static void gen10_disable_metric_set(struct i915_perf_stream *stream) +static void gen11_disable_metric_set(struct i915_perf_stream *stream) { struct intel_uncore *uncore = stream->uncore;

@@ -3896,7 +3895,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr) REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8)); }

-static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr) +static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr) { return gen8_is_valid_mux_addr(perf, addr) || REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) || @@ -4403,27 +4402,23 @@ void i915_perf_init(struct drm_i915_private *i915)

		perf->gen8_valid_ctx_bit = BIT(16);
	}

• } else if (IS_GRAPHICS_VER(i915, 10, 11)) {
  

• } else if (GRAPHICS_VER(i915) == 11) {
  perf->ops.is_valid_b_counter_reg =
  	gen7_is_valid_b_counter_addr;
  perf->ops.is_valid_mux_reg =
  

• 		gen10_is_valid_mux_addr;
  

• 		gen11_is_valid_mux_addr;
  perf->ops.is_valid_flex_reg =
  	gen8_is_valid_flex_addr;
  
  perf->ops.oa_enable = gen8_oa_enable;
  perf->ops.oa_disable = gen8_oa_disable;
  perf->ops.enable_metric_set = gen8_enable_metric_set;
  

• 	perf->ops.disable_metric_set = gen10_disable_metric_set;
  

• 	perf->ops.disable_metric_set = gen11_disable_metric_set;
  perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
  
  

• 	if (GRAPHICS_VER(i915) == 10) {
  

• 		perf->ctx_oactxctrl_offset = 0x128;
  

• 		perf->ctx_flexeu0_offset = 0x3de;
  

• 	} else {
  

• 		perf->ctx_oactxctrl_offset = 0x124;
  

• 		perf->ctx_flexeu0_offset = 0x78e;
  

• 	}
  

• 	perf->ctx_oactxctrl_offset = 0x124;
  

• 	perf->ctx_flexeu0_offset = 0x78e;
  

• perf->gen8_valid_ctx_bit = BIT(16);
  

  } else if (GRAPHICS_VER(i915) == 12) { perf->ops.is_valid_b_counter_reg =

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 2893a8659a8b..4319ae020c86 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) for_each_pipe(dev_priv, pipe) runtime->num_scalers[pipe] = 0;

• else if (GRAPHICS_VER(dev_priv) >= 10) {

• else if (GRAPHICS_VER(dev_priv) >= 11) { for_each_pipe(dev_priv, pipe) runtime->num_scalers[pipe] = 2; } else if (GRAPHICS_VER(dev_priv) == 9) {

@@ -282,7 +282,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) else if (GRAPHICS_VER(dev_priv) >= 11) for_each_pipe(dev_priv, pipe) runtime->num_sprites[pipe] = 6;

• else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))

• else if (IS_GEMINILAKE(dev_priv)) for_each_pipe(dev_priv, pipe) runtime->num_sprites[pipe] = 3; else if (IS_BROXTON(dev_priv)) {

-- 2.31.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Fri, Jul 23, 2021 at 05:11:12PM -0700, Lucas De Marchi wrote:

Remove registers that are not used anymore due to CNL removal and rename those that are.

Signed-off-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

drivers/gpu/drm/i915/i915_reg.h | 192 ++++++----------------- drivers/gpu/drm/i915/intel_device_info.c | 2 +- 2 files changed, 48 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8782d1723254..925cbdb53712 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)

/*

• • CNL/ICL Port/COMBO-PHY Registers

• • ICL Port/COMBO-PHY Registers
  */

#define _ICL_COMBOPHY_A 0x162000 #define _ICL_COMBOPHY_B 0x6C000 @@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) _RKL_COMBOPHY_D, \ _ADL_COMBOPHY_E)

-/* CNL/ICL Port CL_DW registers */ +/* ICL Port CL_DW registers */ #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 4 * (dw))

-#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) #define CL_POWER_DOWN_ENABLE (1 << 4) #define SUS_CLOCK_CONFIG (3 << 0) @@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) #define ICL_LANE_ENABLE_AUX (1 << 0)

-/* CNL/ICL Port COMP_DW registers */ +/* ICL Port COMP_DW registers */ #define _ICL_PORT_COMP 0x100 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_COMP + 4 * (dw))

-#define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) #define COMP_INIT (1 << 31)

-#define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))

-#define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) #define PROCESS_INFO_DOT_1 (1 << 26) @@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24)

-#define CNL_PORT_COMP_DW9 _MMIO(0x162124) #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))

-#define CNL_PORT_COMP_DW10 _MMIO(0x162128) #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))

-/* CNL/ICL Port PCS registers */ -#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 -#define _CNL_PORT_PCS_DW1_GRP_B 0x162384 -#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 -#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 -#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 -#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 -#define _CNL_PORT_PCS_DW1_LN0_B 0x162604 -#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 -#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 -#define _CNL_PORT_PCS_DW1_LN0_F 0x162804 -#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \

• 				    _CNL_PORT_PCS_DW1_GRP_AE, \
  

• 				    _CNL_PORT_PCS_DW1_GRP_B, \
  

• 				    _CNL_PORT_PCS_DW1_GRP_C, \
  

• 				    _CNL_PORT_PCS_DW1_GRP_D, \
  

• 				    _CNL_PORT_PCS_DW1_GRP_AE, \
  

• 				    _CNL_PORT_PCS_DW1_GRP_F))
  

-#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \

• 				    _CNL_PORT_PCS_DW1_LN0_AE, \
  

• 				    _CNL_PORT_PCS_DW1_LN0_B, \
  

• 				    _CNL_PORT_PCS_DW1_LN0_C, \
  

• 				    _CNL_PORT_PCS_DW1_LN0_D, \
  

• 				    _CNL_PORT_PCS_DW1_LN0_AE, \
  

• 				    _CNL_PORT_PCS_DW1_LN0_F))
  

+/* ICL Port PCS registers */ #define _ICL_PORT_PCS_AUX 0x300 #define _ICL_PORT_PCS_GRP 0x600 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) @@ -1998,34 +1967,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2)

-/* CNL/ICL Port TX registers */ -#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 -#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 -#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 -#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 -#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 -#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 -#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 -#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 -#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 -#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 -#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \

• 			       _CNL_PORT_TX_AE_GRP_OFFSET, \
  

• 			       _CNL_PORT_TX_B_GRP_OFFSET, \
  

• 			       _CNL_PORT_TX_B_GRP_OFFSET, \
  

• 			       _CNL_PORT_TX_D_GRP_OFFSET, \
  

• 			       _CNL_PORT_TX_AE_GRP_OFFSET, \
  

• 			       _CNL_PORT_TX_F_GRP_OFFSET) + \
  

• 			       4 * (dw))
  

-#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \

• 			       _CNL_PORT_TX_AE_LN0_OFFSET, \
  

• 			       _CNL_PORT_TX_B_LN0_OFFSET, \
  

• 			       _CNL_PORT_TX_B_LN0_OFFSET, \
  

• 			       _CNL_PORT_TX_D_LN0_OFFSET, \
  

• 			       _CNL_PORT_TX_AE_LN0_OFFSET, \
  

• 			       _CNL_PORT_TX_F_LN0_OFFSET) + \
  

• 			       4 * (dw))
  

+/* ICL Port TX registers */ #define _ICL_PORT_TX_AUX 0x380 #define _ICL_PORT_TX_GRP 0x680 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) @@ -2037,8 +1979,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_TX_LN(ln) + 4 * (dw))

-#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) -#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) #define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) @@ -2051,13 +1991,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RCOMP_SCALAR(x) ((x) << 0) #define RCOMP_SCALAR_MASK (0xFF << 0)

-#define _CNL_PORT_TX_DW4_LN0_AE 0x162450 -#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 -#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) -#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) -#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \

• 			   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
  

• 				    _CNL_PORT_TX_DW4_LN0_AE)))
  

#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) #define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) @@ -2070,8 +2003,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CURSOR_COEFF(x) ((x) << 0) #define CURSOR_COEFF_MASK (0x3F << 0)

-#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) -#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) #define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) @@ -2083,8 +2014,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT_MASK (0x7 << 3)

-#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) -#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) #define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) @@ -8135,7 +8064,6 @@ enum { #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)

#define CHICKEN_MISC_2 _MMIO(0x42084) -#define CNL_COMP_PWR_DOWN (1 << 23) #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) #define GLK_CL2_PWR_DOWN (1 << 12) @@ -8175,7 +8103,7 @@ enum { [TRANSCODER_D] = _CHICKEN_TRANS_D)) #define HSW_FRAME_START_DELAY_MASK (3 << 27) #define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ -#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ +#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK */ #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ @@ -8241,7 +8169,6 @@ enum { #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) #define ICL_DELAY_PMRSP (1 << 22) #define MASK_WAKEMEM (1 << 13) -#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)

#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) @@ -8262,10 +8189,9 @@ enum { #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) -#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) +#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)

#define SKL_DSSM _MMIO(0x51004) -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) @@ -8364,7 +8290,6 @@ enum {

/* GEN8 chicken */ #define HDC_CHICKEN0 _MMIO(0x7300) -#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) #define ICL_HDC_MODE _MMIO(0xE5F4) #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) @@ -9540,7 +9465,6 @@ enum { #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) -#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)

#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) @@ -9721,15 +9645,12 @@ enum { /* HSW/BDW power well */ #define HSW_PW_CTL_IDX_GLOBAL 15

-/* SKL/BXT/GLK/CNL power wells */ +/* SKL/BXT/GLK power wells */ #define SKL_PW_CTL_IDX_PW_2 15 #define SKL_PW_CTL_IDX_PW_1 14 -#define CNL_PW_CTL_IDX_AUX_F 12 -#define CNL_PW_CTL_IDX_AUX_D 11 #define GLK_PW_CTL_IDX_AUX_C 10 #define GLK_PW_CTL_IDX_AUX_B 9 #define GLK_PW_CTL_IDX_AUX_A 8 -#define CNL_PW_CTL_IDX_DDI_F 6 #define SKL_PW_CTL_IDX_DDI_D 4 #define SKL_PW_CTL_IDX_DDI_C 3 #define SKL_PW_CTL_IDX_DDI_B 2 @@ -10127,11 +10048,11 @@ enum skl_power_gate { #define TRANS_DDI_BPC_10 (1 << 20) #define TRANS_DDI_BPC_6 (2 << 20) #define TRANS_DDI_BPC_12 (3 << 20) -#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */ +#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) #define TRANS_DDI_PVSYNC (1 << 17) #define TRANS_DDI_PHSYNC (1 << 16) -#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */ +#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) @@ -10487,17 +10408,6 @@ enum skl_power_gate { #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)

-/*

• • CNL Clocks
• */

-#define DPCLKA_CFGCR0 _MMIO(0x6C200) -#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \

• 				      (port) + 10))
  

-#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \

• 				(port) * 2)
  

-#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) -#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))

/* ICL Clocks */ #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) @@ -10730,60 +10640,52 @@ enum skl_power_gate { _MG_PLL_TDC_COLDST_BIAS_PORT1, \ _MG_PLL_TDC_COLDST_BIAS_PORT2)

-#define _CNL_DPLL0_CFGCR0 0x6C000 -#define _CNL_DPLL1_CFGCR0 0x6C080 -#define DPLL_CFGCR0_HDMI_MODE (1 << 30) -#define DPLL_CFGCR0_SSC_ENABLE (1 << 29) -#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) -#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) -#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) -#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) -#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) -#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) -#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) -#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) -#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) -#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) -#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) -#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) -#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) -#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) -#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)

-#define _CNL_DPLL0_CFGCR1 0x6C004 -#define _CNL_DPLL1_CFGCR1 0x6C084 -#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) -#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) -#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) -#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) -#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) -#define DPLL_CFGCR1_KDIV_MASK (7 << 6) -#define DPLL_CFGCR1_KDIV_SHIFT (6) -#define DPLL_CFGCR1_KDIV(x) ((x) << 6) -#define DPLL_CFGCR1_KDIV_1 (1 << 6) -#define DPLL_CFGCR1_KDIV_2 (2 << 6) -#define DPLL_CFGCR1_KDIV_3 (4 << 6) -#define DPLL_CFGCR1_PDIV_MASK (0xf << 2) -#define DPLL_CFGCR1_PDIV_SHIFT (2) -#define DPLL_CFGCR1_PDIV(x) ((x) << 2) -#define DPLL_CFGCR1_PDIV_2 (1 << 2) -#define DPLL_CFGCR1_PDIV_3 (2 << 2) -#define DPLL_CFGCR1_PDIV_5 (4 << 2) -#define DPLL_CFGCR1_PDIV_7 (8 << 2) -#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) -#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) -#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) -#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)

#define _ICL_DPLL0_CFGCR0 0x164000 #define _ICL_DPLL1_CFGCR0 0x164080 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ _ICL_DPLL1_CFGCR0) +#define DPLL_CFGCR0_HDMI_MODE (1 << 30) +#define DPLL_CFGCR0_SSC_ENABLE (1 << 29) +#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) +#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) +#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) +#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) +#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) +#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) +#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) +#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) +#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) +#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) +#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) +#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) +#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) +#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)

#define _ICL_DPLL0_CFGCR1 0x164004 #define _ICL_DPLL1_CFGCR1 0x164084 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ _ICL_DPLL1_CFGCR1) +#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) +#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) +#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) +#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) +#define DPLL_CFGCR1_KDIV_MASK (7 << 6) +#define DPLL_CFGCR1_KDIV_SHIFT (6) +#define DPLL_CFGCR1_KDIV(x) ((x) << 6) +#define DPLL_CFGCR1_KDIV_1 (1 << 6) +#define DPLL_CFGCR1_KDIV_2 (2 << 6) +#define DPLL_CFGCR1_KDIV_3 (4 << 6) +#define DPLL_CFGCR1_PDIV_MASK (0xf << 2) +#define DPLL_CFGCR1_PDIV_SHIFT (2) +#define DPLL_CFGCR1_PDIV(x) ((x) << 2) +#define DPLL_CFGCR1_PDIV_2 (1 << 2) +#define DPLL_CFGCR1_PDIV_3 (2 << 2) +#define DPLL_CFGCR1_PDIV_5 (4 << 2) +#define DPLL_CFGCR1_PDIV_7 (8 << 2) +#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) +#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) +#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)

#define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 4319ae020c86..ffe3b5d89a63 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -365,7 +365,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->display.has_dmc = 0;

if (DISPLAY_VER(dev_priv) >= 10 &&

•     (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
  

•     (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
  info->display.has_dsc = 0;
  

  }

-- 2.31.1

---

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