Use a different value for system clock offset in the ppl/llp ratio calculations for clocks higher than 500 Mhz.
Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 231041b269f5..7e2371ffcb18 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -482,6 +482,10 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_dsi *kmb_dsi, return 0; }
+#define CLK_DIFF_LOW 50 +#define CLK_DIFF_HI 60 +#define SYSCLK_500 500 + static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) { @@ -492,7 +496,12 @@ static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen, /* 500 Mhz system clock minus 50 to account for the difference in * MIPI clock speed in RTL tests */ - sysclk = kmb_dsi->sys_clk_mhz - 50; + if (kmb_dsi->sys_clk_mhz == SYSCLK_500) { + sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW; + } else { + /* 700 Mhz clk*/ + sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI; + }
/* PPL-Pixel Packing Layer, LLP-Low Level Protocol * Frame genartor timing parameters are clocked on the system clock,
For B0 silicon, the media driver pads the decoded video dmabufs for 256B alignment. This is the backing buffer of the framebuffer and info in the drm frame buffer is not correct for these buffers as this is done internally in the media driver. This change extracts the meta data info from dmabuf priv structure and uses that info for programming stride and offsets in kmb_plane_atomic_update().
v2: simplified logic
Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display") Signed-off-by: Edmund Dea edmund.j.dea@intel.com Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_plane.c | 58 ++++++++++++++++++++++++++------ drivers/gpu/drm/kmb/kmb_vidmem.h | 52 ++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/kmb/kmb_vidmem.h
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index ecee6782612d..e61c2798c206 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -3,6 +3,8 @@ * Copyright © 2018-2020 Intel Corporation */
+#include <linux/dma-buf.h> + #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> @@ -11,12 +13,14 @@ #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_managed.h> #include <drm/drm_plane_helper.h>
#include "kmb_drv.h" #include "kmb_plane.h" #include "kmb_regs.h" +#include "kmb_vidmem.h"
const u32 layer_irqs[] = { LCD_INT_VL0, @@ -296,6 +300,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned char plane_id; int num_planes; static dma_addr_t addr[MAX_SUB_PLANES]; + struct viv_vidmem_metadata *md = NULL; + struct drm_gem_object *gem_obj; + unsigned int cb_stride, cr_stride;
if (!plane || !new_plane_state || !old_plane_state) return; @@ -325,6 +332,16 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, drm_dbg(&kmb->drm, "src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", src_w, src_h, fb->format->format, fb->flags); + gem_obj = drm_gem_fb_get_obj(fb, plane_id); + if (gem_obj && gem_obj->import_attach && + gem_obj->import_attach->dmabuf && + gem_obj->import_attach->dmabuf->priv) { + md = gem_obj->import_attach->dmabuf->priv; + + /* Check if metadata is coming from hantro driver */ + if (md->magic != HANTRO_IMAGE_VIV_META_DATA_MAGIC) + md = NULL; + }
width = fb->width; height = fb->height; @@ -332,8 +349,13 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, drm_dbg(&kmb->drm, "dma_len=%d ", dma_len); kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[0]); + if (md) { + kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + md->plane[0].stride); + } else { + kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); + } kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), (width * fb->format->cpp[0]));
@@ -344,13 +366,19 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= get_bits_per_pixel(fb->format); /* Program Cb/Cr for planar formats */ if (num_planes > 1) { - kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), - width * fb->format->cpp[0]); - kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); - - addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, new_plane_state, - U_PLANE); + cb_stride = md ? md->plane[1].stride : + width * fb->format->cpp[0]; + kmb_write_lcd(kmb, + LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + cb_stride); + + if (md) { + addr[U_PLANE] = addr[Y_PLANE] + md->plane[1].offset; + } else { + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, + new_plane_state, + U_PLANE); + } /* check if Cb/Cr is swapped*/ if (num_planes == 3 && (val & LCD_LAYER_CRCB_ORDER)) kmb_write_lcd(kmb, @@ -362,17 +390,25 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, addr[U_PLANE]);
if (num_planes == 3) { + cr_stride = md ? md->plane[2].stride : + width * fb->format->cpp[0]; kmb_write_lcd(kmb, LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), - ((width) * fb->format->cpp[0])); + cr_stride);
kmb_write_lcd(kmb, LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), ((width) * fb->format->cpp[0]));
- addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, + if (md) { + addr[V_PLANE] = addr[Y_PLANE] + + md->plane[2].offset; + } else { + addr[V_PLANE] = + drm_fb_cma_get_gem_addr(fb, new_plane_state, V_PLANE); + }
/* check if Cb/Cr is swapped*/ if (val & LCD_LAYER_CRCB_ORDER) diff --git a/drivers/gpu/drm/kmb/kmb_vidmem.h b/drivers/gpu/drm/kmb/kmb_vidmem.h new file mode 100644 index 000000000000..06198d413f50 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_vidmem.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright © 2018-2020 Intel Corporation + */ + +#ifndef __KMB_VIDMEM_H__ +#define __KMB_VIDMEM_H__ + +#define HANTRO_MAGIC(ch0, ch1, ch2, ch3) \ + ((unsigned long)(unsigned char)(ch0) | \ + ((unsigned long)(unsigned char)(ch1) << 8) | \ + ((unsigned long)(unsigned char)(ch2) << 16) | \ + ((unsigned long)(unsigned char)(ch3) << 24)) + +#define HANTRO_IMAGE_VIV_META_DATA_MAGIC HANTRO_MAGIC('V', 'I', 'V', 'M') + +struct viv_vidmem_metadata { + u32 magic; // __FOURCC('v', 'i', 'v', 'm') + u32 dmabuf_size; // DMABUF buffer size in byte (Maximum 4GB) + u32 time_stamp; // time stamp for the DMABUF buffer + + u32 image_format; // ImageFormat, determined plane number. + u32 compressed; // if DMABUF buffer is compressed by DEC400 + struct { + u32 offset; // plane buffer address offset from DMABUF address + u32 stride; // pitch in bytes + u32 width; // width in pixels + u32 height; // height in pixels + + u32 tile_format; // uncompressed tile format + u32 compress_format; // tile mode for DEC400 + + /** tile status buffer offset within this plane buffer. when it is 0， + * indicates using separate tile status buffer + */ + u32 ts_offset; + /** fd of separate tile status buffer of the plane buffer */ + u32 ts_fd; + /** valid fd of the ts buffer in consumer side. */ + u32 ts_fd2; + /** the vpu virtual address for this ts data buffer */ + u32 ts_vaddr; + + /** gpu fastclear enabled for the plane buffer */ + u32 fc_enabled; + /** gpu fastclear color value (lower 32 bits) for the plane buffer */ + u32 fc_value_lower; + /** gpu fastclear color value (upper 32 bits) for the plane buffer */ + u32 fc_value_upper; + } plane[3]; +}; +#endif /*__KMB_VIDMEM_H__*/
KMB only supports single resolution(1080p), this commit checks for 1920x1080x60 or 1920x1080x59 in crtc_mode_valid. Also, modes with vfp < 4 are not supported in KMB display. This change prunes display modes with vfp < 4.
v2: added vfp check
Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Signed-off-by: Edmund Dea edmund.j.dea@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 34 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 16 ++++++++++++++-- 2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 44327bc629ca..08a45e813db7 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -185,11 +185,45 @@ static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, spin_unlock_irq(&crtc->dev->event_lock); }
+static enum drm_mode_status + kmb_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + int refresh; + struct drm_device *dev = crtc->dev; + int vfp = mode->vsync_start - mode->vdisplay; + + if (mode->vdisplay < KMB_CRTC_MAX_HEIGHT) { + drm_dbg(dev, "height = %d less than %d", + mode->vdisplay, KMB_CRTC_MAX_HEIGHT); + return MODE_BAD_VVALUE; + } + if (mode->hdisplay < KMB_CRTC_MAX_WIDTH) { + drm_dbg(dev, "width = %d less than %d", + mode->hdisplay, KMB_CRTC_MAX_WIDTH); + return MODE_BAD_HVALUE; + } + refresh = drm_mode_vrefresh(mode); + if (refresh < KMB_MIN_VREFRESH || refresh > KMB_MAX_VREFRESH) { + drm_dbg(dev, "refresh = %d less than %d or greater than %d", + refresh, KMB_MIN_VREFRESH, KMB_MAX_VREFRESH); + return MODE_BAD; + } + + if (vfp < KMB_CRTC_MIN_VFP) { + drm_dbg(dev, "vfp = %d less than %d", vfp, KMB_CRTC_MIN_VFP); + return MODE_BAD; + } + + return MODE_OK; +} + static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { .atomic_begin = kmb_crtc_atomic_begin, .atomic_enable = kmb_crtc_atomic_enable, .atomic_disable = kmb_crtc_atomic_disable, .atomic_flush = kmb_crtc_atomic_flush, + .mode_valid = kmb_crtc_mode_valid, };
int kmb_setup_crtc(struct drm_device *drm) diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index ebbaa5f422d5..d297218869e8 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -18,8 +18,20 @@
#define DRIVER_DATE "20210223" #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 1 - +#define DRIVER_MINOR 2 + +/* Platform definitions */ +#define KMB_CRTC_MIN_VFP 4 +#define KMB_CRTC_MAX_WIDTH 1920 /* max width in pixels */ +#define KMB_CRTC_MAX_HEIGHT 1080 /* max height in pixels */ +#define KMB_CRTC_MIN_WIDTH 1920 +#define KMB_CRTC_MIN_HEIGHT 1080 +#define KMB_FB_MAX_WIDTH 1920 +#define KMB_FB_MAX_HEIGHT 1080 +#define KMB_FB_MIN_WIDTH 1 +#define KMB_FB_MIN_HEIGHT 1 +#define KMB_MIN_VREFRESH 59 /*vertical refresh in Hz */ +#define KMB_MAX_VREFRESH 60 /*vertical refresh in Hz */ #define KMB_LCD_DEFAULT_CLK 200000000 #define KMB_SYS_CLK_MHZ 500
From: Edmund Dea edmund.j.dea@intel.com
Don't clear the shared DPHY registers common to MIPI Rx and MIPI Tx during DSI initialization since this was causing MIPI Rx reset. Rest of the writes are bitwise, so do not affect Mipi Rx side.
Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Signed-off-by: Edmund Dea edmund.j.dea@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 7e2371ffcb18..5bc6c84073a3 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -1393,11 +1393,6 @@ int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, mipi_tx_init_cfg.lane_rate_mbps = data_rate; }
- kmb_write_mipi(kmb_dsi, DPHY_ENABLE, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL0, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL1, 0); - kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0); - /* Initialize mipi controller */ mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg);
From: Edmund Dea edmund.j.dea@intel.com
Due to HW limitations, KMB cannot change height, width, or pixel format after initial plane configuration.
Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display") Signed-off-by: Edmund Dea edmund.j.dea@intel.com Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_crtc.c | 2 ++ drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_plane.c | 44 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/kmb/kmb_plane.h | 6 +++++ 4 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 08a45e813db7..0e42c40f0dce 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -232,6 +232,8 @@ int kmb_setup_crtc(struct drm_device *drm) struct kmb_plane *primary; int ret;
+ memset(kmb->init_disp_cfg, 0, sizeof(kmb->init_disp_cfg)); + primary = kmb_plane_init(drm); if (IS_ERR(primary)) return PTR_ERR(primary); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index d297218869e8..b3203f583a46 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -57,6 +57,7 @@ struct kmb_drm_private { spinlock_t irq_lock; int irq_lcd; int sys_clk_mhz; + struct disp_cfg init_disp_cfg[KMB_MAX_PLANES]; struct layer_status plane_status[KMB_MAX_PLANES]; int kmb_under_flow; int kmb_flush_done; diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index e61c2798c206..ae4ebba5ea2a 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -71,12 +71,26 @@ static const u32 kmb_formats_v[] = {
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { + struct kmb_drm_private *kmb; + struct kmb_plane *kmb_plane = to_kmb_plane(plane); int i; + int plane_id = kmb_plane->id; + struct disp_cfg init_disp_cfg;
+ kmb = to_kmb(plane->dev); + init_disp_cfg = kmb->init_disp_cfg[plane_id]; + /* Due to HW limitations, changing pixel format after initial + * plane configuration is not supported. + */ + if (init_disp_cfg.format && init_disp_cfg.format != format) { + drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration"); + return -EINVAL; + } for (i = 0; i < plane->format_count; i++) { if (plane->format_types[i] == format) return 0; } + return -EINVAL; }
@@ -85,11 +99,17 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct kmb_drm_private *kmb; + struct kmb_plane *kmb_plane = to_kmb_plane(plane); + int plane_id = kmb_plane->id; + struct disp_cfg init_disp_cfg; struct drm_framebuffer *fb; int ret; struct drm_crtc_state *crtc_state; bool can_position;
+ kmb = to_kmb(plane->dev); + init_disp_cfg = kmb->init_disp_cfg[plane_id]; fb = new_plane_state->fb; if (!fb || !new_plane_state->crtc) return 0; @@ -102,6 +122,16 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, return -EINVAL; if (new_plane_state->crtc_w < KMB_MIN_WIDTH || new_plane_state->crtc_h < KMB_MIN_HEIGHT) return -EINVAL; + + /* Due to HW limitations, changing plane height or width after + * initial plane configuration is not supported. + */ + if ((init_disp_cfg.width && init_disp_cfg.height) && + (init_disp_cfg.width != fb->width || + init_disp_cfg.height != fb->height)) { + drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration"); + return -EINVAL; + } can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY); crtc_state = drm_atomic_get_existing_crtc_state(state, @@ -300,6 +330,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned char plane_id; int num_planes; static dma_addr_t addr[MAX_SUB_PLANES]; + struct disp_cfg *init_disp_cfg; struct viv_vidmem_metadata *md = NULL; struct drm_gem_object *gem_obj; unsigned int cb_stride, cr_stride; @@ -324,7 +355,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, } spin_unlock_irq(&kmb->irq_lock);
- src_w = (new_plane_state->src_w >> 16); + init_disp_cfg = &kmb->init_disp_cfg[plane_id]; + src_w = new_plane_state->src_w >> 16; src_h = new_plane_state->src_h >> 16; crtc_x = new_plane_state->crtc_x; crtc_y = new_plane_state->crtc_y; @@ -484,6 +516,16 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
/* Enable DMA */ kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + + /* Save initial display config */ + if (!init_disp_cfg->width || + !init_disp_cfg->height || + !init_disp_cfg->format) { + init_disp_cfg->width = width; + init_disp_cfg->height = height; + init_disp_cfg->format = fb->format->format; + } + drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));
diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 486490f7a3ec..99207b35365c 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -62,6 +62,12 @@ struct layer_status { u32 ctrl; };
+struct disp_cfg { + unsigned int width; + unsigned int height; + unsigned int format; +}; + struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); #endif /* __KMB_PLANE_H__ */
Check for Overflow bits for layer3 in the irq handler.
Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index f54392ec4fab..bb7eca9e13ae 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -381,7 +381,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) if (val & LAYER3_DMA_FIFO_UNDERFLOW) drm_dbg(&kmb->drm, "LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); - if (val & LAYER3_DMA_FIFO_UNDERFLOW) + if (val & LAYER3_DMA_FIFO_OVERFLOW) drm_dbg(&kmb->drm, "LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); }
On KMB, ADV bridge must be programmed and powered on prior to MIPI DSI HW initialization.
Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_dsi.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 5bc6c84073a3..1cca0fe6f35f 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -1341,6 +1341,7 @@ static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi) return; }
+ drm_bridge_chain_enable(adv_bridge); /* DISABLE MIPI->CIF CONNECTION */ regmap_write(msscam, MSS_MIPI_CIF_CFG, 0);
From: Edmund Dea edmund.j.dea@intel.com
Enable support for fbcon (framebuffer console). The user can initialize fbcon by loading kmb-drm with the parameter console=1.
v2: added missing static clk_enable
Signed-off-by: Edmund Dea edmund.j.dea@intel.com Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com --- drivers/gpu/drm/kmb/kmb_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index bb7eca9e13ae..b4c29ae297c8 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -5,6 +5,7 @@
#include <linux/clk.h> #include <linux/module.h> +#include <linux/moduleparam.h> #include <linux/of_graph.h> #include <linux/of_platform.h> #include <linux/of_reserved_mem.h> @@ -15,6 +16,7 @@
#include <drm/drm_atomic_helper.h> #include <drm/drm_drv.h> +#include <drm/drm_fb_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_irq.h> @@ -25,6 +27,12 @@ #include "kmb_dsi.h" #include "kmb_regs.h"
+/* Module Parameters */ +static bool console; +module_param(console, bool, 0400); +MODULE_PARM_DESC(console, + "Enable framebuffer console support (0=disable [default], 1=on)"); + static int kmb_display_clk_enable(struct kmb_drm_private *kmb) { int ret = 0; @@ -545,6 +553,9 @@ static int kmb_probe(struct platform_device *pdev) if (ret) goto err_register;
+ if (console) + drm_fbdev_generic_setup(&kmb->drm, 32); + return 0;
err_register:
Hi Anitha,
On Tue, Aug 03, 2021 at 03:04:45PM -0700, Anitha Chrisanthus wrote:
Use a different value for system clock offset in the ppl/llp ratio calculations for clocks higher than 500 Mhz.
Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver") Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com
drivers/gpu/drm/kmb/kmb_dsi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 231041b269f5..7e2371ffcb18 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -482,6 +482,10 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_dsi *kmb_dsi, return 0; }
+#define CLK_DIFF_LOW 50 +#define CLK_DIFF_HI 60 +#define SYSCLK_500 500
static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) { @@ -492,7 +496,12 @@ static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen, /* 500 Mhz system clock minus 50 to account for the difference in * MIPI clock speed in RTL tests */
The comment should be updated to match the code.
Sam
- sysclk = kmb_dsi->sys_clk_mhz - 50;
if (kmb_dsi->sys_clk_mhz == SYSCLK_500) {
sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW;} else {
/* 700 Mhz clk*/sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI;}
/* PPL-Pixel Packing Layer, LLP-Low Level Protocol
- Frame genartor timing parameters are clocked on the system clock,
-- 2.25.1
dri-devel@lists.freedesktop.org
-
Anitha Chrisanthus -
Sam Ravnborg