Enable DP driver for sc7180.

This change depends-on following series: https://patchwork.freedesktop.org/series/78247/ and https://patchwork.freedesktop.org/patch/351990/

Signed-off-by: Tanmay Shah tanmay@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 58 ++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 998f101ad623..989960d2200b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1557,10 +1557,19 @@ ports { #address-cells = <1>; #size-cells = <0>;

+ port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = + <&dsi0_in>; + }; + }; + port@0 { reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + dpu_intf0_out: endpoint { + remote-endpoint = + <&dp_in>; }; }; }; @@ -1634,6 +1643,47 @@ dsi_phy: dsi-phy@ae94400 { }; };

+ msm_dp: displayport-controller@ae90000{ + status = "ok"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + reg = <0 0xae90000 0 0x1400>; + reg-names = "dp_controller"; + + interrupt-parent = <&mdss>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + clock-names = "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel", + "pixel_rcg"; + #clock-cells = <1>; + + data-lanes = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = + <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sc7180-dispcc"; reg = <0 0x0af00000 0 0x200000>; @@ -1641,8 +1691,8 @@ dispcc: clock-controller@af00000 { <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>; + <&msm_dp 0>, + <&msm_dp 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk",