From: Ben Widawsky ben@bwidawsk.net

This got lost on rebase, I believe

Signed-off-by: Ben Widawsky benjamin.widawsky@intel.com --- intel/intel_bufmgr_gem.c | 2 ++ intel/intel_decode.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 45a26da..71f140f 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3662,6 +3662,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->gen = 8; else if (IS_GEN9(bufmgr_gem->pci_device)) bufmgr_gem->gen = 9; + else if (IS_GEN10(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 10; else { free(bufmgr_gem); bufmgr_gem = NULL; diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 2721ffd..3a81500 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid) ctx->devid = devid; ctx->out = stdout;

- if (IS_GEN9(devid)) + if (IS_GEN10(devid)) + ctx->gen = 10; + else if (IS_GEN9(devid)) ctx->gen = 9; else if (IS_GEN8(devid)) ctx->gen = 8;

Reviewed-by: Clinton Taylor clinton.a.taylor@intel.com

-Clint

On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa anusha.srivatsa@intel.com Cc: Clinton Taylor clinton.a.taylor@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@intel.com

---

intel/intel_chipset.h | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 891b50f..e6b49d7 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -233,6 +233,11 @@ #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8

+#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 +#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A +#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 +#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A

• #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \

@@ -496,5 +501,13 @@ IS_GEN8(dev) || \ IS_GEN9(dev))

+#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \

• 		 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
  

• 		 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
  

• 		 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
  

+#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))

+#define IS_GEN10(devid) (IS_CANNONLAKE(devid))

#endif /* _INTEL_CHIPSET_H */