Hi!
This adds D3 support to the DU and LVDS drivers, not including LVDS PLL support.
It also adds LVDS encoders to the D3 device tree, and LVDS decoder, HDMI encoder and HDMI output connector to the Draak device tree.
In theory that should be good enough to provide HDMI output on the Draak board, but in practice the lack of LVDS PLL support prevents generation of close-enough dot clock frequencies.
This series is based on renesas-drivers-2018-05-02-v4.17-rc3 and requires Jacopo's "drm: bridge: Add thc63lvd1024 LVDS decoder driver" patch.
CU Uli
Kieran Bingham (1): arm64: dts: renesas: r8a77995: Add LVDS support
Koji Matsuoka (1): drm: rcar-du: Add r8a77995 device support
Ulrich Hecht (3): drm: rcar-du: lvds: Add R8A77995 support arm64: dts: renesas: r8a77995-draak: add HDMI output arm64: dts: renesas: r8a77995-draak: add X12 input dot clock
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 91 ++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 ++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++ drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++ 4 files changed, 179 insertions(+)
From: Koji Matsuoka koji.matsuoka.xm@renesas.com
Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver.
Signed-off-by: Koji Matsuoka koji.matsuoka.xm@renesas.com Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com --- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 05745e8..ba82842 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -266,6 +266,31 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .num_lvds = 1, };
+static const struct rcar_du_device_info rcar_du_r8a77995_info = { + .gen = 3, + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS + | RCAR_DU_FEATURE_VSP1_SOURCE, + .num_crtcs = 2, + .routes = { + /* R8A77995 has two LVDS output and one RGB output. + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0) | BIT(1), + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), + .port = 1, + }, + [RCAR_DU_OUTPUT_LVDS1] = { + .possible_crtcs = BIT(1), + .port = 2, + }, + }, + .num_lvds = 2, +}; + static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info }, @@ -278,6 +303,7 @@ static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info }, + { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a77995_info }, { } };
On Tue, May 15, 2018 at 02:20:36PM +0200, Ulrich Hecht wrote:
From: Koji Matsuoka koji.matsuoka.xm@renesas.com
Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver.
Signed-off-by: Koji Matsuoka koji.matsuoka.xm@renesas.com Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
Reviewed-by: Simon Horman horms+renesas@verge.net.au
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 05745e8..ba82842 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -266,6 +266,31 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .num_lvds = 1, };
+static const struct rcar_du_device_info rcar_du_r8a77995_info = {
- .gen = 3,
- .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS| RCAR_DU_FEATURE_VSP1_SOURCE,- .num_crtcs = 2,
- .routes = {
/* R8A77995 has two LVDS output and one RGB output.*/[RCAR_DU_OUTPUT_DPAD0] = {.possible_crtcs = BIT(0) | BIT(1),.port = 0,},[RCAR_DU_OUTPUT_LVDS0] = {.possible_crtcs = BIT(0),.port = 1,},[RCAR_DU_OUTPUT_LVDS1] = {.possible_crtcs = BIT(1),.port = 2,},- },
- .num_lvds = 2,
+};
static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info }, @@ -278,6 +303,7 @@ static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
- { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a77995_info }, { }
};
-- 2.7.4
Hi Ulrich,
Thank you for the patch.
On Tuesday, 15 May 2018 15:20:36 EEST Ulrich Hecht wrote:
From: Koji Matsuoka koji.matsuoka.xm@renesas.com
Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver.
Signed-off-by: Koji Matsuoka koji.matsuoka.xm@renesas.com Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 05745e8..ba82842 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -266,6 +266,31 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .num_lvds = 1, };
+static const struct rcar_du_device_info rcar_du_r8a77995_info = {
- .gen = 3,
- .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
| RCAR_DU_FEATURE_EXT_CTRL_REGS| RCAR_DU_FEATURE_VSP1_SOURCE,- .num_crtcs = 2,
- .routes = {
/* R8A77995 has two LVDS output and one RGB output.*/
This comment holds on a single line.
Apart from that the patch looks good to me, but it conflicts with
commit 5361cc7f8e9146f393cfcb76890d8c80a4e73086 Author: Kieran Bingham kieran.bingham+renesas@ideasonboard.com Date: Fri Apr 27 23:21:52 2018 +0100
drm: rcar-du: Split CRTC handling to support hardware indexing
that has been queued in Dave's DRM tree for v4.18. The num_crtcs field has been replaced with a channels_mask field. I can fix when applying but I can't test the result as I don't have a D3 board, so I'd prefer if you could submit a v2 rebased on top of Dave's drm-next branch.
I'm also wondering whether we also need
commit 6f3850955384cff722f02530f570806897b02a87 Author: Koji Matsuoka koji.matsuoka.xm@renesas.com Date: Wed Dec 6 20:30:24 2017 +0900
drm: rcar-du: Fix digital RGB routing for R8A77995
from the BSP. What's your opinion ?
[RCAR_DU_OUTPUT_DPAD0] = {.possible_crtcs = BIT(0) | BIT(1),.port = 0,},[RCAR_DU_OUTPUT_LVDS0] = {.possible_crtcs = BIT(0),.port = 1,},[RCAR_DU_OUTPUT_LVDS1] = {.possible_crtcs = BIT(1),.port = 2,},- },
- .num_lvds = 2,
+};
static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info }, @@ -278,6 +303,7 @@ static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info }, { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
- { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a77995_info }, { }
};
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com --- drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, };
+static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = { + .gen = 3, + .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN, +}; + static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info }, { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info }, @@ -519,6 +524,7 @@ static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info }, + { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info }, { } };
On Tue, May 15, 2018 at 02:20:37PM +0200, Ulrich Hecht wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, };
+static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
- .gen = 3,
- .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
+};
This new structure seems to be identical to rcar_lvds_r8a77970_info. Could we consolidate somehow?
static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info }, { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info }, @@ -519,6 +524,7 @@ static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
- { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info }, { }
};
-- 2.7.4
Hello!
On 5/16/2018 10:54 AM, Simon Horman wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, };
+static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
- .gen = 3,
- .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
+};
This new structure seems to be identical to rcar_lvds_r8a77970_info. Could we consolidate somehow?
In my book, that one has 2 quirk flags. What tree are you looking at?
[...]
MBR, Sergei
On Wed, May 16, 2018 at 10:59 AM, Sergei Shtylyov sergei.shtylyov@cogentembedded.com wrote:
Hello!
On 5/16/2018 10:54 AM, Simon Horman wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, }; +static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
.gen = 3,.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,+};
This new structure seems to be identical to rcar_lvds_r8a77970_info.
Could we consolidate somehow?
In my book, that one has 2 quirk flags. What tree are you looking at?
IIRC the other one was for the PLL, which is not supported yet.
CU Uli
On 05/16/2018 04:06 PM, Ulrich Hecht wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, }; +static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
.gen = 3,.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,+};
This new structure seems to be identical to rcar_lvds_r8a77970_info.
Could we consolidate somehow?
In my book, that one has 2 quirk flags. What tree are you looking at?
IIRC the other one was for the PLL, which is not supported yet.
V3M PLL is surely supported and it's surely different from D3 one. My point was that r8a77970 data can't be reused...
CU Uli
MBR, Sergei
On Wed, May 16, 2018 at 11:59:32AM +0300, Sergei Shtylyov wrote:
Hello!
On 5/16/2018 10:54 AM, Simon Horman wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, }; +static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
- .gen = 3,
- .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
+};
This new structure seems to be identical to rcar_lvds_r8a77970_info. Could we consolidate somehow?
In my book, that one has 2 quirk flags. What tree are you looking at?
True, my eyes seem to have deceived me.
Hi Ulrich,
Thank you for the patch.
On Tuesday, 15 May 2018 15:20:37 EEST Ulrich Hecht wrote:
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 3d2d3bb..58fb9f8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN, };
+static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
- .gen = 3,
- .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
I'm afraid this won't be enough. With this patch the driver will call rcar_lvds_lvdpllcr_gen3(), which writes values to the LVDPLLCR register that don't match the register layout for D3.
While I'm fine with an initial version that doesn't support fine-grained control of the LVDS PLL to achieve the HDMI clock accuracy requirements, we need the LVDS encoder to be at least functional for the patches to get merged.
There are also other registers not related to the PLL that need to be set (such as the LVDSTRIPE register), and other differences in register layouts (for instance the D3 doesn't have a PLLON bit in register LVDC0).
Even the LVEN bit seems to need special handling on D3. According to version 1.00 of the datasheet it should be set to 1 at the same time as bit LVRES.
Could you please study the datasheet in details and update the code accordingly ?
+};
static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info }, { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info }, @@ -519,6 +524,7 @@ static const struct of_device_id rcar_lvds_of_table[] = { { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info }, { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
- { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info
}, { } };
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865..8e78110d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -757,12 +757,68 @@ port@1 { reg = <1>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; }; };
port@2 { reg = <2>; du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a77995-lvds"; + reg = <0 0xfeb90000 0 0x20>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds-encoder@feb90100 { + compatible = "renesas,r8a77995-lvds"; + reg = <0 0xfeb90100 0 0x20>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + + port@1 { + reg = <1>; + lvds1_out: endpoint { }; }; };
On Tue, May 15, 2018 at 02:20:38PM +0200, Ulrich Hecht wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
This looks fine but I will wait to see if there are other reviews before applying.
Reviewed-by: Simon Horman horms+renesas@verge.net.au
Hi Ulrich,
Thank you for the patch.
On Tuesday, 15 May 2018 15:20:38 EEST Ulrich Hecht wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865..8e78110d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -757,12 +757,68 @@ port@1 { reg = <1>; du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>; }; }; port@2 { reg = <2>; du_out_lvds1: endpoint {remote-endpoint = <&lvds1_in>;};};};};lvds0: lvds-encoder@feb90000 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90000 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds0_in: endpoint {remote-endpoint = <&du_out_lvds0>;};};port@1 {reg = <1>;lvds0_out: endpoint {};};};};lvds1: lvds-encoder@feb90100 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90100 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;
While there seems to be a single clock for both LVDS encoders, it appears that two separate reset lines are used.
Apart from that,
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
Given that the LVDS encoder driver isn't functional yet I wouldn't rule out a need to update the LVDS DT bindings in order to properly support D3. I don't mind if this patch gets merged already (provided the reset problem gets fixed of course), as long as it won't be considered a blocker for DT bindings rework. Otherwise I'd prefer delaying upstreaming until the whole series can be tested.
status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds1_in: endpoint {remote-endpoint = <&du_out_lvds1>;};};port@1 {reg = <1>;lvds1_out: endpoint { }; }; };
Hi Laurent,
On Sun, May 20, 2018 at 10:50 AM, Laurent Pinchart laurent.pinchart@ideasonboard.com wrote:
On Tuesday, 15 May 2018 15:20:38 EEST Ulrich Hecht wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865..8e78110d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -757,12 +757,68 @@ port@1 { reg = <1>; du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>; }; }; port@2 { reg = <2>; du_out_lvds1: endpoint {remote-endpoint = <&lvds1_in>;};};};};lvds0: lvds-encoder@feb90000 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90000 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds0_in: endpoint {remote-endpoint = <&du_out_lvds0>;};};port@1 {reg = <1>;lvds0_out: endpoint {};};};};lvds1: lvds-encoder@feb90100 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90100 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;While there seems to be a single clock for both LVDS encoders, it appears that two separate reset lines are used.
Nice catch!
So you can reset the individual LVDS instances, but not the individual DU instances. Doh...
Gr{oetje,eeting}s,
Geert
Hi Ulrich, I know this series needs to be re-spin when the D3/E3 LVDS PLL support will be added, but since I need it for testing on D3 the LVDS interface reset support, I noticed a small issue which I thought it is worth reporting.
On Tue, May 15, 2018 at 02:20:38PM +0200, Ulrich Hecht wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865..8e78110d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -757,12 +757,68 @@ port@1 { reg = <1>; du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>; }; }; port@2 { reg = <2>; du_out_lvds1: endpoint {remote-endpoint = <&lvds1_in>;};};};};lvds0: lvds-encoder@feb90000 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90000 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds0_in: endpoint {remote-endpoint = <&du_out_lvds0>;};};port@1 {reg = <1>;lvds0_out: endpoint {};};};};lvds1: lvds-encoder@feb90100 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90100 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;
The LVDS-IF1 CPG reset is SRCR7[26], this I think this should be <&cpg 726>
Please note that the most recent chip manual release has probably an error at page 3180, section 37-32
5. When display on in the LVDS0-IF, it is necessary to reset (SRCR7[27]) and reset clearing (SRSTCLR7[27]) LVDS0-IF module. When display on in the LVDS1-IF, it is necessary to reset (SRCR7[26]) and reset clearing (SRSTCLR7[26]) LVDS0-IF module ^- This should probablt be LVDS1-IF
Thanks j
status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds1_in: endpoint {remote-endpoint = <&du_out_lvds1>;};};port@1 {reg = <1>;lvds1_out: endpoint { }; }; };-- 2.7.4
On August 1, 2018 at 12:35 PM jacopo mondi jacopo@jmondi.org wrote:
Hi Ulrich, I know this series needs to be re-spin when the D3/E3 LVDS PLL support will be added, but since I need it for testing on D3 the LVDS interface reset support, I noticed a small issue which I thought it is worth reporting.
On Tue, May 15, 2018 at 02:20:38PM +0200, Ulrich Hecht wrote:
From: Kieran Bingham kieran.bingham+renesas@ideasonboard.com
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham kieran.bingham+renesas@ideasonboard.com [uli: moved lvds* into the soc node, added PM domains, resets] Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index ba98865..8e78110d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -757,12 +757,68 @@ port@1 { reg = <1>; du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>; }; }; port@2 { reg = <2>; du_out_lvds1: endpoint {remote-endpoint = <&lvds1_in>;};};};};lvds0: lvds-encoder@feb90000 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90000 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;lvds0_in: endpoint {remote-endpoint = <&du_out_lvds0>;};};port@1 {reg = <1>;lvds0_out: endpoint {};};};};lvds1: lvds-encoder@feb90100 {compatible = "renesas,r8a77995-lvds";reg = <0 0xfeb90100 0 0x20>;clocks = <&cpg CPG_MOD 727>;power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;resets = <&cpg 727>;The LVDS-IF1 CPG reset is SRCR7[26], this I think this should be <&cpg 726>
Please note that the most recent chip manual release has probably an error at page 3180, section 37-32
- When display on in the LVDS0-IF, it is necessary to reset (SRCR7[27]) and reset clearing (SRSTCLR7[27])
LVDS0-IF module. When display on in the LVDS1-IF, it is necessary to reset (SRCR7[26]) and reset clearing (SRSTCLR7[26]) LVDS0-IF module ^- This should probablt be LVDS1-IF
Thanks for the hint, I will keep this in mind.
CU Uli
Adds LVDS decoder, HDMI encoder and connector for Draak boards.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 80 ++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 9d73de8..b059e32 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -27,6 +27,41 @@ stdout-path = "serial0:115200n8"; };
+ lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <®_3p3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + vga { compatible = "vga-connector";
@@ -154,6 +189,39 @@ reg = <0x50>; pagesize = <8>; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>, <0x3f>, <0x38>, <0x3c>; + reg-names = "main", "edid", "packet", "cec"; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; };
&i2c1 { @@ -176,6 +244,18 @@ }; };
+&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + &ehci0 { status = "okay"; };
On Tue, May 15, 2018 at 02:20:39PM +0200, Ulrich Hecht wrote:
Adds LVDS decoder, HDMI encoder and connector for Draak boards.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 80 ++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)
This looks fine but I will wait to see if there are other reviews before applying.
Reviewed-by: Simon Horman horms+renesas@verge.net.au
Hi Ulrich,
Thank you for the patch.
On Tuesday, 15 May 2018 15:20:39 EEST Ulrich Hecht wrote:
Adds LVDS decoder, HDMI encoder and connector for Draak boards.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 9d73de8..b059e32 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -27,6 +27,41 @@ stdout-path = "serial0:115200n8"; };
- lvds-decoder {
compatible = "thine,thc63lvd1024";vcc-supply = <®_3p3v>;ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;thc63lvd1024_in: endpoint {remote-endpoint = <&lvds0_out>;};};port@2 {reg = <2>;thc63lvd1024_out: endpoint {remote-endpoint = <&adv7511_in>;};};};- };
- hdmi-out {
compatible = "hdmi-connector";type = "a";port {hdmi_con_out: endpoint {remote-endpoint = <&adv7511_out>;};};- };
- vga { compatible = "vga-connector";
@@ -154,6 +189,39 @@ reg = <0x50>; pagesize = <8>; };
- hdmi@39 {
compatible = "adi,adv7511w";reg = <0x39>, <0x3f>, <0x38>, <0x3c>;reg-names = "main", "edid", "packet", "cec";interrupt-parent = <&gpio1>;interrupts = <28 IRQ_TYPE_LEVEL_LOW>;adi,input-depth = <8>;adi,input-colorspace = "rgb";adi,input-clock = "1x";adi,input-style = <1>;adi,input-justification = "evenly";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;adv7511_in: endpoint {remote-endpoint = <&thc63lvd1024_out>;};};port@1 {reg = <1>;adv7511_out: endpoint {remote-endpoint = <&hdmi_con_out>;};};};- };
};
&i2c1 { @@ -176,6 +244,18 @@ }; };
+&lvds0 {
- status = "okay";
- ports {
port@1 {lvds0_out: endpoint {remote-endpoint = <&thc63lvd1024_in>;};};- };
+};
&ehci0 { status = "okay"; };
74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index b059e32..04d2018 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -117,6 +117,12 @@ regulator-boot-on; regulator-always-on; }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; };
&extal_clk { @@ -235,6 +241,11 @@ pinctrl-names = "default"; status = "okay";
+ clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x12_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + ports { port@0 { endpoint {
On Tue, May 15, 2018 at 02:20:40PM +0200, Ulrich Hecht wrote:
74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
This looks fine but I will wait to see if there are other reviews before applying.
Reviewed-by: Simon Horman horms+renesas@verge.net.au
Hi Ulrich,
Thank you for the patch.
On Wednesday, 16 May 2018 11:38:22 EEST Simon Horman wrote:
On Tue, May 15, 2018 at 02:20:40PM +0200, Ulrich Hecht wrote:
74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
This looks fine but I will wait to see if there are other reviews before applying.
Reviewed-by: Simon Horman horms+renesas@verge.net.au
As far as I'm concerned this patch can be merged already. I would however possibly hold off merging patch 3/5 and 4/5 until they can be tested.
On Sun, May 20, 2018 at 11:58:36AM +0300, Laurent Pinchart wrote:
Hi Ulrich,
Thank you for the patch.
On Wednesday, 16 May 2018 11:38:22 EEST Simon Horman wrote:
On Tue, May 15, 2018 at 02:20:40PM +0200, Ulrich Hecht wrote:
74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.
Signed-off-by: Ulrich Hecht ulrich.hecht+renesas@gmail.com
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
This looks fine but I will wait to see if there are other reviews before applying.
Reviewed-by: Simon Horman horms+renesas@verge.net.au
As far as I'm concerned this patch can be merged already. I would however possibly hold off merging patch 3/5 and 4/5 until they can be tested.
Thanks, I have applied this patch for v4.19.
As per your suggestion, I have marked patches 3/5 and 4/5 as deferred pending testing.
Hi Ulrich,
On Tuesday, 15 May 2018 15:20:35 EEST Ulrich Hecht wrote:
Hi!
This adds D3 support to the DU and LVDS drivers, not including LVDS PLL support.
It also adds LVDS encoders to the D3 device tree, and LVDS decoder, HDMI encoder and HDMI output connector to the Draak device tree.
In theory that should be good enough to provide HDMI output on the Draak board, but in practice the lack of LVDS PLL support prevents generation of close-enough dot clock frequencies.
This series is based on renesas-drivers-2018-05-02-v4.17-rc3 and requires Jacopo's "drm: bridge: Add thc63lvd1024 LVDS decoder driver" patch.
As HDMI output isn't functional yet this is difficult to test. Could you add support for the VGA output (using the DU DPAD) in v2 of the patch series ? VGA should work without LVDS PLL support as the clock frequency requirements are not as strict as for HDMI.
Kieran Bingham (1): arm64: dts: renesas: r8a77995: Add LVDS support
Koji Matsuoka (1): drm: rcar-du: Add r8a77995 device support
Ulrich Hecht (3): drm: rcar-du: lvds: Add R8A77995 support arm64: dts: renesas: r8a77995-draak: add HDMI output arm64: dts: renesas: r8a77995-draak: add X12 input dot clock
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 91 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 ++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++ drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++ 4 files changed, 179 insertions(+)
Hi Ulrich,
On Sunday, 20 May 2018 11:27:02 EEST Laurent Pinchart wrote:
On Tuesday, 15 May 2018 15:20:35 EEST Ulrich Hecht wrote:
Hi!
This adds D3 support to the DU and LVDS drivers, not including LVDS PLL support.
It also adds LVDS encoders to the D3 device tree, and LVDS decoder, HDMI encoder and HDMI output connector to the Draak device tree.
In theory that should be good enough to provide HDMI output on the Draak board, but in practice the lack of LVDS PLL support prevents generation of close-enough dot clock frequencies.
This series is based on renesas-drivers-2018-05-02-v4.17-rc3 and requires Jacopo's "drm: bridge: Add thc63lvd1024 LVDS decoder driver" patch.
As HDMI output isn't functional yet this is difficult to test. Could you add support for the VGA output (using the DU DPAD) in v2 of the patch series ? VGA should work without LVDS PLL support as the clock frequency requirements are not as strict as for HDMI.
*sigh* I should really refrain from writing e-mails when I'm jetlagged :-/ VGA is already supported, there's nothing to be done there. Sorry for the noise.
Kieran Bingham (1): arm64: dts: renesas: r8a77995: Add LVDS support
Koji Matsuoka (1): drm: rcar-du: Add r8a77995 device support
Ulrich Hecht (3): drm: rcar-du: lvds: Add R8A77995 support arm64: dts: renesas: r8a77995-draak: add HDMI output arm64: dts: renesas: r8a77995-draak: add X12 input dot clock
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 91 +++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 ++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++ drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++ 4 files changed, 179 insertions(+)
dri-devel@lists.freedesktop.org
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Laurent Pinchart -
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Ulrich Hecht -
Ulrich Hecht