Re-use unpin_work->pending, but also set vblank count before intel_mark_page_flip_active to be sure.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 11 ++++++----- drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++------------------- drivers/gpu/drm/i915/intel_drv.h | 1 - 3 files changed, 18 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9640738aabf2..df8073a2ffbe 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -582,9 +582,14 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) seq_printf(m, "No flip due on pipe %c (plane %c)\n", pipe, plane); } else { + u32 pending; u32 addr;

- if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { + pending = atomic_read(&work->pending); + if (pending == INTEL_FLIP_INACTIVE) { + seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", + pipe, plane); + } else if (pending >= INTEL_FLIP_COMPLETE) { seq_printf(m, "Flip queued on pipe %c (plane %c)\n", pipe, plane); } else { @@ -606,10 +611,6 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) work->flip_queued_vblank, work->flip_ready_vblank, drm_crtc_vblank_count(&crtc->base)); - if (work->enable_stall_check) - seq_puts(m, "Stall check enabled, "); - else - seq_puts(m, "Stall check waiting for page flip ioctl, "); seq_printf(m, "%d prepares\n", atomic_read(&work->pending));

if (INTEL_INFO(dev)->gen >= 4) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f2be54a48727..618e034a7a5e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11415,8 +11415,6 @@ static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) if (work == NULL) return;

- intel_mark_page_flip_active(work); - intel_pipe_update_start(crtc);

if (INTEL_INFO(mmio_flip->i915)->gen >= 9) @@ -11426,6 +11424,8 @@ static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) ilk_do_mmio_flip(crtc, work);

intel_pipe_update_end(crtc); + + intel_mark_page_flip_active(work); }

static void intel_mmio_flip_work_func(struct work_struct *work) @@ -11492,15 +11492,11 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_unpin_work *work = intel_crtc->unpin_work; u32 addr; + u32 pending;

- if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) - return true; - - if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) - return false; - - if (!work->enable_stall_check) - return false; + pending = atomic_read(&work->pending); + if (pending != INTEL_FLIP_PENDING) + return pending == INTEL_FLIP_COMPLETE;

if (work->flip_ready_vblank == 0) { if (work->flip_queued_req && @@ -11676,6 +11672,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, */ if (!mmio_flip) { ret = i915_gem_object_sync(obj, engine, &request); + if (!ret && !request) { + request = i915_gem_request_alloc(engine, NULL); + ret = PTR_ERR_OR_ZERO(request); + } + if (ret) goto cleanup_pending; } @@ -11687,6 +11688,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj, 0); work->gtt_offset += intel_crtc->dspaddr_offset; + work->flip_queued_vblank = drm_crtc_vblank_count(crtc);

if (mmio_flip) { ret = intel_queue_mmio_flip(dev, crtc, obj); @@ -11696,14 +11698,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_gem_request_assign(&work->flip_queued_req, obj->last_write_req); } else { - if (!request) { - request = i915_gem_request_alloc(engine, NULL); - if (IS_ERR(request)) { - ret = PTR_ERR(request); - goto cleanup_unpin; - } - } - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, page_flip_flags); if (ret) @@ -11716,7 +11710,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_add_request_no_flush(request);

work->flip_queued_vblank = drm_crtc_vblank_count(crtc); - work->enable_stall_check = true;

i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, to_intel_plane(primary)->frontbuffer_bit); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e0fcfa1683cc..ce2a6d985bbe 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -952,7 +952,6 @@ struct intel_unpin_work { struct drm_i915_gem_request *flip_queued_req; u32 flip_queued_vblank; u32 flip_ready_vblank; - bool enable_stall_check; };

struct intel_load_detect_pipe {

Do it in 1 step instead, use atomic_read since INTEL_FLIP_COMPLETE is no longer useful.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 3 -- drivers/gpu/drm/i915/i915_irq.c | 18 ++----- drivers/gpu/drm/i915/intel_display.c | 96 ++++++++++++++---------------------- drivers/gpu/drm/i915/intel_drv.h | 2 - 4 files changed, 40 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index df8073a2ffbe..c3b029e7bffd 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -589,9 +589,6 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) if (pending == INTEL_FLIP_INACTIVE) { seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", pipe, plane); - } else if (pending >= INTEL_FLIP_COMPLETE) { - seq_printf(m, "Flip queued on pipe %c (plane %c)\n", - pipe, plane); } else { seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", pipe, plane); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 679f08c944ef..5ed2f73a7ea9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1707,10 +1707,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) intel_pipe_handle_vblank(dev, pipe)) intel_check_page_flip(dev, pipe);

- if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { - intel_prepare_page_flip(dev, pipe); + if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) intel_finish_page_flip(dev, pipe); - }

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev, pipe); @@ -2109,10 +2107,8 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) i9xx_pipe_crc_irq_handler(dev, pipe);

/* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { - intel_prepare_page_flip(dev, pipe); + if (de_iir & DE_PLANE_FLIP_DONE(pipe)) intel_finish_page_flip_plane(dev, pipe); - } }

/* check event from PCH */ @@ -2156,10 +2152,8 @@ static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) intel_check_page_flip(dev, pipe);

/* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { - intel_prepare_page_flip(dev, pipe); + if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) intel_finish_page_flip_plane(dev, pipe); - } }

/* check event from PCH */ @@ -2363,10 +2357,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) else flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;

- if (flip_done) { - intel_prepare_page_flip(dev, pipe); + if (flip_done) intel_finish_page_flip_plane(dev, pipe); - }

if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev, pipe); @@ -4024,7 +4016,6 @@ static bool i8xx_handle_vblank(struct drm_device *dev, if (I915_READ16(ISR) & flip_pending) goto check_page_flip;

- intel_prepare_page_flip(dev, plane); intel_finish_page_flip(dev, pipe); return true;

@@ -4215,7 +4206,6 @@ static bool i915_handle_vblank(struct drm_device *dev, if (I915_READ(ISR) & flip_pending) goto check_page_flip;

- intel_prepare_page_flip(dev, plane); intel_finish_page_flip(dev, pipe); return true;

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 618e034a7a5e..dc42335409b3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3101,7 +3101,6 @@ static void intel_complete_page_flips(struct drm_device *dev) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum plane plane = intel_crtc->plane;

- intel_prepare_page_flip(dev, plane); intel_finish_page_flip_plane(dev, plane); } } @@ -10925,53 +10924,6 @@ static void intel_unpin_work_fn(struct work_struct *__work) kfree(work); }

-static void do_intel_finish_page_flip(struct drm_device *dev, - struct drm_crtc *crtc) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_unpin_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (intel_crtc == NULL) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = intel_crtc->unpin_work; - - /* Ensure we don't miss a work->pending update ... */ - smp_rmb(); - - if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { - spin_unlock_irqrestore(&dev->event_lock, flags); - return; - } - - page_flip_completed(intel_crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -void intel_finish_page_flip(struct drm_device *dev, int pipe) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; - - do_intel_finish_page_flip(dev, crtc); -} - -void intel_finish_page_flip_plane(struct drm_device *dev, int plane) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; - - do_intel_finish_page_flip(dev, crtc); -} - /* Is 'a' after or equal to 'b'? */ static bool g4x_flip_count_after_eq(u32 a, u32 b) { @@ -11024,28 +10976,52 @@ static bool page_flip_finished(struct intel_crtc *crtc) crtc->unpin_work->flip_count); }

-void intel_prepare_page_flip(struct drm_device *dev, int plane) +static void do_intel_finish_page_flip(struct drm_device *dev, + struct drm_crtc *crtc) { - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = - to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_unpin_work *work; unsigned long flags;

+ /* Ignore early vblank irqs */ + if (intel_crtc == NULL) + return;

/* * This is called both by irq handlers and the reset code (to complete * lost pageflips) so needs the full irqsave spinlocks. - * - * NB: An MMIO update of the plane base pointer will also - * generate a page-flip completion irq, i.e. every modeset - * is also accompanied by a spurious intel_prepare_page_flip(). */ spin_lock_irqsave(&dev->event_lock, flags); - if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) - atomic_inc_not_zero(&intel_crtc->unpin_work->pending); + work = intel_crtc->unpin_work; + + if (work == NULL || + atomic_read(&work->pending) == INTEL_FLIP_INACTIVE || + !page_flip_finished(intel_crtc)) { + spin_unlock_irqrestore(&dev->event_lock, flags); + return; + } + + page_flip_completed(intel_crtc); + spin_unlock_irqrestore(&dev->event_lock, flags); }

+void intel_finish_page_flip(struct drm_device *dev, int pipe) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; + + do_intel_finish_page_flip(dev, crtc); +} + +void intel_finish_page_flip_plane(struct drm_device *dev, int plane) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; + + do_intel_finish_page_flip(dev, crtc); +} + static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) { /* Ensure that the work item is consistent when activating it ... */ @@ -11495,8 +11471,8 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, u32 pending;

pending = atomic_read(&work->pending); - if (pending != INTEL_FLIP_PENDING) - return pending == INTEL_FLIP_COMPLETE; + if (pending == INTEL_FLIP_INACTIVE) + return false;

if (work->flip_ready_vblank == 0) { if (work->flip_queued_req && diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ce2a6d985bbe..a74edecfd179 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -946,7 +946,6 @@ struct intel_unpin_work { atomic_t pending; #define INTEL_FLIP_INACTIVE 0 #define INTEL_FLIP_PENDING 1 -#define INTEL_FLIP_COMPLETE 2 u32 flip_count; u32 gtt_offset; struct drm_i915_gem_request *flip_queued_req; @@ -1159,7 +1158,6 @@ struct drm_framebuffer * __intel_framebuffer_create(struct drm_device *dev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_i915_gem_object *obj); -void intel_prepare_page_flip(struct drm_device *dev, int plane); void intel_finish_page_flip(struct drm_device *dev, int pipe); void intel_finish_page_flip_plane(struct drm_device *dev, int plane); void intel_check_page_flip(struct drm_device *dev, int pipe);

Rename intel_unpin_work to intel_flip_work and use it for mmio flips and unpinning. Use flip_queued_req to hold the wait request in the mmio case and allow the vblank interrupt to complete mmio work to have mmio flips run correctly on g4 and earlier.

Changes since v1: - Add smp_mb__after_atomic() to __intel_pageflip_stall_check, to match the smp_mb__before_atomic() in pipe_update_end(). - Check for cur != flip_queued_vblank in pageflip_stall_check.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +- drivers/gpu/drm/i915/intel_display.c | 271 +++++++++++------------------------ drivers/gpu/drm/i915/intel_drv.h | 18 +-- drivers/gpu/drm/i915/intel_sprite.c | 8 +- 4 files changed, 95 insertions(+), 206 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c3b029e7bffd..5662cd5a1a9d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -574,10 +574,10 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) for_each_intel_crtc(dev, crtc) { const char pipe = pipe_name(crtc->pipe); const char plane = plane_name(crtc->plane); - struct intel_unpin_work *work; + struct intel_flip_work *work;

spin_lock_irq(&dev->event_lock); - work = crtc->unpin_work; + work = crtc->flip_work; if (work == NULL) { seq_printf(m, "No flip due on pipe %c (plane %c)\n", pipe, plane); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f1a895153e64..b614f118b973 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -48,6 +48,11 @@ #include <linux/reservation.h> #include <linux/dma-buf.h>

+static bool is_mmio_work(struct intel_flip_work *work) +{ + return work->mmio_work.func; +} + /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, @@ -3285,7 +3290,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) return false;

spin_lock_irq(&dev->event_lock); - pending = to_intel_crtc(crtc)->unpin_work != NULL; + pending = to_intel_crtc(crtc)->flip_work != NULL; spin_unlock_irq(&dev->event_lock);

return pending; @@ -3864,7 +3869,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev) if (atomic_read(&crtc->unpin_work_count) == 0) continue;

- if (crtc->unpin_work) + if (crtc->flip_work) intel_wait_for_vblank(dev, crtc->pipe);

return true; @@ -3876,11 +3881,11 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev) static void page_flip_completed(struct intel_crtc *intel_crtc) { struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct intel_unpin_work *work = intel_crtc->unpin_work; + struct intel_flip_work *work = intel_crtc->flip_work;

- /* ensure that the unpin work is consistent wrt ->pending. */ + /* ensure that the flip work is consistent wrt ->pending. */ smp_rmb(); - intel_crtc->unpin_work = NULL; + intel_crtc->flip_work = NULL;

if (work->event) drm_send_vblank_event(intel_crtc->base.dev, @@ -3890,7 +3895,7 @@ static void page_flip_completed(struct intel_crtc *intel_crtc) drm_crtc_vblank_put(&intel_crtc->base);

wake_up_all(&dev_priv->pending_flip_queue); - queue_work(dev_priv->wq, &work->work); + queue_work(dev_priv->wq, &work->unpin_work);

trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); @@ -3914,9 +3919,11 @@ static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)

if (ret == 0) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_flip_work *work;

spin_lock_irq(&dev->event_lock); - if (intel_crtc->unpin_work) { + work = intel_crtc->flip_work; + if (work && !is_mmio_work(work)) { WARN_ONCE(1, "Removing stuck page flip\n"); page_flip_completed(intel_crtc); } @@ -6308,7 +6315,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) return;

if (to_intel_plane_state(crtc->primary->state)->visible) { - WARN_ON(intel_crtc->unpin_work); + WARN_ON(intel_crtc->flip_work);

intel_pre_disable_primary_noatomic(crtc);

@@ -10881,15 +10888,16 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_device *dev = crtc->dev; - struct intel_unpin_work *work; + struct intel_flip_work *work;

spin_lock_irq(&dev->event_lock); - work = intel_crtc->unpin_work; - intel_crtc->unpin_work = NULL; + work = intel_crtc->flip_work; + intel_crtc->flip_work = NULL; spin_unlock_irq(&dev->event_lock);

if (work) { - cancel_work_sync(&work->work); + cancel_work_sync(&work->mmio_work); + cancel_work_sync(&work->unpin_work); kfree(work); }

@@ -10900,12 +10908,15 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)

static void intel_unpin_work_fn(struct work_struct *__work) { - struct intel_unpin_work *work = - container_of(__work, struct intel_unpin_work, work); + struct intel_flip_work *work = + container_of(__work, struct intel_flip_work, unpin_work); struct intel_crtc *crtc = to_intel_crtc(work->crtc); struct drm_device *dev = crtc->base.dev; struct drm_plane *primary = crtc->base.primary;

+ if (is_mmio_work(work)) + flush_work(&work->mmio_work); + mutex_lock(&dev->struct_mutex); intel_unpin_fb_obj(work->old_fb, primary->state->rotation); drm_gem_object_unreference(&work->pending_flip_obj->base); @@ -10971,16 +10982,16 @@ static bool page_flip_finished(struct intel_crtc *crtc) * anyway, we don't really care. */ return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == - crtc->unpin_work->gtt_offset && + crtc->flip_work->gtt_offset && g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), - crtc->unpin_work->flip_count); + crtc->flip_work->flip_count); }

static void do_intel_finish_page_flip(struct drm_device *dev, struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_unpin_work *work; + struct intel_flip_work *work; unsigned long flags;

/* Ignore early vblank irqs */ @@ -10992,11 +11003,11 @@ static void do_intel_finish_page_flip(struct drm_device *dev, * lost pageflips) so needs the full irqsave spinlocks. */ spin_lock_irqsave(&dev->event_lock, flags); - work = intel_crtc->unpin_work; + work = intel_crtc->flip_work;

if (work == NULL || atomic_read(&work->pending) == INTEL_FLIP_INACTIVE || - !page_flip_finished(intel_crtc)) { + !page_flip_finished(intel_crtc)) { spin_unlock_irqrestore(&dev->event_lock, flags); return; } @@ -11022,7 +11033,7 @@ void intel_finish_page_flip_plane(struct drm_device *dev, int plane) do_intel_finish_page_flip(dev, crtc); }

-static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) +static inline void intel_mark_page_flip_active(struct intel_flip_work *work) { /* Ensure that the work item is consistent when activating it ... */ smp_wmb(); @@ -11059,10 +11070,9 @@ static int intel_gen2_queue_flip(struct drm_device *dev, intel_ring_emit(engine, MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); + intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); intel_ring_emit(engine, 0); /* aux display base address, unused */

- intel_mark_page_flip_active(intel_crtc->unpin_work); return 0; }

@@ -11091,10 +11101,9 @@ static int intel_gen3_queue_flip(struct drm_device *dev, intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); + intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); intel_ring_emit(engine, MI_NOOP);

- intel_mark_page_flip_active(intel_crtc->unpin_work); return 0; }

@@ -11122,7 +11131,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev, intel_ring_emit(engine, MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | + intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset | obj->tiling_mode);

/* XXX Enabling the panel-fitter across page-flip is so far @@ -11133,7 +11142,6 @@ static int intel_gen4_queue_flip(struct drm_device *dev, pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; intel_ring_emit(engine, pf | pipesrc);

- intel_mark_page_flip_active(intel_crtc->unpin_work); return 0; }

@@ -11157,7 +11165,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev, intel_ring_emit(engine, MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); - intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); + intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);

/* Contrary to the suggestions in the documentation, * "Enable Panel Fitter" does not seem to be required when page @@ -11169,7 +11177,6 @@ static int intel_gen6_queue_flip(struct drm_device *dev, pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; intel_ring_emit(engine, pf | pipesrc);

- intel_mark_page_flip_active(intel_crtc->unpin_work); return 0; }

@@ -11261,10 +11268,9 @@ static int intel_gen7_queue_flip(struct drm_device *dev,

intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); - intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); + intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); intel_ring_emit(engine, (MI_NOOP));

- intel_mark_page_flip_active(intel_crtc->unpin_work); return 0; }

@@ -11282,9 +11288,6 @@ static bool use_mmio_flip(struct intel_engine_cs *engine, if (engine == NULL) return true;

- if (INTEL_INFO(engine->dev)->gen < 5) - return false; - if (i915.use_mmio_flip < 0) return false; else if (i915.use_mmio_flip > 0) @@ -11299,126 +11302,21 @@ static bool use_mmio_flip(struct intel_engine_cs *engine, return engine != i915_gem_request_get_engine(obj->last_write_req); }

-static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, - unsigned int rotation, - struct intel_unpin_work *work) +static void intel_mmio_flip_work_func(struct work_struct *w) { - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - const enum pipe pipe = intel_crtc->pipe; - u32 ctl, stride, tile_height; - - ctl = I915_READ(PLANE_CTL(pipe, 0)); - ctl &= ~PLANE_CTL_TILED_MASK; - switch (fb->modifier[0]) { - case DRM_FORMAT_MOD_NONE: - break; - case I915_FORMAT_MOD_X_TILED: - ctl |= PLANE_CTL_TILED_X; - break; - case I915_FORMAT_MOD_Y_TILED: - ctl |= PLANE_CTL_TILED_Y; - break; - case I915_FORMAT_MOD_Yf_TILED: - ctl |= PLANE_CTL_TILED_YF; - break; - default: - MISSING_CASE(fb->modifier[0]); - } - - /* - * The stride is either expressed as a multiple of 64 bytes chunks for - * linear buffers or in number of tiles for tiled buffers. - */ - if (intel_rotation_90_or_270(rotation)) { - /* stride = Surface height in tiles */ - tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); - stride = DIV_ROUND_UP(fb->height, tile_height); - } else { - stride = fb->pitches[0] / - intel_fb_stride_alignment(dev_priv, fb->modifier[0], - fb->pixel_format); - } - - /* - * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on - * PLANE_SURF updates, the update is then guaranteed to be atomic. - */ - I915_WRITE(PLANE_CTL(pipe, 0), ctl); - I915_WRITE(PLANE_STRIDE(pipe, 0), stride); - - I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); - POSTING_READ(PLANE_SURF(pipe, 0)); -} - -static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, - struct intel_unpin_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; + struct intel_flip_work *work = + container_of(w, struct intel_flip_work, mmio_work); + struct intel_crtc *crtc = to_intel_crtc(work->crtc); + struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_framebuffer *intel_fb = - to_intel_framebuffer(intel_crtc->base.primary->fb); - struct drm_i915_gem_object *obj = intel_fb->obj; - i915_reg_t reg = DSPCNTR(intel_crtc->plane); - u32 dspcntr; - - dspcntr = I915_READ(reg); - - if (obj->tiling_mode != I915_TILING_NONE) - dspcntr |= DISPPLANE_TILED; - else - dspcntr &= ~DISPPLANE_TILED; + struct intel_plane *primary = to_intel_plane(crtc->base.primary); + struct drm_i915_gem_object *obj = intel_fb_obj(primary->base.state->fb);

- I915_WRITE(reg, dspcntr); - - I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); - POSTING_READ(DSPSURF(intel_crtc->plane)); -} - -/* - * XXX: This is the temporary way to update the plane registers until we get - * around to using the usual plane update functions for MMIO flips - */ -static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) -{ - struct intel_crtc *crtc = mmio_flip->crtc; - struct intel_unpin_work *work; - - spin_lock_irq(&crtc->base.dev->event_lock); - work = crtc->unpin_work; - spin_unlock_irq(&crtc->base.dev->event_lock); - if (work == NULL) - return; - - intel_pipe_update_start(crtc); - - if (INTEL_INFO(mmio_flip->i915)->gen >= 9) - skl_do_mmio_flip(crtc, mmio_flip->rotation, work); - else - /* use_mmio_flip() retricts MMIO flips to ilk+ */ - ilk_do_mmio_flip(crtc, work); - - intel_pipe_update_end(crtc); - - intel_mark_page_flip_active(work); -} - -static void intel_mmio_flip_work_func(struct work_struct *work) -{ - struct intel_mmio_flip *mmio_flip = - container_of(work, struct intel_mmio_flip, work); - struct intel_framebuffer *intel_fb = - to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); - struct drm_i915_gem_object *obj = intel_fb->obj; - - if (mmio_flip->req) { - WARN_ON(__i915_wait_request(mmio_flip->req, - mmio_flip->crtc->reset_counter, + if (work->flip_queued_req) + WARN_ON(__i915_wait_request(work->flip_queued_req, + crtc->reset_counter, false, NULL, - &mmio_flip->i915->rps.mmioflips)); - i915_gem_request_unreference__unlocked(mmio_flip->req); - } + &dev_priv->rps.mmioflips));

/* For framebuffer backed by dmabuf, wait for fence */ if (obj->base.dma_buf) @@ -11426,29 +11324,11 @@ static void intel_mmio_flip_work_func(struct work_struct *work) false, false, MAX_SCHEDULE_TIMEOUT) < 0);

- intel_do_mmio_flip(mmio_flip); - kfree(mmio_flip); -} - -static int intel_queue_mmio_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_i915_gem_object *obj) -{ - struct intel_mmio_flip *mmio_flip; - - mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); - if (mmio_flip == NULL) - return -ENOMEM; - - mmio_flip->i915 = to_i915(dev); - mmio_flip->req = i915_gem_request_reference(obj->last_write_req); - mmio_flip->crtc = to_intel_crtc(crtc); - mmio_flip->rotation = crtc->primary->state->rotation; - - INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); - schedule_work(&mmio_flip->work); - - return 0; + intel_pipe_update_start(crtc); + primary->update_plane(&primary->base, + crtc->config, + to_intel_plane_state(primary->base.state)); + intel_pipe_update_end(crtc, work); }

static int intel_default_queue_flip(struct drm_device *dev, @@ -11466,7 +11346,7 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_unpin_work *work = intel_crtc->unpin_work; + struct intel_flip_work *work = intel_crtc->flip_work; u32 addr; u32 pending;

@@ -11474,6 +11354,15 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, if (pending == INTEL_FLIP_INACTIVE) return false;

+ smp_mb__after_atomic(); + + if (is_mmio_work(work)) { + u32 cur = intel_crtc_get_vblank_counter(intel_crtc); + + /* MMIO work completes when vblank is different from flip_queued_vblank. */ + return cur != work->flip_queued_vblank; + } + if (work->flip_ready_vblank == 0) { if (work->flip_queued_req && !i915_gem_request_completed(work->flip_queued_req, true)) @@ -11504,7 +11393,7 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_unpin_work *work; + struct intel_flip_work *work;

WARN_ON(!in_interrupt());

@@ -11512,14 +11401,15 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) return;

spin_lock(&dev->event_lock); - work = intel_crtc->unpin_work; + work = intel_crtc->flip_work; if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { - WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", + WARN_ONCE(!is_mmio_work(work), + "Kicking stuck page flip: queued at %d, now %d\n", work->flip_queued_vblank, drm_vblank_count(dev, pipe)); page_flip_completed(intel_crtc); work = NULL; } - if (work != NULL && + if (work != NULL && !is_mmio_work(work) && drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) intel_queue_rps_boost_for_request(dev, work->flip_queued_req); spin_unlock(&dev->event_lock); @@ -11537,7 +11427,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_plane *primary = crtc->primary; enum pipe pipe = intel_crtc->pipe; - struct intel_unpin_work *work; + struct intel_flip_work *work; struct intel_engine_cs *engine; bool mmio_flip; struct drm_i915_gem_request *request = NULL; @@ -11574,15 +11464,15 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->event = event; work->crtc = crtc; work->old_fb = old_fb; - INIT_WORK(&work->work, intel_unpin_work_fn); + INIT_WORK(&work->unpin_work, intel_unpin_work_fn);

ret = drm_crtc_vblank_get(crtc); if (ret) goto free_work;

- /* We borrow the event spin lock for protecting unpin_work */ + /* We borrow the event spin lock for protecting flip_work */ spin_lock_irq(&dev->event_lock); - if (intel_crtc->unpin_work) { + if (intel_crtc->flip_work) { /* Before declaring the flip queue wedged, check if * the hardware completed the operation behind our backs. */ @@ -11598,7 +11488,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, return -EBUSY; } } - intel_crtc->unpin_work = work; + intel_crtc->flip_work = work; spin_unlock_irq(&dev->event_lock);

if (atomic_read(&intel_crtc->unpin_work_count) >= 2) @@ -11667,23 +11557,22 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->flip_queued_vblank = drm_crtc_vblank_count(crtc);

if (mmio_flip) { - ret = intel_queue_mmio_flip(dev, crtc, obj); - if (ret) - goto cleanup_unpin; + INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);

i915_gem_request_assign(&work->flip_queued_req, obj->last_write_req); + + schedule_work(&work->mmio_work); } else { + i915_gem_request_assign(&work->flip_queued_req, request); ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, page_flip_flags); if (ret) goto cleanup_unpin;

- i915_gem_request_assign(&work->flip_queued_req, request); - } - - if (request) + intel_mark_page_flip_active(work); i915_add_request_no_flush(request); + }

work->flip_queued_vblank = drm_crtc_vblank_count(crtc);

@@ -11713,7 +11602,7 @@ cleanup: drm_framebuffer_unreference(work->old_fb);

spin_lock_irq(&dev->event_lock); - intel_crtc->unpin_work = NULL; + intel_crtc->flip_work = NULL; spin_unlock_irq(&dev->event_lock);

drm_crtc_vblank_put(crtc); @@ -14018,7 +13907,7 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, { struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

- intel_pipe_update_end(intel_crtc); + intel_pipe_update_end(intel_crtc, NULL); }

/** diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a2712f6f1eb3..d46aff0350a0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -592,14 +592,6 @@ struct vlv_wm_state { bool cxsr; };

-struct intel_mmio_flip { - struct work_struct work; - struct drm_i915_private *i915; - struct drm_i915_gem_request *req; - struct intel_crtc *crtc; - unsigned int rotation; -}; - struct intel_crtc { struct drm_crtc base; enum pipe pipe; @@ -614,7 +606,7 @@ struct intel_crtc { unsigned long enabled_power_domains; bool lowfreq_avail; struct intel_overlay *overlay; - struct intel_unpin_work *unpin_work; + struct intel_flip_work *flip_work;

atomic_t unpin_work_count;

@@ -937,8 +929,10 @@ intel_get_crtc_for_plane(struct drm_device *dev, int plane) return dev_priv->plane_to_crtc_mapping[plane]; }

-struct intel_unpin_work { - struct work_struct work; +struct intel_flip_work { + struct work_struct unpin_work; + struct work_struct mmio_work; + struct drm_crtc *crtc; struct drm_framebuffer *old_fb; struct drm_i915_gem_object *pending_flip_obj; @@ -1618,7 +1612,7 @@ int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); void intel_pipe_update_start(struct intel_crtc *crtc); -void intel_pipe_update_end(struct intel_crtc *crtc); +void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);

/* intel_tv.c */ void intel_tv_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e2de6b0df5a8..8ec7ce549835 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -151,13 +151,19 @@ void intel_pipe_update_start(struct intel_crtc *crtc) * re-enables interrupts and verifies the update was actually completed * before a vblank using the value of @start_vbl_count. */ -void intel_pipe_update_end(struct intel_crtc *crtc) +void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) { enum pipe pipe = crtc->pipe; int scanline_end = intel_get_crtc_scanline(crtc); u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); ktime_t end_vbl_time = ktime_get();

+ if (work) { + work->flip_queued_vblank = end_vbl_count; + smp_mb__before_atomic(); + atomic_set(&work->pending, INTEL_FLIP_PENDING); + } + trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);

local_irq_enable();

Set plane_state->base.fence to the dma_buf exclusive fence, and add a wait to the mmio function. This will make it easier to unify plane updates later on.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++++++++-------- 2 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 7de7721f65bc..2ab45f16fa65 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -102,6 +102,7 @@ intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { WARN_ON(state && to_intel_plane_state(state)->wait_req); + WARN_ON(state && state->fence); drm_atomic_helper_plane_destroy_state(plane, state); }

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3d29bc6910f6..a9cec8ae0bc4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13370,6 +13370,15 @@ static int intel_atomic_prepare_commit(struct drm_device *dev, struct intel_plane_state *intel_plane_state = to_intel_plane_state(plane_state);

+ if (plane_state->fence) { + long lret = fence_wait(plane_state->fence, true); + + if (lret < 0) { + ret = lret; + break; + } + } + if (!intel_plane_state->wait_req) continue;

@@ -13701,6 +13710,33 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .atomic_destroy_state = intel_crtc_destroy_state, };

+static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj) +{ + struct reservation_object *resv; + + + if (!obj->base.dma_buf) + return NULL; + + resv = obj->base.dma_buf->resv; + + /* For framebuffer backed by dmabuf, wait for fence */ + while (1) { + struct fence *fence_excl, *ret = NULL; + + rcu_read_lock(); + + fence_excl = rcu_dereference(resv->fence_excl); + if (fence_excl) + ret = fence_get_rcu(fence_excl); + + rcu_read_unlock(); + + if (ret == fence_excl) + return ret; + } +} + /** * intel_prepare_plane_fb - Prepare fb for usage on plane * @plane: drm plane to prepare for @@ -13752,19 +13788,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, return ret; }

- /* For framebuffer backed by dmabuf, wait for fence */ - if (obj && obj->base.dma_buf) { - long lret; - - lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, - false, true, - MAX_SCHEDULE_TIMEOUT); - if (lret == -ERESTARTSYS) - return lret; - - WARN(lret < 0, "waiting returns %li\n", lret); - } - if (!obj) { ret = 0; } else if (plane->type == DRM_PLANE_TYPE_CURSOR && @@ -13784,6 +13807,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,

i915_gem_request_assign(&plane_state->wait_req, obj->last_write_req); + + plane_state->base.fence = intel_get_excl_fence(obj); }

i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); @@ -13826,6 +13851,9 @@ intel_cleanup_plane_fb(struct drm_plane *plane, i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);

i915_gem_request_assign(&old_intel_state->wait_req, NULL); + + fence_put(old_intel_state->base.fence); + old_intel_state->base.fence = NULL; }

int

With mmio flips now available on all platforms it's time to remove support for cs flips.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 21 +-- drivers/gpu/drm/i915/intel_display.c | 273 +---------------------------------- drivers/gpu/drm/i915/intel_drv.h | 6 +- 3 files changed, 12 insertions(+), 288 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 04ea4129c9f5..ccc390b10258 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -566,7 +566,6 @@ static void i915_dump_pageflip(struct seq_file *m, { const char pipe = pipe_name(crtc->pipe); u32 pending; - u32 addr; int i;

pending = atomic_read(&work->pending); @@ -578,7 +577,6 @@ static void i915_dump_pageflip(struct seq_file *m, pipe, plane_name(crtc->plane)); }

- for (i = 0; i < work->num_planes; i++) { struct intel_plane_state *old_plane_state = work->old_plane_state[i]; struct drm_plane *plane = old_plane_state->base.plane; @@ -602,22 +600,9 @@ static void i915_dump_pageflip(struct seq_file *m, i915_gem_request_completed(req, true)); }

- seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", - work->flip_queued_vblank, - work->flip_ready_vblank, - drm_crtc_vblank_count(&crtc->base)); - seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - - if (INTEL_INFO(dev_priv)->gen >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); - else - addr = I915_READ(DSPADDR(crtc->plane)); - seq_printf(m, "Current scanout address 0x%08x\n", addr); - - if (work->flip_queued_req) { - seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); - seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); - } + seq_printf(m, "Flip queued on frame %d, now %d\n", + pending ? work->flip_queued_vblank : -1, + intel_crtc_get_vblank_counter(crtc)); }

static int i915_gem_pageflip_info(struct seq_file *m, void *data) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2a8392ada270..45fd84ebaccf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -48,11 +48,6 @@ #include <linux/reservation.h> #include <linux/dma-buf.h>

-static bool is_mmio_work(struct intel_flip_work *work) -{ - return !work->flip_queued_req; -} - /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, @@ -3906,21 +3901,7 @@ static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) if (ret < 0) return ret;

- if (ret == 0) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = list_first_entry_or_null(&intel_crtc->flip_work, - struct intel_flip_work, head); - - if (work && !is_mmio_work(work) && - !work_busy(&work->unpin_work)) { - WARN_ONCE(1, "Removing stuck page flip\n"); - page_flip_completed(intel_crtc, work); - } - spin_unlock_irq(&dev->event_lock); - } + WARN(ret == 0, "Stuck page flip\n");

return 0; } @@ -10981,9 +10962,6 @@ static void intel_unpin_work_fn(struct work_struct *__work)

intel_crtc_destroy_state(crtc, &work->old_crtc_state->base);

- if (work->flip_queued_req) - i915_gem_request_unreference__unlocked(work->flip_queued_req); - for (i = 0; i < work->num_planes; i++) { struct intel_plane_state *old_plane_state = work->old_plane_state[i]; @@ -11015,59 +10993,6 @@ static void intel_unpin_work_fn(struct work_struct *__work) kfree(work); }

-/* Is 'a' after or equal to 'b'? */ -static bool g4x_flip_count_after_eq(u32 a, u32 b) -{ - return !((a - b) & 0x80000000); -} - -static bool page_flip_finished(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - - if (i915_reset_in_progress(&dev_priv->gpu_error) || - crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) - return true; - - /* - * The relevant registers doen't exist on pre-ctg. - * As the flip done interrupt doesn't trigger for mmio - * flips on gmch platforms, a flip count check isn't - * really needed there. But since ctg has the registers, - * include it in the check anyway. - */ - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) - return true; - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - - /* - * A DSPSURFLIVE check isn't enough in case the mmio and CS flips - * used the same base address. In that case the mmio flip might - * have completed, but the CS hasn't even executed the flip yet. - * - * A flip count check isn't enough as the CS might have updated - * the base address just after start of vblank, but before we - * managed to process the interrupt. This means we'd complete the - * CS flip too soon. - * - * Combining both checks should get us a good enough result. It may - * still happen that the CS flip has been executed, but has not - * yet actually completed. But in case the base address is the same - * anyway, we don't really care. - */ - return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == - work->gtt_offset && - g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), - work->flip_count); -} - static void do_intel_finish_page_flip(struct drm_device *dev, struct drm_crtc *crtc) { @@ -11090,7 +11015,7 @@ static void do_intel_finish_page_flip(struct drm_device *dev,

if (work == NULL || atomic_read(&work->pending) == INTEL_FLIP_INACTIVE || - !page_flip_finished(intel_crtc, work) || work_busy(&work->unpin_work)) { + work_busy(&work->unpin_work)) { spin_unlock_irqrestore(&dev->event_lock, flags); return; } @@ -11347,153 +11272,6 @@ static int intel_gen7_queue_flip(struct drm_device *dev, return 0; }

-static struct intel_engine_cs * -intel_get_flip_engine(struct drm_device *dev, - struct drm_i915_private *dev_priv, - struct drm_i915_gem_object *obj) -{ - if (IS_VALLEYVIEW(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) - return &dev_priv->engine[BCS]; - - if (dev_priv->info.gen >= 7) { - struct intel_engine_cs *engine; - - engine = i915_gem_request_get_engine(obj->last_write_req); - if (engine && engine->id == RCS) - return engine; - - return &dev_priv->engine[BCS]; - } else - return &dev_priv->engine[RCS]; -} - -static bool -flip_fb_compatible(struct drm_device *dev, - struct drm_framebuffer *fb, - struct drm_framebuffer *old_fb) -{ - struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); - - if (old_fb->pixel_format != fb->pixel_format) - return false; - - if (INTEL_INFO(dev)->gen > 3 && - (fb->offsets[0] != old_fb->offsets[0] || - fb->pitches[0] != old_fb->pitches[0])) - return false; - - /* vlv: DISPLAY_FLIP fails to change tiling */ - if (IS_VALLEYVIEW(dev) && obj->tiling_mode != old_obj->tiling_mode) - return false; - - return true; -} - -static void -intel_display_flip_prepare(struct drm_device *dev, struct drm_crtc *crtc, - struct intel_flip_work *work) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - if (work->flip_prepared) - return; - - work->flip_prepared = true; - - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) - work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(intel_crtc->pipe)) + 1; - work->flip_queued_vblank = drm_crtc_vblank_count(crtc); - - intel_frontbuffer_flip_prepare(dev, work->new_crtc_state->fb_bits); -} - -static void intel_flip_schedule_request(struct intel_flip_work *work, struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_plane_state *new_state = work->new_plane_state[0]; - struct intel_plane_state *old_state = work->old_plane_state[0]; - struct drm_framebuffer *fb, *old_fb; - struct drm_i915_gem_request *request = NULL; - struct intel_engine_cs *engine; - struct drm_i915_gem_object *obj; - struct fence *fence; - int ret; - - if (i915_terminally_wedged(&dev_priv->gpu_error) || - i915_reset_in_progress(&dev_priv->gpu_error) || - i915.enable_execlists || i915.use_mmio_flip > 0 || - !dev_priv->display.queue_flip) - goto mmio; - - /* Not right after modesetting, surface parameters need to be updated */ - if (needs_modeset(crtc->state) || - to_intel_crtc_state(crtc->state)->update_pipe) - goto mmio; - - /* Only allow a mmio flip for a primary plane without a dma-buf fence */ - if (work->num_planes != 1 || - new_state->base.plane != crtc->primary || - new_state->base.fence) - goto mmio; - - fence = work->old_plane_state[0]->base.fence; - if (fence && !fence_is_signaled(fence)) - goto mmio; - - old_fb = old_state->base.fb; - fb = new_state->base.fb; - obj = intel_fb_obj(fb); - - trace_i915_flip_request(to_intel_crtc(crtc)->plane, obj); - - /* Only when updating a already visible fb. */ - if (!new_state->visible || !old_state->visible) - goto mmio; - - if (!flip_fb_compatible(dev, fb, old_fb)) - goto mmio; - - engine = intel_get_flip_engine(dev, dev_priv, obj); - if (i915.use_mmio_flip == 0 && obj->last_write_req && - i915_gem_request_get_engine(obj->last_write_req) != engine) - goto mmio; - - work->gtt_offset = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj, 0); - work->gtt_offset += to_intel_crtc(crtc)->dspaddr_offset; - - ret = i915_gem_object_sync(obj, engine, &request); - if (!ret && !request) { - request = i915_gem_request_alloc(engine, NULL); - ret = PTR_ERR_OR_ZERO(request); - - if (ret) - request = NULL; - } - - intel_display_flip_prepare(dev, crtc, work); - - if (!ret) - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, 0); - - if (!ret) { - i915_gem_request_assign(&work->flip_queued_req, request); - smp_mb__before_atomic(); - atomic_set(&work->pending, INTEL_FLIP_PENDING); - i915_add_request_no_flush(request); - return; - } - if (request) - i915_gem_request_cancel(request); - -mmio: - to_intel_crtc(crtc)->reset_counter = - atomic_read(&dev_priv->gpu_error.reset_counter); - schedule_work(&work->mmio_work); -} - static void intel_mmio_flip_work_func(struct work_struct *w) { struct intel_flip_work *work = @@ -11522,7 +11300,7 @@ static void intel_mmio_flip_work_func(struct work_struct *w) &dev_priv->rps.mmioflips)); }

- intel_display_flip_prepare(dev, crtc, work); + intel_frontbuffer_flip_prepare(dev, crtc_state->fb_bits);

intel_pipe_update_start(intel_crtc); if (!needs_modeset(&crtc_state->base)) { @@ -11551,9 +11329,7 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, struct drm_crtc *crtc, struct intel_flip_work *work) { - struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 addr; u32 pending;

pending = atomic_read(&work->pending); @@ -11563,36 +11339,8 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev,

smp_mb__after_atomic();

- if (is_mmio_work(work)) { - u32 cur = intel_crtc_get_vblank_counter(intel_crtc); - - /* MMIO work completes when vblank is different from flip_queued_vblank. */ - return cur != work->flip_queued_vblank; - } - - if (work->flip_ready_vblank == 0) { - if (work->flip_queued_req && - !i915_gem_request_completed(work->flip_queued_req, true)) - return false; - - work->flip_ready_vblank = drm_crtc_vblank_count(crtc); - } - - if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) - return false; - - /* Potential stall - if we see that the flip has happened, - * assume a missed interrupt. */ - if (INTEL_INFO(dev)->gen >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); - else - addr = I915_READ(DSPADDR(intel_crtc->plane)); - - /* There is a potential issue here with a false positive after a flip - * to the same address. We could address this by checking for a - * non-incrementing frame counter. - */ - return addr == work->gtt_offset; + /* MMIO work completes when vblank is different from flip_queued_vblank. */ + return work->flip_queued_vblank != intel_crtc_get_vblank_counter(intel_crtc); }

void intel_check_page_flip(struct drm_device *dev, int pipe) @@ -11612,15 +11360,8 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) struct intel_flip_work, head);

if (work != NULL && __intel_pageflip_stall_check(dev, crtc, work)) { - WARN_ONCE(!is_mmio_work(work), - "Kicking stuck page flip: queued at %d, now %d\n", - work->flip_queued_vblank, drm_vblank_count(dev, pipe)); page_flip_completed(intel_crtc, work); - work = NULL; } - if (work != NULL && !is_mmio_work(work) && - drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) - intel_queue_rps_boost_for_request(dev, work->flip_queued_req); spin_unlock(&dev->event_lock); }

@@ -11787,7 +11528,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,

intel_fbc_pre_update(intel_crtc);

- intel_flip_schedule_request(work, crtc); + intel_crtc->reset_counter = + atomic_read(&dev_priv->gpu_error.reset_counter); + schedule_work(&work->mmio_work);

mutex_unlock(&dev->struct_mutex);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7ecebf0c22e0..02ea5adfda72 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -939,16 +939,12 @@ struct intel_flip_work { atomic_t pending; #define INTEL_FLIP_INACTIVE 0 #define INTEL_FLIP_PENDING 1 - u32 flip_count; - u32 gtt_offset; - struct drm_i915_gem_request *flip_queued_req; u32 flip_queued_vblank; - u32 flip_ready_vblank;

unsigned put_power_domains; unsigned num_planes;

- bool can_async_unpin, flip_prepared; + bool can_async_unpin; unsigned fb_bits;

struct intel_crtc_state *old_crtc_state, *new_crtc_state;

With the removal of cs support this is no longer reachable. Can be revived if needed.

Signed-off-by: Maarten Lankhorst maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/i915_drv.h | 5 - drivers/gpu/drm/i915/intel_display.c | 259 ----------------------------------- 2 files changed, 264 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7927bd667a6d..3612201af119 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -601,11 +601,6 @@ struct drm_i915_display_funcs { void (*audio_codec_disable)(struct intel_encoder *encoder); void (*fdi_link_train)(struct drm_crtc *crtc); void (*init_clock_gating)(struct drm_device *dev); - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset); void (*hpd_irq_setup)(struct drm_device *dev); /* clock updates for mode set */ /* cursor updates */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45fd84ebaccf..581fe054b240 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11041,237 +11041,6 @@ void intel_finish_page_flip_plane(struct drm_device *dev, int plane) do_intel_finish_page_flip(dev, crtc); }

-static int intel_gen2_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset) -{ - struct intel_engine_cs *engine = req->engine; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask; - int ret; - - ret = intel_ring_begin(req, 6); - if (ret) - return ret; - - /* Can't queue multiple flips, so wait for the previous - * one to finish before executing the next. - */ - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); - intel_ring_emit(engine, MI_NOOP); - intel_ring_emit(engine, MI_DISPLAY_FLIP | - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); - intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, gtt_offset); - intel_ring_emit(engine, 0); /* aux display base address, unused */ - - return 0; -} - -static int intel_gen3_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset) -{ - struct intel_engine_cs *engine = req->engine; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask; - int ret; - - ret = intel_ring_begin(req, 6); - if (ret) - return ret; - - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); - intel_ring_emit(engine, MI_NOOP); - intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); - intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, gtt_offset); - intel_ring_emit(engine, MI_NOOP); - - return 0; -} - -static int intel_gen4_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset) -{ - struct intel_engine_cs *engine = req->engine; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - uint32_t pf, pipesrc; - int ret; - - ret = intel_ring_begin(req, 4); - if (ret) - return ret; - - /* i965+ uses the linear or tiled offsets from the - * Display Registers (which do not change across a page-flip) - * so we need only reprogram the base address. - */ - intel_ring_emit(engine, MI_DISPLAY_FLIP | - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); - intel_ring_emit(engine, fb->pitches[0]); - intel_ring_emit(engine, gtt_offset | obj->tiling_mode); - - /* XXX Enabling the panel-fitter across page-flip is so far - * untested on non-native modes, so ignore it for now. - * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - intel_ring_emit(engine, pf | pipesrc); - - return 0; -} - -static int intel_gen6_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset) -{ - struct intel_engine_cs *engine = req->engine; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - uint32_t pf, pipesrc; - int ret; - - ret = intel_ring_begin(req, 4); - if (ret) - return ret; - - intel_ring_emit(engine, MI_DISPLAY_FLIP | - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); - intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); - intel_ring_emit(engine, gtt_offset); - - /* Contrary to the suggestions in the documentation, - * "Enable Panel Fitter" does not seem to be required when page - * flipping with a non-native mode, and worse causes a normal - * modeset to fail. - * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - intel_ring_emit(engine, pf | pipesrc); - - return 0; -} - -static int intel_gen7_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint64_t gtt_offset) -{ - struct intel_engine_cs *engine = req->engine; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - uint32_t plane_bit = 0; - int len, ret; - - switch (intel_crtc->plane) { - case PLANE_A: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; - break; - case PLANE_B: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; - break; - case PLANE_C: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; - break; - default: - WARN_ONCE(1, "unknown plane in flip command\n"); - return -ENODEV; - } - - len = 4; - if (engine->id == RCS) { - len += 6; - /* - * On Gen 8, SRM is now taking an extra dword to accommodate - * 48bits addresses, and we need a NOOP for the batch size to - * stay even. - */ - if (IS_GEN8(dev)) - len += 2; - } - - /* - * BSpec MI_DISPLAY_FLIP for IVB: - * "The full packet must be contained within the same cache line." - * - * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same - * cacheline, if we ever start emitting more commands before - * the MI_DISPLAY_FLIP we may need to first emit everything else, - * then do the cacheline alignment, and finally emit the - * MI_DISPLAY_FLIP. - */ - ret = intel_ring_cacheline_align(req); - if (ret) - return ret; - - ret = intel_ring_begin(req, len); - if (ret) - return ret; - - /* Unmask the flip-done completion message. Note that the bspec says that - * we should do this for both the BCS and RCS, and that we must not unmask - * more than one flip event at any time (or ensure that one flip message - * can be sent by waiting for flip-done prior to queueing new flips). - * Experimentation says that BCS works despite DERRMR masking all - * flip-done completion events and that unmasking all planes at once - * for the RCS also doesn't appear to drop events. Setting the DERRMR - * to zero does lead to lockups within MI_DISPLAY_FLIP. - */ - if (engine->id == RCS) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit_reg(engine, DERRMR); - intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | - DERRMR_PIPEB_PRI_FLIP_DONE | - DERRMR_PIPEC_PRI_FLIP_DONE)); - if (IS_GEN8(dev)) - intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | - MI_SRM_LRM_GLOBAL_GTT); - else - intel_ring_emit(engine, MI_STORE_REGISTER_MEM | - MI_SRM_LRM_GLOBAL_GTT); - intel_ring_emit_reg(engine, DERRMR); - intel_ring_emit(engine, engine->scratch.gtt_offset + 256); - if (IS_GEN8(dev)) { - intel_ring_emit(engine, 0); - intel_ring_emit(engine, MI_NOOP); - } - } - - intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); - intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); - intel_ring_emit(engine, gtt_offset); - intel_ring_emit(engine, (MI_NOOP)); - - return 0; -} - static void intel_mmio_flip_work_func(struct work_struct *w) { struct intel_flip_work *work = @@ -14882,34 +14651,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = broxton_modeset_calc_cdclk; } - - switch (INTEL_INFO(dev_priv)->gen) { - case 2: - dev_priv->display.queue_flip = intel_gen2_queue_flip; - break; - - case 3: - dev_priv->display.queue_flip = intel_gen3_queue_flip; - break; - - case 4: - case 5: - dev_priv->display.queue_flip = intel_gen4_queue_flip; - break; - - case 6: - dev_priv->display.queue_flip = intel_gen6_queue_flip; - break; - case 7: - case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ - dev_priv->display.queue_flip = intel_gen7_queue_flip; - break; - case 9: - /* Drop through - unsupported since execlist only. */ - default: - /* Default just returns -ENODEV to indicate unsupported */ - break; - } }

/*