When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system.
Signed-off-by: Benjamin Herrenschmidt benh@kernel.crashing.org ---
(resent adding dri-devel to the CC list to hit patchwork)
drivers/gpu/drm/radeon/r600.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7e5c801..25b2dab 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -3300,6 +3300,10 @@ int r600_irq_process(struct radeon_device *rdev) if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE;
+ /* No MSIs, need a dummy read to flush PCI DMAs */ + if (!rdev->msi_enabled) + RREG32(IH_RB_WPTR); + wptr = r600_get_ih_wptr(rdev); rptr = rdev->ih.rptr; DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt benh@kernel.crashing.org wrote:
When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system.
Signed-off-by: Benjamin Herrenschmidt benh@kernel.crashing.org
Reviewed-by: Alex Deucher alexander.deucher@amd.com
(resent adding dri-devel to the CC list to hit patchwork)
drivers/gpu/drm/radeon/r600.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7e5c801..25b2dab 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -3300,6 +3300,10 @@ int r600_irq_process(struct radeon_device *rdev) if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE;
- /* No MSIs, need a dummy read to flush PCI DMAs */
- if (!rdev->msi_enabled)
- RREG32(IH_RB_WPTR);
wptr = r600_get_ih_wptr(rdev); rptr = rdev->ih.rptr; DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
On Wed, Jul 13, 2011 at 10:44 AM, Alex Deucher alexdeucher@gmail.com wrote:
On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt benh@kernel.crashing.org wrote:
When not using MSIs, there is no guarantee that DMA from the device has been fully flushed to point where it's visible to the CPU when taking an interrupt. To get this guarantee, we need to perform an MMIO read from the device, which will flush all outstanding DMAs from bridges between the device and the system.
Signed-off-by: Benjamin Herrenschmidt benh@kernel.crashing.org
Reviewed-by: Alex Deucher alexander.deucher@amd.com
evergreen.c will need a similar fix.
Alex
(resent adding dri-devel to the CC list to hit patchwork)
drivers/gpu/drm/radeon/r600.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 7e5c801..25b2dab 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -3300,6 +3300,10 @@ int r600_irq_process(struct radeon_device *rdev) if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE;
- /* No MSIs, need a dummy read to flush PCI DMAs */
- if (!rdev->msi_enabled)
- RREG32(IH_RB_WPTR);
wptr = r600_get_ih_wptr(rdev); rptr = rdev->ih.rptr; DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
dri-devel@lists.freedesktop.org
-
Alex Deucher -
Benjamin Herrenschmidt