Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 09bde65e1955..2ab42b05e198 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,9 +37,9 @@ properties: description: phandle of the memory controller node

- core-supply: + power-domains: description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle to the SoC "core" power domain.

operating-points-v2: description: @@ -370,7 +370,7 @@ examples:

nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>;

#interconnect-cells = <0>;

All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Add binding for the core power domain.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml new file mode 100644 index 000000000000..f3d8fd2d8371 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Core Power Domain + +maintainers: + - Dmitry Osipenko digetx@gmail.com + - Jon Hunter jonathanh@nvidia.com + - Thierry Reding thierry.reding@gmail.com + +properties: + compatible: + enum: + - nvidia,tegra20-core-domain + - nvidia,tegra30-core-domain + + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + power-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + +required: + - compatible + - operating-points-v2 + - "#power-domain-cells" + - power-supply + +additionalProperties: false + +examples: + - | + core-domain { + compatible = "nvidia,tegra20-core-domain"; + operating-points-v2 = <&opp_table>; + power-supply = <&regulator>; + #power-domain-cells = <0>; + };

Extend OPP API with dev_pm_opp_sync_regulators() function, which syncs voltage state of regulators.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 11 +++++++++++ 2 files changed, 53 insertions(+)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 4268eb359915..500d6c716283 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2499,3 +2499,45 @@ void dev_pm_opp_remove_table(struct device *dev) dev_pm_opp_put_opp_table(opp_table); } EXPORT_SYMBOL_GPL(dev_pm_opp_remove_table); + +/** + * dev_pm_opp_sync_regulators() - Sync state of voltage regulators + * @dev: device for which we do this operation + * + * Sync voltage state of the OPP table regulators. + * + * Return: 0 on success or a negative error value. + */ +int dev_pm_opp_sync_regulators(struct device *dev) +{ + struct opp_table *opp_table; + struct regulator *reg; + int i, ret = 0; + + /* Device may not have OPP table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return 0; + + /* Regulator may not be required for the device */ + if (!opp_table->regulators) + goto put_table; + + /* Nothing to sync if voltage wasn't changed */ + if (!opp_table->enabled) + goto put_table; + + for (i = 0; i < opp_table->regulator_count; i++) { + reg = opp_table->regulators[i]; + ret = regulator_sync_voltage(reg); + if (ret) + break; + } + +put_table: + /* Drop reference taken by _find_opp_table() */ + dev_pm_opp_put_opp_table(opp_table); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_sync_regulators); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 1435c054016a..4c79faa2025e 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -156,6 +156,7 @@ int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cp int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask); void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); +int dev_pm_opp_sync_regulators(struct device *dev); #else static inline struct opp_table *dev_pm_opp_get_opp_table(struct device *dev) { @@ -366,6 +367,11 @@ static inline void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask { }

+static inline int dev_pm_opp_sync_regulators(struct device *dev) +{ + return -ENOTSUPP; +} + #endif /* CONFIG_PM_OPP */

#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) @@ -442,6 +448,11 @@ static inline int dev_pm_opp_of_find_icc_paths(struct device *dev, struct opp_ta { return -ENOTSUPP; } + +static inline int dev_pm_opp_sync_regulators(struct device *dev) +{ + return -ENOTSUPP; +} #endif

#endif /* __LINUX_OPP_H__ */

Add dev_pm_opp_set_voltage() which allows OPP table users to set voltage in accordance to a given OPP. In particular this is needed for driving voltage of a generic power domain which uses OPPs and doesn't have a clock.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 52 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 11 +++++---- 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 500d6c716283..eab37b3a27bb 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2541,3 +2541,55 @@ int dev_pm_opp_sync_regulators(struct device *dev) return ret; } EXPORT_SYMBOL_GPL(dev_pm_opp_sync_regulators); + +/** + * dev_pm_opp_set_voltage() - Change voltage of regulators + * @dev: device for which we do this operation + * @opp: opp based on which the voltages are to be configured + * + * Change voltage of the OPP table regulators. + * + * Return: 0 on success or a negative error value. + */ +int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp *opp) +{ + struct opp_table *opp_table; + struct regulator *reg; + int ret = 0; + + /* Device may not have OPP table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return 0; + + /* Regulator may not be required for the device */ + if (!opp_table->regulators) + goto put_table; + + /* This function only supports single regulator per device */ + if (WARN_ON(opp_table->regulator_count > 1)) { + dev_err(dev, "multiple regulators are not supported\n"); + ret = -EINVAL; + goto put_table; + } + + reg = opp_table->regulators[0]; + ret = _set_opp_voltage(dev, reg, opp->supplies); + + if (!opp_table->enabled) { + ret = regulator_enable(reg); + if (ret < 0) { + dev_warn(dev, "Failed to enable regulator: %d", ret); + goto put_table; + } + + opp_table->enabled = true; + } + +put_table: + /* Drop reference taken by _find_opp_table() */ + dev_pm_opp_put_opp_table(opp_table); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_voltage); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 4c79faa2025e..f311a8b2ca04 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -157,6 +157,7 @@ int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask) void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); int dev_pm_opp_sync_regulators(struct device *dev); +int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp *opp); #else static inline struct opp_table *dev_pm_opp_get_opp_table(struct device *dev) { @@ -372,6 +373,11 @@ static inline int dev_pm_opp_sync_regulators(struct device *dev) return -ENOTSUPP; }

+static inline int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp *opp) +{ + return -ENOTSUPP; +} + #endif /* CONFIG_PM_OPP */

#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) @@ -448,11 +454,6 @@ static inline int dev_pm_opp_of_find_icc_paths(struct device *dev, struct opp_ta { return -ENOTSUPP; } - -static inline int dev_pm_opp_sync_regulators(struct device *dev) -{ - return -ENOTSUPP; -} #endif

#endif /* __LINUX_OPP_H__ */

Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if levels don't start from 0 in OPP table and zero usually means a minimal level.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 49 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 8 +++++++ 2 files changed, 57 insertions(+)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index eab37b3a27bb..0783a4ac819a 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -449,6 +449,55 @@ struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, } EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_exact);

+/** + * dev_pm_opp_find_level_ceil() - search for an rounded up level + * @dev: device for which we do this operation + * @level: level to search for + * + * Return: Searches for rounded up match in the opp table and returns pointer + * to the matching opp if found, else returns ERR_PTR in case of error and + * should be handled using IS_ERR. Error return values can be: + * EINVAL: for bad pointer + * ERANGE: no match found for search + * ENODEV: if device not found in list of registered devices + * + * The callers are required to call dev_pm_opp_put() for the returned OPP after + * use. + */ +struct dev_pm_opp *dev_pm_opp_find_level_ceil(struct device *dev, + unsigned int *level) +{ + struct opp_table *opp_table; + struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int r = PTR_ERR(opp_table); + + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, r); + return ERR_PTR(r); + } + + mutex_lock(&opp_table->lock); + + list_for_each_entry(temp_opp, &opp_table->opp_list, node) { + if (temp_opp->available && temp_opp->level >= *level) { + opp = temp_opp; + *level = opp->level; + + /* Increment the reference count of OPP */ + dev_pm_opp_get(opp); + break; + } + } + + mutex_unlock(&opp_table->lock); + dev_pm_opp_put_opp_table(opp_table); + + return opp; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_ceil); + static noinline struct dev_pm_opp *_find_freq_ceil(struct opp_table *opp_table, unsigned long *freq) { diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index f311a8b2ca04..a17d92d923cc 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -111,6 +111,8 @@ struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, bool available); struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, unsigned int level); +struct dev_pm_opp *dev_pm_opp_find_level_ceil(struct device *dev, + unsigned int *level);

struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq); @@ -228,6 +230,12 @@ static inline struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, return ERR_PTR(-ENOTSUPP); }

+static inline struct dev_pm_opp *dev_pm_opp_find_level_ceil(struct device *dev, + unsigned int *level) +{ + return ERR_PTR(-ENOTSUPP); +} + static inline struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) {

Add resource-managed versions of OPP API functions. This removes a need from drivers to store and manage OPP table pointers.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 173 +++++++++++++++++++++++++++++++++++++++++ drivers/opp/of.c | 25 ++++++ include/linux/pm_opp.h | 51 ++++++++++++ 3 files changed, 249 insertions(+)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 4774701ec82d..d9feb7639598 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2664,3 +2664,176 @@ int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp *opp) return ret; } EXPORT_SYMBOL_GPL(dev_pm_opp_set_voltage); + +/** + * devm_pm_opp_get_opp_table() - Get OPP table of a device + * @dev: device for which we do this operation + * + * This is a resource-managed version of dev_pm_opp_get_opp_table(). + * + * Return: pointer to 'struct opp_table' if found and -ENODEV otherwise. + */ +struct opp_table *devm_pm_opp_get_opp_table(struct device *dev) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_get_opp_table(dev); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_put_opp_table, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_get_opp_table); + +/** + * devm_pm_opp_set_regulators() - Set regulator names for the device + * @dev: Device for which regulator name is being set. + * @names: Array of pointers to the names of the regulator. + * @count: Number of regulators. + * + * This is a resource-managed version of dev_pm_opp_set_regulators(). + * + * Return: pointer to 'struct opp_table' on success and errorno otherwise. + */ +struct opp_table * +devm_pm_opp_set_regulators(struct device *dev, const char * const names[], + unsigned int count) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_set_regulators(dev, names, count); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_put_regulators, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_set_regulators); + +/** + * devm_pm_opp_set_supported_hw() - Set supported platforms + * @dev: Device for which supported-hw has to be set. + * @versions: Array of hierarchy of versions to match. + * @count: Number of elements in the array. + * + * This is a resource-managed version of dev_pm_opp_set_supported_hw(). + * + * Return: pointer to 'struct opp_table' on success and errorno otherwise. + */ +struct opp_table * +devm_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, + unsigned int count) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_set_supported_hw(dev, versions, count); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_put_supported_hw, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_set_supported_hw); + +/** + * devm_pm_opp_set_clkname() - Set clk name for the device + * @dev: Device for which clk name is being set. + * @name: Clk name. + * + * This is a resource-managed version of dev_pm_opp_set_clkname(). + * + * Return: pointer to 'struct opp_table' on success and errorno otherwise. + */ +struct opp_table * +devm_pm_opp_set_clkname(struct device *dev, const char *name) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_set_clkname(dev, name); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_put_clkname, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_set_clkname); + +/** + * devm_pm_opp_register_set_opp_helper() - Register custom set OPP helper + * @dev: Device for which the helper is getting registered. + * @set_opp: Custom set OPP helper. + * + * This is a resource-managed version of dev_pm_opp_register_set_opp_helper(). + * + * Return: pointer to 'struct opp_table' on success and errorno otherwise. + */ +struct opp_table * +devm_pm_opp_register_set_opp_helper(struct device *dev, + int (*set_opp)(struct dev_pm_set_opp_data *data)) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_register_set_opp_helper(dev, set_opp); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_unregister_set_opp_helper, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_register_set_opp_helper); + +/** + * devm_pm_opp_attach_genpd - Attach genpd(s) for the device and save virtual device pointer + * @dev: Consumer device for which the genpd is getting attached. + * @names: Null terminated array of pointers containing names of genpd to attach. + * @virt_devs: Pointer to return the array of virtual devices. + * + * This is a resource-managed version of dev_pm_opp_attach_genpd(). + * + * Return: pointer to 'struct opp_table' on success and errorno otherwise. + */ +struct opp_table * +devm_pm_opp_attach_genpd(struct device *dev, const char **names, + struct device ***virt_devs) +{ + struct opp_table *opp_table; + int err; + + opp_table = dev_pm_opp_attach_genpd(dev, names, virt_devs); + if (IS_ERR(opp_table)) + return opp_table; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_detach_genpd, + opp_table); + if (err) + return ERR_PTR(err); + + return opp_table; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_attach_genpd); diff --git a/drivers/opp/of.c b/drivers/opp/of.c index 03cb387236c4..3b5a4c8bc62f 100644 --- a/drivers/opp/of.c +++ b/drivers/opp/of.c @@ -1350,3 +1350,28 @@ int dev_pm_opp_of_register_em(struct device *dev, struct cpumask *cpus) return ret; } EXPORT_SYMBOL_GPL(dev_pm_opp_of_register_em); + +/** + * devm_pm_opp_of_add_table() - Initialize opp table from device tree + * @dev: device pointer used to lookup OPP table. + * + * This is a resource-managed version of dev_pm_opp_of_add_table(). + * + * Return: 0 on success and errorno otherwise. + */ +int devm_pm_opp_of_add_table(struct device *dev) +{ + int err; + + err = dev_pm_opp_of_add_table(dev); + if (err) + return err; + + err = devm_add_action_or_reset(dev, (void *)dev_pm_opp_remove_table, + dev); + if (err) + return err; + + return 0; +} +EXPORT_SYMBOL_GPL(devm_pm_opp_of_add_table); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 0298b426fba3..0d42fbda0134 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -163,6 +163,12 @@ void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); int dev_pm_opp_sync_regulators(struct device *dev); int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp *opp); +struct opp_table *devm_pm_opp_get_opp_table(struct device *dev); +struct opp_table *devm_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count); +struct opp_table *devm_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, unsigned int count); +struct opp_table *devm_pm_opp_set_clkname(struct device *dev, const char *name); +struct opp_table *devm_pm_opp_register_set_opp_helper(struct device *dev, int (*set_opp)(struct dev_pm_set_opp_data *data)); +struct opp_table *devm_pm_opp_attach_genpd(struct device *dev, const char **names, struct device ***virt_devs); #else static inline struct opp_table *dev_pm_opp_get_opp_table(struct device *dev) { @@ -396,9 +402,49 @@ static inline int dev_pm_opp_set_voltage(struct device *dev, struct dev_pm_opp * return -ENOTSUPP; }

+static inline struct opp_table *devm_pm_opp_get_opp_table(struct device *dev) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct opp_table * +devm_pm_opp_set_regulators(struct device *dev, const char * const names[], + unsigned int count) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct opp_table * +devm_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, + unsigned int count) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct opp_table * +devm_pm_opp_set_clkname(struct device *dev, const char *name) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct opp_table * +devm_pm_opp_register_set_opp_helper(struct device *dev, + int (*set_opp)(struct dev_pm_set_opp_data *data)) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct opp_table * +devm_pm_opp_attach_genpd(struct device *dev, const char **names, + struct device ***virt_devs) +{ + return ERR_PTR(-ENOTSUPP); +} + #endif /* CONFIG_PM_OPP */

#if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) +int devm_pm_opp_of_add_table(struct device *dev); int dev_pm_opp_of_add_table(struct device *dev); int dev_pm_opp_of_add_table_indexed(struct device *dev, int index); void dev_pm_opp_of_remove_table(struct device *dev); @@ -472,6 +518,11 @@ static inline int dev_pm_opp_of_find_icc_paths(struct device *dev, struct opp_ta { return -ENOTSUPP; } + +static inline int devm_pm_opp_of_add_table(struct device *dev) +{ + return -ENOTSUPP; +} #endif

#endif /* __LINUX_OPP_H__ */

Support set_opp() customization without requiring to use regulators. This is needed by drivers which want to use dev_pm_opp_set_rate() for changing rates of a multiple clocks and don't need to touch regulator.

One example is NVIDIA Tegra30/114 SoCs which have two sibling 3D hardware units which should be use to the same clock rate, meanwhile voltage scaling is done using a power domain. In this case OPP table doesn't have a regulator, causing a NULL dereference in _set_opp_custom().

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 3d02fe33630b..625dae7a5ecb 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -828,17 +828,25 @@ static int _set_opp_custom(const struct opp_table *opp_table, struct dev_pm_opp_supply *old_supply, struct dev_pm_opp_supply *new_supply) { - struct dev_pm_set_opp_data *data; + struct dev_pm_set_opp_data *data, tmp_data; + unsigned int regulator_count; int size;

- data = opp_table->set_opp_data; + if (opp_table->set_opp_data) { + data = opp_table->set_opp_data; + regulator_count = opp_table->regulator_count; + } else { + data = &tmp_data; + regulator_count = 0; + } + data->regulators = opp_table->regulators; - data->regulator_count = opp_table->regulator_count; + data->regulator_count = regulator_count; data->clk = opp_table->clk; data->dev = dev;

data->old_opp.rate = old_freq; - size = sizeof(*old_supply) * opp_table->regulator_count; + size = sizeof(*old_supply) * regulator_count; if (!old_supply) memset(data->old_opp.supplies, 0, size); else

The debug message always prints rate=0 instead of a proper value, fix it.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/of.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/opp/of.c b/drivers/opp/of.c index 3b5a4c8bc62f..1f2038a4420b 100644 --- a/drivers/opp/of.c +++ b/drivers/opp/of.c @@ -755,7 +755,6 @@ static struct dev_pm_opp *_opp_add_static_v2(struct opp_table *opp_table, struct device *dev, struct device_node *np) { struct dev_pm_opp *new_opp; - u64 rate = 0; u32 val; int ret; bool rate_not_available = false; @@ -772,7 +771,8 @@ static struct dev_pm_opp *_opp_add_static_v2(struct opp_table *opp_table,

/* Check if the OPP supports hardware's hierarchy of versions or not */ if (!_opp_is_supported(dev, opp_table, np)) { - dev_dbg(dev, "OPP not supported by hardware: %llu\n", rate); + dev_dbg(dev, "OPP not supported by hardware: %lu\n", + new_opp->rate); goto free_opp; }

Fix adding OPP entries in a wrong (opposite) order if OPP rate is unavailable. The OPP comparison is erroneously skipped if OPP rate is missing, thus OPPs are left unsorted.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/opp/core.c | 23 ++++++++++++----------- drivers/opp/opp.h | 2 +- 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 34f7e530d941..5c7f130a8de2 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -1531,9 +1531,10 @@ static bool _opp_supported_by_regulators(struct dev_pm_opp *opp, return true; }

-int _opp_compare_key(struct dev_pm_opp *opp1, struct dev_pm_opp *opp2) +int _opp_compare_key(struct dev_pm_opp *opp1, struct dev_pm_opp *opp2, + bool rate_not_available) { - if (opp1->rate != opp2->rate) + if (!rate_not_available && opp1->rate != opp2->rate) return opp1->rate < opp2->rate ? -1 : 1; if (opp1->bandwidth && opp2->bandwidth && opp1->bandwidth[0].peak != opp2->bandwidth[0].peak) @@ -1545,7 +1546,8 @@ int _opp_compare_key(struct dev_pm_opp *opp1, struct dev_pm_opp *opp2)

static int _opp_is_duplicate(struct device *dev, struct dev_pm_opp *new_opp, struct opp_table *opp_table, - struct list_head **head) + struct list_head **head, + bool rate_not_available) { struct dev_pm_opp *opp; int opp_cmp; @@ -1559,13 +1561,13 @@ static int _opp_is_duplicate(struct device *dev, struct dev_pm_opp *new_opp, * loop. */ list_for_each_entry(opp, &opp_table->opp_list, node) { - opp_cmp = _opp_compare_key(new_opp, opp); + opp_cmp = _opp_compare_key(new_opp, opp, rate_not_available); if (opp_cmp > 0) { *head = &opp->node; continue; }

- if (opp_cmp < 0) + if (opp_cmp < 0 || rate_not_available) return 0;

/* Duplicate OPPs */ @@ -1601,12 +1603,11 @@ int _opp_add(struct device *dev, struct dev_pm_opp *new_opp, mutex_lock(&opp_table->lock); head = &opp_table->opp_list;

- if (likely(!rate_not_available)) { - ret = _opp_is_duplicate(dev, new_opp, opp_table, &head); - if (ret) { - mutex_unlock(&opp_table->lock); - return ret; - } + ret = _opp_is_duplicate(dev, new_opp, opp_table, &head, + rate_not_available); + if (ret) { + mutex_unlock(&opp_table->lock); + return ret; }

list_add(&new_opp->node, head); diff --git a/drivers/opp/opp.h b/drivers/opp/opp.h index 4ced7ffa8158..6f5be6c72f13 100644 --- a/drivers/opp/opp.h +++ b/drivers/opp/opp.h @@ -219,7 +219,7 @@ struct opp_table *_find_opp_table(struct device *dev); struct opp_device *_add_opp_dev(const struct device *dev, struct opp_table *opp_table); struct dev_pm_opp *_opp_allocate(struct opp_table *opp_table); void _opp_free(struct dev_pm_opp *opp); -int _opp_compare_key(struct dev_pm_opp *opp1, struct dev_pm_opp *opp2); +int _opp_compare_key(struct dev_pm_opp *opp1, struct dev_pm_opp *opp2, bool rate_not_available); int _opp_add(struct device *dev, struct dev_pm_opp *new_opp, struct opp_table *opp_table, bool rate_not_available); int _opp_add_v1(struct opp_table *opp_table, struct device *dev, unsigned long freq, long u_volt, bool dynamic); void _dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask, int last_cpu);

Add "performance" column to debug summary which shows performance state of all power domains and theirs devices.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/base/power/domain.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index a3e1bfc233d4..1c60dae8540c 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -2951,7 +2951,15 @@ static void rtpm_status_str(struct seq_file *s, struct device *dev) else WARN_ON(1);

- seq_puts(s, p); + seq_printf(s, "%-25s ", p); +} + +static void perf_status_str(struct seq_file *s, struct device *dev) +{ + struct generic_pm_domain_data *gpd_data; + + gpd_data = to_gpd_data(dev->power.subsys_data->domain_data); + seq_put_decimal_ull(s, "", gpd_data->performance_state); }

static int genpd_summary_one(struct seq_file *s, @@ -2979,7 +2987,7 @@ static int genpd_summary_one(struct seq_file *s, else snprintf(state, sizeof(state), "%s", status_lookup[genpd->status]); - seq_printf(s, "%-30s %-15s ", genpd->name, state); + seq_printf(s, "%-30s %-50s %u", genpd->name, state, genpd->performance_state);

/* * Modifications on the list require holding locks on both @@ -2987,7 +2995,10 @@ static int genpd_summary_one(struct seq_file *s, * Also genpd->name is immutable. */ list_for_each_entry(link, &genpd->parent_links, parent_node) { - seq_printf(s, "%s", link->child->name); + if (list_is_first(&link->parent_node, &genpd->parent_links)) + seq_printf(s, "\n%50s ", link->child->name); + else + seq_printf(s, "%s", link->child->name); if (!list_is_last(&link->parent_node, &genpd->parent_links)) seq_puts(s, ", "); } @@ -3001,6 +3012,7 @@ static int genpd_summary_one(struct seq_file *s,

seq_printf(s, "\n %-50s ", kobj_path); rtpm_status_str(s, pm_data->dev); + perf_status_str(s, pm_data->dev); kfree(kobj_path); }

@@ -3016,9 +3028,9 @@ static int summary_show(struct seq_file *s, void *data) struct generic_pm_domain *genpd; int ret = 0;

- seq_puts(s, "domain status children\n"); + seq_puts(s, "domain status children performance\n"); seq_puts(s, " /device runtime status\n"); - seq_puts(s, "----------------------------------------------------------------------\n"); + seq_puts(s, "----------------------------------------------------------------------------------------------\n");

ret = mutex_lock_interruptible(&gpd_list_lock); if (ret)

The GR3D1 hardware unit needs to pulse hardware reset after removing power clamp, otherwise reset won't be deasserted. Hence give reset a pulse after removing the clamp. This stayed unnoticed previously because power management wasn't supported by the 3D driver until recently and all power gates are usually ungated after bootloader by default.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/pmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fd2ba3c59178..985373ce52b1 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -654,6 +654,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,

usleep_range(10, 20);

+ /* + * Some hardware blocks may need a 0->1->0 reset pulse in order + * to propagate the reset, Tegra30 3D1 is one example. + */ + err = reset_control_reset(pg->reset); + if (err) + goto powergate_off; + if (pg->pmc->soc->needs_mbist_war) err = tegra210_clk_handle_mbist_war(pg->id); if (err)

Switch all clocks of a power domain to a safe rate which is suitable for all possible voltages in order to ensure that hardware constraints aren't violated when power domain state toggles.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 985373ce52b1..8edcd5b319f6 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -237,6 +237,7 @@ struct tegra_powergate { unsigned int id; struct clk **clks; unsigned int num_clks; + unsigned long *clk_rates; struct reset_control *reset; };

@@ -586,6 +587,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, return 0; }

+static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) +{ + unsigned long safe_rate = 100 * 1000 * 1000; + unsigned int i; + int err; + + for (i = 0; i < pg->num_clks; i++) { + pg->clk_rates[i] = clk_get_rate(pg->clks[i]); + + if (!pg->clk_rates[i]) { + err = -EINVAL; + goto out; + } + + if (pg->clk_rates[i] <= safe_rate) + continue; + + /* + * We don't know whether voltage state is okay for the + * current clock rate, hence it's better to temporally + * switch clock to a safe rate which is suitable for + * all voltages, before enabling the clock. + */ + err = clk_set_rate(pg->clks[i], safe_rate); + if (err) + goto out; + } + + return 0; + +out: + while (i--) + clk_set_rate(pg->clks[i], pg->clk_rates[i]); + + return err; +} + +static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) +{ + unsigned int i; + int err; + + for (i = 0; i < pg->num_clks; i++) { + err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); + if (err) + return err; + } + + return 0; +} + static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) { unsigned int i; @@ -636,10 +688,14 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg,

usleep_range(10, 20);

- err = tegra_powergate_enable_clocks(pg); + err = tegra_powergate_prepare_clocks(pg); if (err) goto powergate_off;

+ err = tegra_powergate_enable_clocks(pg); + if (err) + goto unprepare_clks; + usleep_range(10, 20);

err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); @@ -670,12 +726,19 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, if (disable_clocks) tegra_powergate_disable_clocks(pg);

+ err = tegra_powergate_unprepare_clocks(pg); + if (err) + return err; + return 0;

disable_clks: tegra_powergate_disable_clocks(pg); usleep_range(10, 20);

+unprepare_clks: + tegra_powergate_unprepare_clocks(pg); + powergate_off: tegra_powergate_set(pg->pmc, pg->id, false);

@@ -686,10 +749,14 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) { int err;

- err = tegra_powergate_enable_clocks(pg); + err = tegra_powergate_prepare_clocks(pg); if (err) return err;

+ err = tegra_powergate_enable_clocks(pg); + if (err) + goto unprepare_clks; + usleep_range(10, 20);

err = reset_control_assert(pg->reset); @@ -706,6 +773,10 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) if (err) goto assert_resets;

+ err = tegra_powergate_unprepare_clocks(pg); + if (err) + return err; + return 0;

assert_resets: @@ -717,6 +788,9 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) disable_clks: tegra_powergate_disable_clocks(pg);

+unprepare_clks: + tegra_powergate_unprepare_clocks(pg); + return err; }

@@ -834,6 +908,12 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, if (!pg) return -ENOMEM;

+ pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); + if (!pg->clk_rates) { + kfree(pg->clks); + return -ENOMEM; + } + pg->id = id; pg->clks = &clk; pg->num_clks = 1; @@ -845,6 +925,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, err);

+ kfree(pg->clk_rates); kfree(pg);

return err; @@ -995,6 +1076,12 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, if (!pg->clks) return -ENOMEM;

+ pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); + if (!pg->clk_rates) { + kfree(pg->clks); + return -ENOMEM; + } + for (i = 0; i < count; i++) { pg->clks[i] = of_clk_get(np, i); if (IS_ERR(pg->clks[i])) { @@ -1011,6 +1098,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, while (i--) clk_put(pg->clks[i]);

+ kfree(pg->clk_rates); kfree(pg->clks);

return err;

Add common helper which initializes OPP table for Tegra SoC core devices.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/common.c | 137 +++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 35 ++++++++++ 2 files changed, 172 insertions(+)

diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 3dc54f59cafe..1339d46f494d 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -3,9 +3,16 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */

+#define dev_fmt(fmt) "tegra-soc: " fmt + +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/export.h> #include <linux/of.h> +#include <linux/pm_opp.h>

#include <soc/tegra/common.h> +#include <soc/tegra/fuse.h>

static const struct of_device_id tegra_machine_match[] = { { .compatible = "nvidia,tegra20", }, @@ -31,3 +38,133 @@ bool soc_is_tegra(void)

return match != NULL; } + +static int tegra_core_dev_init_opp_state(struct device *dev) +{ + struct dev_pm_opp *opp; + unsigned long rate; + struct clk *clk; + int err; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clk: %pe\n", clk); + return PTR_ERR(clk); + } + + /* + * If voltage regulator presents, then we could select the fastest + * clock rate, but driver doesn't support power management and + * frequency scaling yet, hence the top freq OPP will vote for a + * very high voltage that will produce lot's of heat. Let's select + * OPP for the current/default rate for now. + * + * Clock rate should be pre-initialized (i.e. it's non-zero) either + * by clock driver or by assigned clocks in a device-tree. + */ + rate = clk_get_rate(clk); + if (!rate) { + dev_err(dev, "failed to get clk rate\n"); + return -EINVAL; + } + + /* find suitable OPP for the clock rate and supportable by hardware */ + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + + /* + * dev_pm_opp_set_rate() doesn't search for a floor clock rate and it + * will error out if default clock rate is too high, i.e. unsupported + * by a SoC hardware version. Hence will find floor rate by ourselves. + */ + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dev, &rate); + + err = PTR_ERR_OR_ZERO(opp); + if (err) { + dev_err(dev, "failed to get OPP for %ld Hz: %d\n", + rate, err); + return err; + } + + dev_pm_opp_put(opp); + + /* + * First dummy rate-set initializes voltage vote by setting voltage + * in accordance to the clock rate. We need to do this because some + * drivers currently don't support power management and clock is + * permanently enabled. + */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +/** + * devm_tegra_core_dev_init_opp_table() - initialize OPP table + * @cfg: pointer to the OPP table configuration + * + * This function will initialize OPP table and sync OPP state of a Tegra SoC + * core device. + * + * Return: 0 on success or errorno. + */ +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + struct opp_table *opp_table; + u32 hw_version; + int err; + + opp_table = devm_pm_opp_set_clkname(dev, NULL); + if (IS_ERR(opp_table)) { + dev_err(dev, "failed to set OPP clk %pe\n", opp_table); + return PTR_ERR(opp_table); + } + + /* Tegra114+ don't support OPP yet */ + if (!of_machine_is_compatible("nvidia,tegra20") && + !of_machine_is_compatible("nvidia,tegra30")) + return -ENODEV; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + opp_table = devm_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (IS_ERR(opp_table)) { + dev_err(dev, "failed to set OPP supported HW: %pe\n", opp_table); + return PTR_ERR(opp_table); + } + + /* + * Older device-trees have an empty OPP table, hence we will get + * -ENODEV from devm_pm_opp_of_add_table() for the older DTBs. + * + * The OPP table presence also varies per-device and depending + * on a SoC generation, hence -ENODEV is expected to happen for + * the newer DTs as well. + */ + err = devm_pm_opp_of_add_table(dev); + if (err) { + if (err == -ENODEV) + dev_err_once(dev, "OPP table not found, please update device-tree\n"); + else + dev_err(dev, "failed to add OPP table: %d\n", err); + + return err; + } + + if (params->init_state) { + err = tegra_core_dev_init_opp_state(dev); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..57b56793a9e5 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,41 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__

+#include <linux/errno.h> +#include <linux/types.h> + +struct clk; +struct device; + +/** + * Tegra SoC core device OPP table configuration + * + * @dev: pointer to the core device + * @clkname: name of clock used for DVFS + * @init_state: pre-initialize OPP state of a device + */ +struct tegra_core_opp_params { + struct device *dev; + const char *clkname; + bool init_state; +}; + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *cfg); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} + +static inline int +devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *cfg) +{ + return -ENODEV; +} +#endif

#endif /* __SOC_TEGRA_COMMON_H__ */

NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a value which satisfies all devices within a power domain. Add driver for the core power domain in order to manage the voltage state of the domain. This allows us to support a system-wide DVFS on Tegra.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/Kconfig | 6 ++ drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/core-power-domain.c | 125 ++++++++++++++++++++++++++ include/soc/tegra/common.h | 6 ++ 4 files changed, 138 insertions(+) create mode 100644 drivers/soc/tegra/core-power-domain.c

diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index bcd61ae59ba3..fccbc168dd87 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -16,6 +16,7 @@ config ARCH_TEGRA_2x_SOC select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select SOC_TEGRA_CORE_POWER_DOMAIN select SOC_TEGRA20_VOLTAGE_COUPLER select TEGRA_TIMER help @@ -31,6 +32,7 @@ config ARCH_TEGRA_3x_SOC select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select SOC_TEGRA_CORE_POWER_DOMAIN select SOC_TEGRA30_VOLTAGE_COUPLER select TEGRA_TIMER help @@ -170,3 +172,7 @@ config SOC_TEGRA20_VOLTAGE_COUPLER config SOC_TEGRA30_VOLTAGE_COUPLER bool "Voltage scaling support for Tegra30 SoCs" depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST + +config SOC_TEGRA_CORE_POWER_DOMAIN + bool + select PM_GENERIC_DOMAINS diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index 9c809c1814bd..8f1294f954b4 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o +obj-$(CONFIG_SOC_TEGRA_CORE_POWER_DOMAIN) += core-power-domain.o diff --git a/drivers/soc/tegra/core-power-domain.c b/drivers/soc/tegra/core-power-domain.c new file mode 100644 index 000000000000..7c0cec8c79fd --- /dev/null +++ b/drivers/soc/tegra/core-power-domain.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NVIDIA Tegra SoC Core Power Domain Driver + */ + +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> +#include <linux/slab.h> + +#include <soc/tegra/common.h> + +static struct lock_class_key tegra_core_domain_lock_class; +static bool tegra_core_domain_state_synced; + +static int tegra_genpd_set_performance_state(struct generic_pm_domain *genpd, + unsigned int level) +{ + struct dev_pm_opp *opp; + int err; + + opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); + if (IS_ERR(opp)) { + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", + level, opp); + return PTR_ERR(opp); + } + + err = dev_pm_opp_set_voltage(&genpd->dev, opp); + dev_pm_opp_put(opp); + + if (err) { + dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", + level, err); + return err; + } + + return 0; +} + +static unsigned int +tegra_genpd_opp_to_performance_state(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + +static int tegra_core_domain_probe(struct platform_device *pdev) +{ + struct generic_pm_domain *genpd; + struct opp_table *opp_table; + const char *rname = "power"; + int err; + + genpd = devm_kzalloc(&pdev->dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = pdev->dev.of_node->name; + genpd->set_performance_state = tegra_genpd_set_performance_state; + genpd->opp_to_performance_state = tegra_genpd_opp_to_performance_state; + + opp_table = devm_pm_opp_set_regulators(&pdev->dev, &rname, 1); + if (IS_ERR(opp_table)) + return dev_err_probe(&pdev->dev, PTR_ERR(opp_table), + "failed to set OPP regulator\n"); + + err = pm_genpd_init(genpd, NULL, false); + if (err) { + dev_err(&pdev->dev, "failed to init genpd: %d\n", err); + return err; + } + + /* + * We have a "PMC -> Core" hierarchy of the power domains where + * PMC needs to resume and change performance (voltage) of the + * Core domain from the PMC GENPD on/off callbacks, hence we need + * to annotate the lock in order to remove confusion from the + * lockdep checker when a nested access happens. + */ + lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class); + + err = of_genpd_add_provider_simple(pdev->dev.of_node, genpd); + if (err) { + dev_err(&pdev->dev, "failed to add genpd: %d\n", err); + goto remove_genpd; + } + + return 0; + +remove_genpd: + pm_genpd_remove(genpd); + + return err; +} + +bool tegra_soc_core_domain_state_synced(void) +{ + return tegra_core_domain_state_synced; +} + +static void tegra_core_domain_sync_state(struct device *dev) +{ + tegra_core_domain_state_synced = true; + + dev_pm_opp_sync_regulators(dev); +} + +static const struct of_device_id tegra_core_domain_match[] = { + { .compatible = "nvidia,tegra20-core-domain", }, + { .compatible = "nvidia,tegra30-core-domain", }, + { } +}; + +static struct platform_driver tegra_core_domain_driver = { + .driver = { + .name = "tegra-core-power", + .of_match_table = tegra_core_domain_match, + .suppress_bind_attrs = true, + .sync_state = tegra_core_domain_sync_state, + }, + .probe = tegra_core_domain_probe, +}; +builtin_platform_driver(tegra_core_domain_driver); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 57b56793a9e5..6c2ccbbbf073 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -27,6 +27,7 @@ struct tegra_core_opp_params {

#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +bool tegra_soc_core_domain_state_synced(void); int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *cfg); #else @@ -35,6 +36,11 @@ static inline bool soc_is_tegra(void) return false; }

+static inline bool tegra_soc_core_domain_state_synced(void) +{ + return false; +} + static inline int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *cfg)

The Core domain is a parent of PMC power domains, hence PMC domains should be set up as a sub-domains of the parent (Core) domain if "power-domains" phandle presents in a device-tree node of PMC domain.

This allows to propagate GENPD performance changes to the parent Core domain if performance change is applied to PMC domain.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/pmc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 4f96dc7745c4..1a659d1c06d7 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1236,6 +1236,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) static int tegra_powergate_init(struct tegra_pmc *pmc, struct device_node *parent) { + struct of_phandle_args child_args, parent_args; struct device_node *np, *child; int err = 0;

@@ -1249,6 +1250,24 @@ static int tegra_powergate_init(struct tegra_pmc *pmc, of_node_put(child); break; } + + if (of_parse_phandle_with_args(child, "power-domains", + "#power-domain-cells", + 0, &parent_args)) + continue; + + child_args.np = child; + child_args.args_count = 0; + + err = of_genpd_add_subdomain(&parent_args, &child_args); + of_node_put(parent_args.np); + if (err) { + if (err == -ENOENT) + err = -EPROBE_DEFER; + + of_node_put(child); + break; + } }

of_node_put(np);

The core voltage shall not drop until state of Core domain is synced, i.e. all device drivers that use Core domain are loaded and ready.

Support Core domain state syncing. The Core domain driver invokes the core-regulator voltage syncing once the state of domain is synced, at this point the Core voltage is allowed to go lower.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..e2c11d442591 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -16,6 +16,8 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h>

+#include <soc/tegra/common.h> + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err;

+ /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV;

@@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV;

- pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);

return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 0e776b20f625..42d675b79fa3 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -16,6 +16,7 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h>

+#include <soc/tegra/common.h> #include <soc/tegra/fuse.h>

struct tegra_regulator_coupler { @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err;

+ /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced()) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV;

@@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV;

- pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);

return tegra->core_min_uV; }

The Clock-and-Reset controller resides in a "core" power domain on NVIDIA Tegra SoCs. In order to support voltage scaling of the core power rail, we need to hook up some clocks (which can't operate properly on a lower voltages above certain clock rates) to the core power domain in order to ensure that a proper core voltage is maintained.

The clocks are registered very early during kernel boot when the driver core isn't available yet. Hence clk-device can't be created very early and we need to split the registration of the clocks in two phases:

1. Register all essential clocks which don't use RPM and may be needed during early boot.

2. Register all clocks that use RPM (and not needed early) at a later boot time, once driver core is available.

That's the reason why this patch reshuffles registration of a few clocks.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-device.c | 222 +++++++++++++++++++++++++++ drivers/clk/tegra/clk-divider.c | 2 +- drivers/clk/tegra/clk-periph-gate.c | 2 +- drivers/clk/tegra/clk-periph.c | 2 +- drivers/clk/tegra/clk-pll.c | 2 +- drivers/clk/tegra/clk-super.c | 4 +- drivers/clk/tegra/clk-tegra-periph.c | 140 ++++++++++++----- drivers/clk/tegra/clk-tegra114.c | 1 + drivers/clk/tegra/clk-tegra124.c | 1 + drivers/clk/tegra/clk-tegra20-emc.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 123 ++++++++------- drivers/clk/tegra/clk-tegra210.c | 1 + drivers/clk/tegra/clk-tegra30.c | 133 ++++++++-------- drivers/clk/tegra/clk.c | 89 +++++++++++ drivers/clk/tegra/clk.h | 7 + 16 files changed, 568 insertions(+), 164 deletions(-) create mode 100644 drivers/clk/tegra/clk-device.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 7b1816856eb5..a0715cdfc1a4 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += clk.o obj-y += clk-audio-sync.o +obj-y += clk-device.o obj-y += clk-dfll.o obj-y += clk-divider.o obj-y += clk-periph.o diff --git a/drivers/clk/tegra/clk-device.c b/drivers/clk/tegra/clk-device.c new file mode 100644 index 000000000000..be4143c4c99a --- /dev/null +++ b/drivers/clk/tegra/clk-device.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/mutex.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> + +#include <soc/tegra/common.h> + +#include "clk.h" + +struct tegra_clk_device { + struct notifier_block clk_nb; + struct device *dev; + struct clk_hw *hw; + struct mutex lock; +}; + +static int tegra_clock_set_pd_state(struct tegra_clk_device *clk_dev, + unsigned long rate) +{ + struct device *dev = clk_dev->dev; + struct dev_pm_opp *opp; + unsigned int pstate; + + opp = dev_pm_opp_find_freq_ceil(dev, &rate); + if (opp == ERR_PTR(-ERANGE)) { + dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate); + opp = dev_pm_opp_find_freq_floor(dev, &rate); + } + + if (IS_ERR(opp)) { + dev_err(dev, "failed to find OPP for %luHz: %pe\n", rate, opp); + return PTR_ERR(opp); + } + + pstate = dev_pm_opp_get_required_pstate(opp, 0); + dev_pm_opp_put(opp); + + return dev_pm_genpd_set_performance_state(dev, pstate); +} + +static int tegra_clock_change_notify(struct notifier_block *nb, + unsigned long msg, void *data) +{ + struct clk_notifier_data *cnd = data; + struct tegra_clk_device *clk_dev; + int err = 0; + + clk_dev = container_of(nb, struct tegra_clk_device, clk_nb); + + mutex_lock(&clk_dev->lock); + switch (msg) { + case PRE_RATE_CHANGE: + if (cnd->new_rate > cnd->old_rate) + err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate); + break; + + case ABORT_RATE_CHANGE: + err = tegra_clock_set_pd_state(clk_dev, cnd->old_rate); + break; + + case POST_RATE_CHANGE: + if (cnd->new_rate < cnd->old_rate) + err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate); + break; + + default: + break; + } + mutex_unlock(&clk_dev->lock); + + return notifier_from_errno(err); +} + +static int tegra_clock_sync_pd_state(struct tegra_clk_device *clk_dev) +{ + unsigned long rate; + int ret; + + mutex_lock(&clk_dev->lock); + if (clk_hw_is_enabled(clk_dev->hw)) { + rate = clk_hw_get_rate(clk_dev->hw); + ret = tegra_clock_set_pd_state(clk_dev, rate); + } + mutex_unlock(&clk_dev->lock); + + return ret; +} + +static int tegra_clock_probe(struct platform_device *pdev) +{ + struct tegra_core_opp_params opp_params = {}; + struct tegra_clk_device *clk_dev; + struct device *dev = &pdev->dev; + struct clk *clk; + int err; + + if (!dev->pm_domain) + return -EINVAL; + + clk_dev = devm_kzalloc(dev, sizeof(*clk_dev), GFP_KERNEL); + if (!clk_dev) + return -ENOMEM; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + clk_dev->dev = dev; + clk_dev->hw = __clk_get_hw(clk); + clk_dev->clk_nb.notifier_call = tegra_clock_change_notify; + mutex_init(&clk_dev->lock); + + platform_set_drvdata(pdev, clk_dev); + + err = clk_notifier_register(clk, &clk_dev->clk_nb); + if (err) { + dev_err(dev, "failed to register clk notifier: %d\n", err); + return err; + } + + err = devm_tegra_core_dev_init_opp_table(dev, &opp_params); + if (err) { + clk_notifier_unregister(clk, &clk_dev->clk_nb); + return err; + } + + /* + * The driver is attaching to a potentially active clock, hence we + * need to sync the power domain state in a accordance to the clock + * state. + */ + err = tegra_clock_sync_pd_state(clk_dev); + if (err) { + clk_notifier_unregister(clk, &clk_dev->clk_nb); + return err; + } + + return 0; +} + +static int __maybe_unused tegra_clock_runtime_suspend(struct device *dev) +{ + return dev_pm_genpd_set_performance_state(dev, 0); +} + +static int __maybe_unused tegra_clock_runtime_resume(struct device *dev) +{ + struct tegra_clk_device *clk_dev = dev_get_drvdata(dev); + unsigned long rate = clk_hw_get_rate(clk_dev->hw); + + return tegra_clock_set_pd_state(clk_dev, rate); +} + +static __maybe_unused int tegra_clock_pm_suspend(struct device *dev) +{ + struct tegra_clk_device *clk_dev = dev_get_drvdata(dev); + + /* + * Power management of the clock is entangled with the Tegra PMC + * GENPD because it uses these clocks for toggling PD on/off state. + * + * The PMC GENPD is resumed in NOIRQ phase, before RPM of the clocks + * becomes available, hence PMC can't use clocks at the early resume + * phase. + * + * In order to solve this problem, we will keep the clock resumed. + * This doesn't matter in regards to a power consumption because all + * SoC devices are power-gated, PLLs are disabled and even core power + * rail is completely turned off in a deepest suspend mode. + */ + + return clk_prepare(clk_dev->hw->clk); +} + +static __maybe_unused int tegra_clock_pm_resume(struct device *dev) +{ + struct tegra_clk_device *clk_dev = dev_get_drvdata(dev); + + clk_unprepare(clk_dev->hw->clk); + + return 0; +} + +static void tegra_clock_shutdown(struct platform_device *pdev) +{ + struct tegra_clk_device *clk_dev = platform_get_drvdata(pdev); + + clk_prepare(clk_dev->hw->clk); +} + +static const struct dev_pm_ops tegra_clock_pm = { + SET_RUNTIME_PM_OPS(tegra_clock_runtime_suspend, + tegra_clock_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(tegra_clock_pm_suspend, + tegra_clock_pm_resume) +}; + +static const struct of_device_id tegra_clock_match[] = { + { .compatible = "nvidia,tegra20-clock", }, + { .compatible = "nvidia,tegra30-clock", }, + { } +}; + +static struct platform_driver tegra_clock_driver = { + .driver = { + .name = "tegra-clock", + .of_match_table = tegra_clock_match, + .pm = &tegra_clock_pm, + .suppress_bind_attrs = true, + }, + .probe = tegra_clock_probe, + .shutdown = tegra_clock_shutdown, +}; +builtin_platform_driver(tegra_clock_driver); diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 38daf483ddf1..b11d47afc798 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -163,7 +163,7 @@ struct clk *tegra_clk_register_divider(const char *name, /* Data in .init is copied by clk_register(), so stack variable OK */ divider->hw.init = &init;

- clk = clk_register(NULL, &divider->hw); + clk = tegra_clk_register(&divider->hw); if (IS_ERR(clk)) kfree(divider);

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 3c4259fec82e..b0bebf597b33 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -176,7 +176,7 @@ struct clk *tegra_clk_register_periph_gate(const char *name, /* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init;

- clk = clk_register(NULL, &gate->hw); + clk = tegra_clk_register(&gate->hw); if (IS_ERR(clk)) kfree(gate);

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 79ca3aa072b7..f7affeba829b 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -195,7 +195,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, periph->gate.regs = bank; periph->gate.enable_refcnt = periph_clk_enb_refcnt;

- clk = clk_register(NULL, &periph->hw); + clk = tegra_clk_register(&periph->hw); if (IS_ERR(clk)) return clk;

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d709ecb7d8d7..eee2e64e251b 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1911,7 +1911,7 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, /* Data in .init is copied by clk_register(), so stack variable OK */ pll->hw.init = &init;

- return clk_register(NULL, &pll->hw); + return tegra_clk_register(&pll->hw); }

struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index 6099c6e9acd4..b2db6cf7d9db 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -226,7 +226,7 @@ struct clk *tegra_clk_register_super_mux(const char *name, /* Data in .init is copied by clk_register(), so stack variable OK */ super->hw.init = &init;

- clk = clk_register(NULL, &super->hw); + clk = tegra_clk_register(&super->hw); if (IS_ERR(clk)) kfree(super);

@@ -266,7 +266,7 @@ struct clk *tegra_clk_register_super_clk(const char *name, /* Data in .init is copied by clk_register(), so stack variable OK */ super->hw.init = &init;

- clk = clk_register(NULL, &super->hw); + clk = tegra_clk_register(&super->hw); if (IS_ERR(clk)) kfree(super);

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 60cc34f90cb9..c401e5f6d504 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -612,13 +612,6 @@ static struct tegra_periph_init_data periph_clks[] = { I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6), - INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), - INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), - INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), - INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), - INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), - INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), - INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), @@ -629,7 +622,6 @@ static struct tegra_periph_init_data periph_clks[] = { INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8), INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9), - INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se_10), INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), @@ -641,10 +633,8 @@ static struct tegra_periph_init_data periph_clks[] = { MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), - MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8), - MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), @@ -652,18 +642,12 @@ static struct tegra_periph_init_data periph_clks[] = { MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8), MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), - MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), - MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), - MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), - MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9), MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9), MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8), - MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), - MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9), MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), @@ -676,20 +660,8 @@ static struct tegra_periph_init_data periph_clks[] = { MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref), MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc), MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow), - MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), - MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), - MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), - MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), - MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), - MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), - MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), - MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), - MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), - MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), - MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8), - MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8), MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), @@ -711,7 +683,6 @@ static struct tegra_periph_init_data periph_clks[] = { MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9), MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), - MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), @@ -727,9 +698,7 @@ static struct tegra_periph_init_data periph_clks[] = { MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8), MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED), - NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL), - NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL), UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), @@ -769,6 +738,40 @@ static struct tegra_periph_init_data periph_clks[] = { MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3), };

+static struct tegra_periph_init_data rpm_periph_clks[] = { + INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), + INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), + INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), + INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), + INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), + INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), + INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), + INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), + MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), + MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), + MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), + MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), + MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), + MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), + MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), + MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), + MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), + MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), + MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), + MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), + MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), + MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), + MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), + MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), + MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), + MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), + MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), + MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), + MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), + NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), + NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), +}; + static struct tegra_periph_init_data gate_clks[] = { GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), @@ -782,18 +785,13 @@ static struct tegra_periph_init_data gate_clks[] = { * from LP1 system suspend and as part of CCPLEX cluster switching. */ GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), - GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0), GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0), GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0), GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0), - GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0), - GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), - GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0), - GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0), GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), @@ -801,12 +799,10 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), - GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL), GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0), GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0), GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), - GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0), GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0), @@ -824,6 +820,15 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0), };

+static struct tegra_periph_init_data rpm_gate_clks[] = { + GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), + GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0), + GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), + GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), + GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0), + GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL), + GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), +}; static struct tegra_periph_init_data div_clks[] = { DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0), }; @@ -888,6 +893,33 @@ static void __init periph_clk_init(void __iomem *clk_base, } }

+static void __init rpm_periph_clk_init(void __iomem *clk_base, + struct tegra_clk *tegra_clks) +{ + int i; + struct clk *clk; + struct clk **dt_clk; + + for (i = 0; i < ARRAY_SIZE(rpm_periph_clks); i++) { + const struct tegra_clk_periph_regs *bank; + struct tegra_periph_init_data *data; + + data = rpm_periph_clks + i; + + dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); + if (!dt_clk) + continue; + + bank = get_reg_bank(data->periph.gate.clk_num); + if (!bank) + continue; + + data->periph.gate.regs = bank; + clk = tegra_clk_register_periph_data(clk_base, data); + *dt_clk = clk; + } +} + static void __init gate_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { @@ -913,6 +945,31 @@ static void __init gate_clk_init(void __iomem *clk_base, } }

+static void __init rpm_gate_clk_init(void __iomem *clk_base, + struct tegra_clk *tegra_clks) +{ + int i; + struct clk *clk; + struct clk **dt_clk; + + for (i = 0; i < ARRAY_SIZE(rpm_gate_clks); i++) { + struct tegra_periph_init_data *data; + + data = rpm_gate_clks + i; + + dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); + if (!dt_clk) + continue; + + clk = tegra_clk_register_periph_gate(data->name, + data->p.parent_name, data->periph.gate.flags, + clk_base, data->flags, + data->periph.gate.clk_num, + periph_clk_enb_refcnt); + *dt_clk = clk; + } +} + static void __init div_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks) { @@ -1032,3 +1089,10 @@ void __init tegra_periph_clk_init(void __iomem *clk_base, gate_clk_init(clk_base, tegra_clks); div_clk_init(clk_base, tegra_clks); } + +void __init tegra_periph_clk_rpm_init(void __iomem *clk_base, + struct tegra_clk *tegra_clks) +{ + rpm_periph_clk_init(clk_base, tegra_clks); + rpm_gate_clk_init(clk_base, tegra_clks); +} diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index bc9e47a4cb60..9d90f1300370 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1069,6 +1069,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,

tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks, &pll_p_params); + tegra_periph_clk_rpm_init(clk_base, tegra114_clks); }

/* Tegra114 CPU clock and reset control functions */ diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 934520aab6e3..0ca82f7e4628 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1081,6 +1081,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, }

tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); + tegra_periph_clk_rpm_init(clk_base, tegra124_clks); }

static void __init tegra124_pll_init(void __iomem *clk_base, diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c index dd74b8543bf1..d2da6412775c 100644 --- a/drivers/clk/tegra/clk-tegra20-emc.c +++ b/drivers/clk/tegra/clk-tegra20-emc.c @@ -270,7 +270,7 @@ struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter) emc->hw.init = &init; emc->want_low_jitter = low_jitter;

- clk = clk_register(NULL, &emc->hw); + clk = tegra_clk_register(&emc->hw); if (IS_ERR(clk)) { kfree(emc); return NULL; diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3efc651b42e3..c29d5af517c3 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -624,11 +624,6 @@ static void tegra20_pll_init(void) { struct clk *clk;

- /* PLLC */ - clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, - &pll_c_params, NULL); - clks[TEGRA20_CLK_PLL_C] = clk; - /* PLLC_OUT1 */ clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, @@ -638,11 +633,6 @@ static void tegra20_pll_init(void) 0, NULL); clks[TEGRA20_CLK_PLL_C_OUT1] = clk;

- /* PLLM */ - clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, - CLK_SET_RATE_GATE, &pll_m_params, NULL); - clks[TEGRA20_CLK_PLL_M] = clk; - /* PLLM_OUT1 */ clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, @@ -685,11 +675,6 @@ static void tegra20_pll_init(void) clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, NULL); clks[TEGRA20_CLK_PLL_A_OUT0] = clk; - - /* PLLE */ - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, - 0, &pll_e_params, NULL); - clks[TEGRA20_CLK_PLL_E] = clk; }

static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", @@ -710,13 +695,6 @@ static void tegra20_super_clk_init(void) NULL); clks[TEGRA20_CLK_CCLK] = clk;

- /* SCLK */ - clk = tegra_clk_register_super_mux("sclk", sclk_parents, - ARRAY_SIZE(sclk_parents), - CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); - clks[TEGRA20_CLK_SCLK] = clk; - /* twd */ clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); clks[TEGRA20_CLK_TWD] = clk; @@ -787,9 +765,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {

static void __init tegra20_periph_clk_init(void) { - struct tegra_periph_init_data *data; struct clk *clk; - unsigned int i;

/* ac97 */ clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", @@ -797,26 +773,10 @@ static void __init tegra20_periph_clk_init(void) clk_base, 0, 3, periph_clk_enb_refcnt); clks[TEGRA20_CLK_AC97] = clk;

- /* emc */ - clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false); - - clks[TEGRA20_CLK_EMC] = clk; - clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, NULL); clks[TEGRA20_CLK_MC] = clk;

- /* dsi */ - clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, - 48, periph_clk_enb_refcnt); - clk_register_clkdev(clk, NULL, "dsi"); - clks[TEGRA20_CLK_DSI] = clk; - - /* pex */ - clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, - periph_clk_enb_refcnt); - clks[TEGRA20_CLK_PEX] = clk; - /* dev1 OSC divider */ clk_register_divider(NULL, "dev1_osc_div", "clk_m", 0, clk_base + MISC_CLK_ENB, 22, 2, @@ -839,21 +799,6 @@ static void __init tegra20_periph_clk_init(void) clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk;

- for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { - data = &tegra_periph_clk_list[i]; - clk = tegra_clk_register_periph_data(clk_base, data); - clks[data->clk_id] = clk; - } - - for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { - data = &tegra_periph_nodiv_clk_list[i]; - clk = tegra_clk_register_periph_nodiv(data->name, - data->p.parent_names, - data->num_parents, &data->periph, - clk_base, data->offset); - clks[data->clk_id] = clk; - } - tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); }

@@ -1111,6 +1056,70 @@ static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, return clk; }

+static void __init tegra20_clock_core_rpm_init(void) +{ + struct tegra_periph_init_data *data; + struct clk *clk; + unsigned int i; + + /* PLLC */ + clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, + &pll_c_params, NULL); + clks[TEGRA20_CLK_PLL_C] = clk; + + /* PLLE */ + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, + 0, &pll_e_params, NULL); + clks[TEGRA20_CLK_PLL_E] = clk; + + /* PLLM */ + clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, + CLK_SET_RATE_GATE, &pll_m_params, NULL); + clks[TEGRA20_CLK_PLL_M] = clk; + + /* SCLK */ + clk = tegra_clk_register_super_mux("sclk", sclk_parents, + ARRAY_SIZE(sclk_parents), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clks[TEGRA20_CLK_SCLK] = clk; + + /* dsi */ + clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, + 48, periph_clk_enb_refcnt); + clk_register_clkdev(clk, NULL, "dsi"); + clks[TEGRA20_CLK_DSI] = clk; + + for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { + data = &tegra_periph_clk_list[i]; + clk = tegra_clk_register_periph_data(clk_base, data); + clks[data->clk_id] = clk; + } + + for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { + data = &tegra_periph_nodiv_clk_list[i]; + clk = tegra_clk_register_periph_nodiv(data->name, + data->p.parent_names, + data->num_parents, &data->periph, + clk_base, data->offset); + clks[data->clk_id] = clk; + } + + /* pex */ + clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, + periph_clk_enb_refcnt); + clks[TEGRA20_CLK_PEX] = clk; + + /* emc */ + clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false); + + clks[TEGRA20_CLK_EMC] = clk; + + tegra_periph_clk_rpm_init(clk_base, tegra20_clks); + tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); + tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); +} + static void __init tegra20_clock_init(struct device_node *np) { struct device_node *node; @@ -1146,12 +1155,10 @@ static void __init tegra20_clock_init(struct device_node *np) tegra20_periph_clk_init(); tegra20_audio_clk_init();

- tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); - tegra_add_of_provider(np, tegra20_clk_src_onecell_get); - tegra_register_devclks(devclks, ARRAY_SIZE(devclks));

tegra_clk_apply_init_table = tegra20_clock_apply_init_table; + tegra_clk_apply_rpm_clocks = tegra20_clock_core_rpm_init;

tegra_cpu_car_ops = &tegra20_cpu_car_ops; } diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 68cbb98af567..c3fb0c98ee44 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3131,6 +3131,7 @@ static __init void tegra210_periph_clk_init(struct device_node *np, }

tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); + tegra_periph_clk_rpm_init(clk_base, tegra210_clks);

/* emc */ clk = tegra210_clk_register_emc(np, clk_base); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 98923c4674bf..3d48fd1e034a 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -812,11 +812,6 @@ static void __init tegra30_pll_init(void) { struct clk *clk;

- /* PLLC */ - clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, - &pll_c_params, NULL); - clks[TEGRA30_CLK_PLL_C] = clk; - /* PLLC_OUT1 */ clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, @@ -826,11 +821,6 @@ static void __init tegra30_pll_init(void) 0, NULL); clks[TEGRA30_CLK_PLL_C_OUT1] = clk;

- /* PLLM */ - clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, - CLK_SET_RATE_GATE, &pll_m_params, NULL); - clks[TEGRA30_CLK_PLL_M] = clk; - /* PLLM_OUT1 */ clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, @@ -880,9 +870,6 @@ static void __init tegra30_pll_init(void) ARRAY_SIZE(pll_e_parents), CLK_SET_RATE_NO_REPARENT, clk_base + PLLE_AUX, 2, 1, 0, NULL); - clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, - CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); - clks[TEGRA30_CLK_PLL_E] = clk; }

static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", @@ -971,14 +958,6 @@ static void __init tegra30_super_clk_init(void) NULL); clks[TEGRA30_CLK_CCLK_LP] = clk;

- /* SCLK */ - clk = tegra_clk_register_super_mux("sclk", sclk_parents, - ARRAY_SIZE(sclk_parents), - CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - clk_base + SCLK_BURST_POLICY, - 0, 4, 0, 0, NULL); - clks[TEGRA30_CLK_SCLK] = clk; - /* twd */ clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", CLK_SET_RATE_PARENT, 1, 2); @@ -1018,29 +997,7 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {

static void __init tegra30_periph_clk_init(void) { - struct tegra_periph_init_data *data; struct clk *clk; - unsigned int i; - - /* dsia */ - clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, - 0, 48, periph_clk_enb_refcnt); - clks[TEGRA30_CLK_DSIA] = clk; - - /* pcie */ - clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, - 70, periph_clk_enb_refcnt); - clks[TEGRA30_CLK_PCIE] = clk; - - /* afi */ - clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, - periph_clk_enb_refcnt); - clks[TEGRA30_CLK_AFI] = clk; - - /* emc */ - clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true); - - clks[TEGRA30_CLK_EMC] = clk;

clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, NULL); @@ -1056,21 +1013,6 @@ static void __init tegra30_periph_clk_init(void) 1, 0, &cml_lock); clks[TEGRA30_CLK_CML1] = clk;

- for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { - data = &tegra_periph_clk_list[i]; - clk = tegra_clk_register_periph_data(clk_base, data); - clks[data->clk_id] = clk; - } - - for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { - data = &tegra_periph_nodiv_clk_list[i]; - clk = tegra_clk_register_periph_nodiv(data->name, - data->p.parent_names, - data->num_parents, &data->periph, - clk_base, data->offset); - clks[data->clk_id] = clk; - } - tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params); }

@@ -1315,6 +1257,77 @@ static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec, return clk; }

+static void __init tegra30_clock_core_rpm_init(void) +{ + struct tegra_periph_init_data *data; + struct clk *clk; + unsigned int i; + + /* PLLC */ + clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, + &pll_c_params, NULL); + clks[TEGRA30_CLK_PLL_C] = clk; + + /* PLLE */ + clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, + CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); + clks[TEGRA30_CLK_PLL_E] = clk; + + /* PLLM */ + clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, + CLK_SET_RATE_GATE, &pll_m_params, NULL); + clks[TEGRA30_CLK_PLL_M] = clk; + + /* SCLK */ + clk = tegra_clk_register_super_mux("sclk", sclk_parents, + ARRAY_SIZE(sclk_parents), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + clk_base + SCLK_BURST_POLICY, + 0, 4, 0, 0, NULL); + clks[TEGRA30_CLK_SCLK] = clk; + + /* dsia */ + clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, + 0, 48, periph_clk_enb_refcnt); + clks[TEGRA30_CLK_DSIA] = clk; + + /* dsib */ + for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { + data = &tegra_periph_nodiv_clk_list[i]; + clk = tegra_clk_register_periph_nodiv(data->name, + data->p.parent_names, + data->num_parents, + &data->periph, + clk_base, data->offset); + clks[data->clk_id] = clk; + } + + for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { + data = &tegra_periph_clk_list[i]; + clk = tegra_clk_register_periph_data(clk_base, data); + clks[data->clk_id] = clk; + } + + /* pcie */ + clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, + 70, periph_clk_enb_refcnt); + clks[TEGRA30_CLK_PCIE] = clk; + + /* afi */ + clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, + periph_clk_enb_refcnt); + clks[TEGRA30_CLK_AFI] = clk; + + /* emc */ + clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true); + + clks[TEGRA30_CLK_EMC] = clk; + + tegra_periph_clk_rpm_init(clk_base, tegra30_clks); + tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); + tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); +} + static void __init tegra30_clock_init(struct device_node *np) { struct device_node *node; @@ -1355,12 +1368,10 @@ static void __init tegra30_clock_init(struct device_node *np) tegra30_audio_plls, ARRAY_SIZE(tegra30_audio_plls), 24000000);

- tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); - tegra_add_of_provider(np, tegra30_clk_src_onecell_get); - tegra_register_devclks(devclks, ARRAY_SIZE(devclks));

tegra_clk_apply_init_table = tegra30_clock_apply_init_table; + tegra_clk_apply_rpm_clocks = tegra30_clock_core_rpm_init;

tegra_cpu_car_ops = &tegra30_cpu_car_ops; } diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index f6cdce441cf7..02f3db424376 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -9,14 +9,19 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/clk/tegra.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include <linux/reset-controller.h> +#include <linux/string.h>

#include <soc/tegra/fuse.h>

#include "clk.h"

/* Global data of Tegra CPU CAR ops */ +static struct device_node *tegra_car_np; static struct tegra_cpu_car_ops dummy_car_ops; struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;

@@ -320,6 +325,8 @@ void __init tegra_add_of_provider(struct device_node *np, { int i;

+ tegra_car_np = np; + for (i = 0; i < clk_num; i++) { if (IS_ERR(clks[i])) { pr_err @@ -372,6 +379,66 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id, return NULL; }

+static struct device_node *tegra_clk_dt_node(struct clk_hw *hw) +{ + struct device_node *np, *root; + + if (!tegra_car_np) + return NULL; + + root = of_get_child_by_name(tegra_car_np, "clocks"); + if (!root) + return NULL; + + for_each_child_of_node(root, np) { + if (strcmp(np->name, hw->init->name)) + continue; + + if (!of_device_is_compatible(np, "nvidia,tegra20-clock") && + !of_device_is_compatible(np, "nvidia,tegra30-clock")) + continue; + + return np; + } + + of_node_put(root); + + return NULL; +} + +struct clk *tegra_clk_register(struct clk_hw *hw) +{ + struct platform_device *pdev; + struct device *dev = NULL; + struct device_node *np; + const char *dev_name; + + np = tegra_clk_dt_node(hw); + + if (!of_device_is_available(np)) + goto reg_clk; + + dev_name = kasprintf(GFP_KERNEL, "tegra_clk_%s", hw->init->name); + if (!dev_name) { + of_node_put(np); + goto reg_clk; + } + + pdev = of_platform_device_create(np, dev_name, NULL); + if (!pdev) { + pr_err("%s: failed to create device for %pOF\n", __func__, np); + kfree(dev_name); + of_node_put(np); + goto reg_clk; + } + + dev = &pdev->dev; + pm_runtime_enable(dev); + +reg_clk: + return clk_register(dev, hw); +} + tegra_clk_apply_init_table_func tegra_clk_apply_init_table;

static int __init tegra_clocks_apply_init_table(void) @@ -384,3 +451,25 @@ static int __init tegra_clocks_apply_init_table(void) return 0; } arch_initcall(tegra_clocks_apply_init_table); + +tegra_clk_apply_rpm_init_table_func tegra_clk_apply_rpm_clocks; + +/* + * Clocks that use runtime PM can't be created at the CLK_OF_DECLARE + * stage because drivers base isn't initialized yet, and thus platform + * devices can't be created for the clocks. Hence we need to split the + * registration of the clocks into two phases. The first phase registers + * essential clocks which don't require RPM and are actually used during + * early boot. The second phase registers clocks which use RPM and this + * is done when drivers base is ready. + */ +static int __init tegra_clocks_apply_core_rpm(void) +{ + if (!tegra_clk_apply_rpm_clocks) + return 0; + + tegra_clk_apply_rpm_clocks(); + + return 0; +} +postcore_initcall_sync(tegra_clocks_apply_core_rpm); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c3e36b5dcc75..d45f36237cc0 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -869,6 +869,9 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params);

+void tegra_periph_clk_rpm_init(void __iomem *clk_base, + struct tegra_clk *tegra_clks); + void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned long *input_freqs, unsigned int num, @@ -907,6 +910,8 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);

typedef void (*tegra_clk_apply_init_table_func)(void); extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; +typedef void (*tegra_clk_apply_rpm_init_table_func)(void); +extern tegra_clk_apply_rpm_init_table_func tegra_clk_apply_rpm_clocks; int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); @@ -931,4 +936,6 @@ struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter); struct clk *tegra210_clk_register_emc(struct device_node *np, void __iomem *regs);

+struct clk *tegra_clk_register(struct clk_hw *hw); + #endif /* TEGRA_CLK_H */

Add suspend/resume and generic power domain support to the Host1x driver. This is required for enabling system-wide DVFS and supporting dynamic power management using a generic power domain.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/host1x/dev.c | 102 ++++++++++++++++++++++++++++++++++----- 1 file changed, 91 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index d0ebb70e2fdd..c1525cffe7b1 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -12,6 +12,7 @@ #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> +#include <linux/pm_runtime.h> #include <linux/slab.h>

#define CREATE_TRACE_POINTS @@ -417,7 +418,7 @@ static int host1x_probe(struct platform_device *pdev) return err; }

- host->rst = devm_reset_control_get(&pdev->dev, "host1x"); + host->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "host1x"); if (IS_ERR(host->rst)) { err = PTR_ERR(host->rst); dev_err(&pdev->dev, "failed to get reset: %d\n", err); @@ -437,16 +438,15 @@ static int host1x_probe(struct platform_device *pdev) goto iommu_exit; }

- err = clk_prepare_enable(host->clk); - if (err < 0) { - dev_err(&pdev->dev, "failed to enable clock\n"); - goto free_channels; - } + pm_runtime_enable(&pdev->dev); + err = pm_runtime_get_sync(&pdev->dev); + if (err < 0) + goto rpm_disable;

err = reset_control_deassert(host->rst); if (err < 0) { dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); - goto unprepare_disable; + goto rpm_disable; }

err = host1x_syncpt_init(host); @@ -485,9 +485,10 @@ static int host1x_probe(struct platform_device *pdev) host1x_syncpt_deinit(host); reset_assert: reset_control_assert(host->rst); -unprepare_disable: - clk_disable_unprepare(host->clk); -free_channels: +rpm_disable: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + host1x_channel_list_free(&host->channel_list); iommu_exit: host1x_iommu_exit(host); @@ -504,16 +505,95 @@ static int host1x_remove(struct platform_device *pdev) host1x_intr_deinit(host); host1x_syncpt_deinit(host); reset_control_assert(host->rst); - clk_disable_unprepare(host->clk); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); host1x_iommu_exit(host);

return 0; }

+static int __maybe_unused host1x_runtime_suspend(struct device *dev) +{ + struct host1x *host = dev_get_drvdata(dev); + + clk_disable_unprepare(host->clk); + reset_control_release(host->rst); + + return 0; +} + +static int __maybe_unused host1x_runtime_resume(struct device *dev) +{ + struct host1x *host = dev_get_drvdata(dev); + int err; + + err = reset_control_acquire(host->rst); + if (err) { + dev_err(dev, "failed to acquire reset: %d\n", err); + return err; + } + + err = clk_prepare_enable(host->clk); + if (err) { + dev_err(dev, "failed to enable clock: %d\n", err); + goto release_reset; + } + + return 0; + +release_reset: + reset_control_release(host->rst); + + return err; +} + +static __maybe_unused int host1x_suspend(struct device *dev) +{ + struct host1x *host = dev_get_drvdata(dev); + int err; + + host1x_syncpt_save(host); + + err = pm_runtime_force_suspend(dev); + if (err < 0) + return err; + + return 0; +} + +static __maybe_unused int host1x_resume(struct device *dev) +{ + struct host1x *host = dev_get_drvdata(dev); + struct host1x_channel *channel; + unsigned int index; + int err; + + err = pm_runtime_force_resume(dev); + if (err < 0) + return err; + + host1x_syncpt_restore(host); + + for_each_set_bit(index, host->channel_list.allocated_channels, + host->info->nb_channels) { + channel = &host->channel_list.channels[index]; + host1x_hw_channel_init(host, channel, channel->id); + } + + return 0; +} + +static const struct dev_pm_ops host1x_pm = { + SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(host1x_suspend, host1x_resume) +}; + static struct platform_driver tegra_host1x_driver = { .driver = { .name = "tegra-host1x", .of_match_table = host1x_of_match, + .pm = &host1x_pm, }, .probe = host1x_probe, .remove = host1x_remove,

Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/tegra/dc.c | 66 +++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b6676f1fe358..105ad786e432 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -11,9 +11,12 @@ #include <linux/interconnect.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h>

+#include <soc/tegra/common.h> #include <soc/tegra/pmc.h>

#include <drm/drm_atomic.h> @@ -1699,6 +1702,48 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, return 0; }

+static void tegra_dc_update_voltage_state(struct tegra_dc *dc, + struct tegra_dc_state *state) +{ + unsigned long rate, pstate; + struct dev_pm_opp *opp; + int err; + + /* calculate actual pixel clock rate which depends on internal divider */ + rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); + + /* find suitable OPP for the rate */ + opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); + + if (opp == ERR_PTR(-ERANGE)) + opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); + + /* -ENOENT means that this device-tree doesn't have OPP table */ + if (opp == ERR_PTR(-ENOENT)) + return; + + if (IS_ERR(opp)) { + dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", + rate, opp); + return; + } + + pstate = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + /* + * The minimum core voltage depends on the pixel clock rate (which + * depends on internal clock divider of the CRTC) and not on the + * rate of the display controller clock. This is why we're not using + * dev_pm_opp_set_rate() API and instead controlling the power domain + * directly. + */ + err = dev_pm_genpd_set_performance_state(dc->dev, pstate); + if (err) + dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", + pstate, err); +} + static void tegra_dc_commit_state(struct tegra_dc *dc, struct tegra_dc_state *state) { @@ -1738,6 +1783,8 @@ static void tegra_dc_commit_state(struct tegra_dc *dc, if (err < 0) dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", dc->clk, state->pclk, err); + + tegra_dc_update_voltage_state(dc, state); }

static void tegra_dc_stop(struct tegra_dc *dc) @@ -1931,6 +1978,8 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, err = host1x_client_suspend(&dc->client); if (err < 0) dev_err(dc->dev, "failed to suspend: %d\n", err); + + dev_pm_genpd_set_performance_state(dc->dev, 0); }

static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, @@ -2523,7 +2572,6 @@ static int tegra_dc_runtime_suspend(struct host1x_client *client)

clk_disable_unprepare(dc->clk); pm_runtime_put_sync(dev); - return 0; }

@@ -2881,6 +2929,18 @@ static int tegra_dc_couple(struct tegra_dc *dc) return 0; }

+static int tegra_dc_init_opp_table(struct tegra_dc *dc) +{ + struct tegra_core_opp_params opp_params = {}; + int err; + + err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); + if (err && err != -ENODEV) + return err; + + return 0; +} + static int tegra_dc_probe(struct platform_device *pdev) { struct tegra_dc *dc; @@ -2939,6 +2999,10 @@ static int tegra_dc_probe(struct platform_device *pdev) tegra_powergate_power_off(dc->powergate); }

+ err = tegra_dc_init_opp_table(dc); + if (err < 0) + return err; + dc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dc->regs)) return PTR_ERR(dc->regs);

Add OPP and PM support to the GR2D driver. This is required for enabling system-wide DVFS and supporting dynamic power management using a generic power domain.

Tested-by: Peter Geis pgwipeout@gmail.com Tested-by: Nicolas Chauvet kwizart@gmail.com Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/tegra/gr2d.c | 73 +++++++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c index f30aa86e4c9f..689554ef81a8 100644 --- a/drivers/gpu/drm/tegra/gr2d.c +++ b/drivers/gpu/drm/tegra/gr2d.c @@ -7,6 +7,9 @@ #include <linux/iommu.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_runtime.h> + +#include <soc/tegra/common.h>

#include "drm.h" #include "gem.h" @@ -185,8 +188,15 @@ static const u32 gr2d_addr_regs[] = { GR2D_VA_BASE_ADDR_SB, };

+static void gr2d_pm_runtime_release(void *dev) +{ + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + static int gr2d_probe(struct platform_device *pdev) { + struct tegra_core_opp_params opp_params = {}; struct device *dev = &pdev->dev; struct host1x_syncpt **syncpts; struct gr2d *gr2d; @@ -197,6 +207,8 @@ static int gr2d_probe(struct platform_device *pdev) if (!gr2d) return -ENOMEM;

+ platform_set_drvdata(pdev, gr2d); + gr2d->soc = of_device_get_match_data(dev);

syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); @@ -209,12 +221,23 @@ static int gr2d_probe(struct platform_device *pdev) return PTR_ERR(gr2d->clk); }

- err = clk_prepare_enable(gr2d->clk); - if (err) { - dev_err(dev, "cannot turn on clock\n"); + opp_params.init_state = true; + + err = devm_tegra_core_dev_init_opp_table(dev, &opp_params); + if (err && err != -ENODEV) + return err; + + pm_runtime_enable(dev); + err = pm_runtime_get_sync(dev); + if (err < 0) { + gr2d_pm_runtime_release(dev); return err; }

+ err = devm_add_action_or_reset(dev, gr2d_pm_runtime_release, dev); + if (err) + return err; + INIT_LIST_HEAD(&gr2d->client.base.list); gr2d->client.base.ops = &gr2d_client_ops; gr2d->client.base.dev = dev; @@ -229,7 +252,6 @@ static int gr2d_probe(struct platform_device *pdev) err = host1x_client_register(&gr2d->client.base); if (err < 0) { dev_err(dev, "failed to register host1x client: %d\n", err); - clk_disable_unprepare(gr2d->clk); return err; }

@@ -237,8 +259,6 @@ static int gr2d_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++) set_bit(gr2d_addr_regs[i], gr2d->addr_regs);

- platform_set_drvdata(pdev, gr2d); - return 0; }

@@ -254,15 +274,56 @@ static int gr2d_remove(struct platform_device *pdev) return err; }

+ return 0; +} + +static int __maybe_unused gr2d_runtime_suspend(struct device *dev) +{ + struct gr2d *gr2d = dev_get_drvdata(dev); + clk_disable_unprepare(gr2d->clk);

return 0; }

+static int __maybe_unused gr2d_runtime_resume(struct device *dev) +{ + struct gr2d *gr2d = dev_get_drvdata(dev); + int err; + + err = clk_prepare_enable(gr2d->clk); + if (err) { + dev_err(dev, "failed to enable clock: %d\n", err); + return err; + } + + return 0; +} + +static __maybe_unused int gr2d_suspend(struct device *dev) +{ + struct gr2d *gr2d = dev_get_drvdata(dev); + int err; + + host1x_channel_stop(gr2d->channel); + + err = pm_runtime_force_suspend(dev); + if (err < 0) + return err; + + return 0; +} + +static const struct dev_pm_ops tegra_gr2d_pm = { + SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(gr2d_suspend, pm_runtime_force_resume) +}; + struct platform_driver tegra_gr2d_driver = { .driver = { .name = "tegra-gr2d", .of_match_table = gr2d_match, + .pm = &tegra_gr2d_pm, }, .probe = gr2d_probe, .remove = gr2d_remove,

Host1x channel should be idling before hardware is turned off, hence stop the channel in the suspend callback.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/gpu/drm/tegra/vic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index ade56b860cf9..92d3d48c4277 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -510,8 +510,23 @@ static int vic_remove(struct platform_device *pdev) return 0; }

+static __maybe_unused int vic_suspend(struct device *dev) +{ + struct vic *vic = dev_get_drvdata(dev); + int err; + + host1x_channel_stop(vic->channel); + + err = pm_runtime_force_suspend(dev); + if (err < 0) + return err; + + return 0; +} + static const struct dev_pm_ops vic_pm_ops = { SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(vic_suspend, pm_runtime_force_resume) };

struct platform_driver tegra_vic_driver = {

Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- drivers/memory/tegra/tegra20-emc.c | 57 +++--------------------------- 1 file changed, 4 insertions(+), 53 deletions(-)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 686aaf477d8a..4be847442fc7 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -908,58 +908,6 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc) return err; }

-static int tegra_emc_opp_table_init(struct tegra_emc *emc) -{ - u32 hw_version = BIT(tegra_sku_info.soc_process_id); - struct opp_table *clk_opp_table, *hw_opp_table; - int err; - - clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); - err = PTR_ERR_OR_ZERO(clk_opp_table); - if (err) { - dev_err(emc->dev, "failed to set OPP clk: %d\n", err); - return err; - } - - hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); - err = PTR_ERR_OR_ZERO(hw_opp_table); - if (err) { - dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); - goto put_clk_table; - } - - err = dev_pm_opp_of_add_table(emc->dev); - if (err) { - if (err == -ENODEV) - dev_err(emc->dev, "OPP table not found, please update your device tree\n"); - else - dev_err(emc->dev, "failed to add OPP table: %d\n", err); - - goto put_hw_table; - } - - dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); - - /* first dummy rate-set initializes voltage state */ - err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); - if (err) { - dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); - goto remove_table; - } - - return 0; - -remove_table: - dev_pm_opp_of_remove_table(emc->dev); -put_hw_table: - dev_pm_opp_put_supported_hw(hw_opp_table); -put_clk_table: - dev_pm_opp_put_clkname(clk_opp_table); - - return err; -} - static void devm_tegra_emc_unset_callback(void *data) { tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1086,6 +1034,7 @@ static int tegra_emc_devfreq_init(struct tegra_emc *emc)

static int tegra_emc_probe(struct platform_device *pdev) { + struct tegra_core_opp_params opp_params = {}; struct device_node *np; struct tegra_emc *emc; int irq, err; @@ -1131,7 +1080,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err;

- err = tegra_emc_opp_table_init(emc); + opp_params.init_state = true; + + err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); if (err) return err;

Add OPP tables and power domains to the Tegra20 device-tree.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- .../boot/dts/tegra20-acer-a500-picasso.dts | 4 + arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +- arch/arm/boot/dts/tegra20-harmony.dts | 6 +- arch/arm/boot/dts/tegra20-paz00.dts | 46 +- .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 ++++++++++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 6 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 6 +- arch/arm/boot/dts/tegra20-trimslice.dts | 12 + arch/arm/boot/dts/tegra20-ventana.dts | 6 +- arch/arm/boot/dts/tegra20.dtsi | 220 ++++ 10 files changed, 1241 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 40c1bab22155..78b307370a46 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -834,6 +834,10 @@ rtc_32k_wifi: clock@1 { clock-output-names = "kk3270032"; };

+ core-domain { + power-supply = <&vdd_core>; + }; + cpus { cpu0: cpu@0 { cpu-supply = <&vdd_cpu>; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 585a5b441cf6..5ad803fea48f 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -495,7 +495,7 @@ reg_3v3_vsys: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -701,6 +701,10 @@ usb-phy@c5004000 { vbus-supply = <&reg_lan_v_bus>; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: xtal3 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 86494cb4d5a1..762e12b73e7e 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -339,7 +339,7 @@ sys_reg: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -640,6 +640,10 @@ backlight: backlight { default-brightness-level = <6>; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 7e49112cd9a1..d30169722282 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -26,7 +26,19 @@ memory@0 { };

host1x@50000000 { + core-supply = <&core_vdd_reg>; + + gr2d@54140000 { + core-supply = <&core_vdd_reg>; + }; + + gr3d@54180000 { + core-supply = <&core_vdd_reg>; + }; + dc@54200000 { + core-supply = <&core_vdd_reg>; + rgb { status = "okay";

@@ -34,11 +46,16 @@ rgb { }; };

+ dc@54240000 { + core-supply = <&core_vdd_reg>; + }; + hdmi@54280000 { status = "okay";

vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; + core-supply = <&core_vdd_reg>;

nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) @@ -46,6 +63,10 @@ hdmi@54280000 { }; };

+ vde@6001a000 { + core-supply = <&core_vdd_reg>; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -314,6 +335,8 @@ nvec@7000c500 { memory-controller@7000f400 { nvidia,use-ram-code;

+ core-supply = <&core_vdd_reg>; + emc-tables@0 { nvidia,ram-code = <0x0>; #address-cells = <1>; @@ -387,10 +410,10 @@ sys_reg: sys {

core_vdd_reg: sm0 { regulator-name = "+1.2vs_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 450000>; + regulator-coupled-max-spread = <170000 550000>; regulator-always-on;

nvidia,tegra-core-regulator; @@ -401,7 +424,7 @@ cpu_vdd_reg: sm1 { regulator-min-microvolt = <750000>; regulator-max-microvolt = <1100000>; regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; - regulator-coupled-max-spread = <450000 450000>; + regulator-coupled-max-spread = <550000 550000>; regulator-always-on;

nvidia,tegra-cpu-regulator; @@ -425,10 +448,10 @@ ldo1 {

rtc_vdd_reg: ldo2 { regulator-name = "+1.2vs_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; - regulator-coupled-max-spread = <170000 450000>; + regulator-coupled-max-spread = <170000 550000>; regulator-always-on;

nvidia,tegra-rtc-regulator; @@ -517,6 +540,7 @@ usb@c5000000 { compatible = "nvidia,tegra20-udc"; status = "okay"; dr_mode = "peripheral"; + core-supply = <&core_vdd_reg>; };

usb-phy@c5000000 { @@ -527,6 +551,7 @@ usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + core-supply = <&core_vdd_reg>; };

usb-phy@c5004000 { @@ -537,6 +562,7 @@ usb-phy@c5004000 {

usb@c5008000 { status = "okay"; + core-supply = <&core_vdd_reg>; };

usb-phy@c5008000 { @@ -549,12 +575,14 @@ mmc@c8000000 { wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; bus-width = <4>; + core-supply = <&core_vdd_reg>; };

mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; + core-supply = <&core_vdd_reg>; };

backlight: backlight { @@ -569,6 +597,10 @@ backlight: backlight { backlight-boot-off; };

+ core-domain { + power-supply = <&core_vdd_reg>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi index b84afecea154..7e015cdfbc55 100644 --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -1,6 +1,46 @@ // SPDX-License-Identifier: GPL-2.0

/ { + core_opp_table: core-power-domain-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + core_opp_950: opp@950000 { + opp-microvolt = <950000 950000 1300000>; + opp-level = <950000>; + }; + + core_opp_1000: opp@1000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-level = <1000000>; + }; + + core_opp_1100: opp@1100000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-level = <1100000>; + }; + + core_opp_1200: opp@1200000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-level = <1200000>; + }; + + core_opp_1225: opp@1225000 { + opp-microvolt = <1225000 1225000 1300000>; + opp-level = <1225000>; + }; + + core_opp_1275: opp@1275000 { + opp-microvolt = <1275000 1275000 1300000>; + opp-level = <1275000>; + }; + + core_opp_1300: opp@1300000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-level = <1300000>; + }; + }; + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { compatible = "operating-points-v2";

@@ -8,102 +48,1003 @@ opp@36000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <36000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; };

opp@47500000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <47500000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; };

opp@50000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <50000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; };

opp@54000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <54000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; };

opp@57000000 { opp-microvolt = <950000 950000 1300000>; opp-hz = /bits/ 64 <57000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; };

opp@100000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <100000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@108000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <108000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@126666000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <126666000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@150000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <150000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@190000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <190000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@216000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <216000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@300000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <300000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@333000000 { opp-microvolt = <1000000 1000000 1300000>; opp-hz = /bits/ 64 <333000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; };

opp@380000000 { opp-microvolt = <1100000 1100000 1300000>; opp-hz = /bits/ 64 <380000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; };

opp@600000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <600000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; };

opp@666000000 { opp-microvolt = <1200000 1200000 1300000>; opp-hz = /bits/ 64 <666000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; };

opp@760000000 { opp-microvolt = <1300000 1300000 1300000>; opp-hz = /bits/ 64 <760000000>; opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1300>; + }; + }; + + gr2d_dvfs_opp_table: gr2d-opp-table { + compatible = "operating-points-v2"; + + opp@133000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@171000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + gr3d_dvfs_opp_table: gr3d-opp-table { + compatible = "operating-points-v2"; + + opp@114000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <114000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp@161500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp@161500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <161500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp@218500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp@247000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp@256500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp@285000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp@304000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <304000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp@323000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <323000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp@333500000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp@333500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp@351500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <351500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp@361000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <361000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp@380000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp@400000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp@400000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + }; + + disp1_dvfs_opp_table: disp1-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + disp2_dvfs_opp_table: disp2-opp-table { + compatible = "operating-points-v2"; + + opp@158000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + dsi_dvfs_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp@100000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@500000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <500000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + epp_dvfs_opp_table: epp-opp-table { + compatible = "operating-points-v2"; + + opp@133000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@171000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@247000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + hdmi_dvfs_opp_table: hdmi-opp-table { + compatible = "operating-points-v2"; + + opp@148500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <148500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + host1x_dvfs_opp_table: host1x-opp-table { + compatible = "operating-points-v2"; + + opp@104500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@133000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@166000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <166000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + ide_dvfs_opp_table: ide-opp-table { + compatible = "operating-points-v2"; + + opp@100000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + mipi_dvfs_opp_table: mipi-opp-table { + compatible = "operating-points-v2"; + + opp@40000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <40000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@60000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <60000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1275>; + }; + }; + + mpe_dvfs_opp_table: mpe-opp-table { + compatible = "operating-points-v2"; + + opp@104500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <104500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp@142500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <142500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp@152000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp@190000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp@190000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp@228000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp@228000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <228000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp@237500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp@266000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <266000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp@275500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + required-opps = <&core_opp_1200>; + }; + + opp@300000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000C>; + required-opps = <&core_opp_1100>; + }; + }; + + ndflash_dvfs_opp_table: ndflash-opp-table { + compatible = "operating-points-v2"; + + opp@130000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <130000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@150000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@158000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <158000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + + opp@164000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <164000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + nor_dvfs_opp_table: nor-opp-table { + compatible = "operating-points-v2"; + + opp@92000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <92000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + pcie_dvfs_opp_table: pcie-opp-table { + compatible = "operating-points-v2"; + + opp@250000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + sdmmc1_dvfs_opp_table: sdmmc1-opp-table { + compatible = "operating-points-v2"; + + opp@44000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@52000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc2_dvfs_opp_table: sdmmc2-opp-table { + compatible = "operating-points-v2"; + + opp@44000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@52000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc3_dvfs_opp_table: sdmmc3-opp-table { + compatible = "operating-points-v2"; + + opp@44000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@52000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sdmmc4_dvfs_opp_table: sdmmc4-opp-table { + compatible = "operating-points-v2"; + + opp@44000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <44000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@52000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <52000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + }; + + sclk_dvfs_opp_table: sclk-opp-table { + compatible = "operating-points-v2"; + + opp@95000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp@123500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp@133000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp@152000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp@159500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <159500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp@171000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp@180500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <180500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp@190000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp@207000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <207000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp@218500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp@222500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <222500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp@229500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <229500000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp@240000000,1225 { + opp-microvolt = <1225000 1225000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1225>; + }; + + opp@240000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <240000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1200>; + }; + + opp@247000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <247000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp@256500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <256500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + + opp@260000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <260000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1200>; + }; + + opp@262000000,1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <262000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1300>; + }; + + opp@264000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1275>; + }; + + opp@277500000,1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <277500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1300>; + }; + + opp@285000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1275>; + }; + + opp@292500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <292500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1200>; + }; + + opp@300000000,1300 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1300>; + }; + + opp@300000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1275>; + }; + }; + + tvo_dvfs_opp_table: tvo-opp-table { + compatible = "operating-points-v2"; + + opp@250000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <250000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1200>; + }; + }; + + usbd_dvfs_opp_table: usbd-opp-table { + compatible = "operating-points-v2"; + + opp@480000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb2_dvfs_opp_table: usb2-opp-table { + compatible = "operating-points-v2"; + + opp@480000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + usb3_dvfs_opp_table: usb3-opp-table { + compatible = "operating-points-v2"; + + opp@480000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; + }; + }; + + vde_dvfs_opp_table: vde-opp-table { + compatible = "operating-points-v2"; + + opp@95000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <95000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_950>; + }; + + opp@123500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1000>; + }; + + opp@123500000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <123500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_950>; + }; + + opp@152000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1000>; + }; + + opp@152000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <152000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_950>; + }; + + opp@171000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <171000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_950>; + }; + + opp@209000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1100>; + }; + + opp@209000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <209000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1000>; + }; + + opp@218500000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <218500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1000>; + }; + + opp@237500000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <237500000>; + opp-supported-hw = <0x0002>; + required-opps = <&core_opp_1100>; + }; + + opp@275500000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <275500000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1200>; + }; + + opp@285000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <285000000>; + opp-supported-hw = <0x0004>; + required-opps = <&core_opp_1100>; + }; + + opp@300000000,1275 { + opp-microvolt = <1275000 1275000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0001>; + required-opps = <&core_opp_1275>; + }; + + opp@300000000,1200 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0006>; + required-opps = <&core_opp_1200>; + }; + + opp@300000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1100>; + }; + }; + + vi_dvfs_opp_table: vi-opp-table { + compatible = "operating-points-v2"; + + opp@85000000,950 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <85000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_950>; + }; + + opp@100000000,1000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1000>; + }; + + opp@150000000,1100 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + required-opps = <&core_opp_1100>; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index c24d4a37613e..b617c69465fc 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -444,7 +444,7 @@ sys_reg: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -792,6 +792,10 @@ backlight: backlight { default-brightness-level = <6>; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 95e6bccdb4f6..bead3c88dec4 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,7 +357,7 @@ sys_reg: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -502,6 +502,10 @@ mmc@c8000600 { status = "okay"; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4bc87bc0c2a4..afcf8ff56087 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -379,6 +379,10 @@ mmc@c8000600 { bus-width = <4>; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; @@ -444,6 +448,14 @@ pci_vdd_reg: regulator@4 { regulator-always-on; };

+ vdd_core: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 055334ae3d28..0b03b3b0fd0c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -420,7 +420,7 @@ sys_reg: sys { regulator-always-on; };

- sm0 { + vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -587,6 +587,10 @@ backlight: backlight { default-brightness-level = <6>; };

+ core-domain { + power-supply = <&vdd_core>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6ce498178105..39963aa667c6 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -42,6 +42,8 @@ host1x@50000000 { clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&host1x_dvfs_opp_table>; + power-domains = <&pd_core>;

#address-cells = <1>; #size-cells = <1>; @@ -55,6 +57,7 @@ mpe@54040000 { clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + power-domains = <&pd_mpe>; };

vi@54080000 { @@ -64,6 +67,7 @@ vi@54080000 { clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; reset-names = "vi"; + power-domains = <&pd_venc>; };

epp@540c0000 { @@ -73,6 +77,7 @@ epp@540c0000 { clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + power-domains = <&pd_core>; };

isp@54100000 { @@ -82,6 +87,7 @@ isp@54100000 { clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + power-domains = <&pd_venc>; };

gr2d@54140000 { @@ -91,6 +97,8 @@ gr2d@54140000 { clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&gr2d_dvfs_opp_table>; + power-domains = <&pd_core>; };

gr3d@54180000 { @@ -99,6 +107,8 @@ gr3d@54180000 { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; + power-domains = <&pd_3d>; };

dc@54200000 { @@ -110,6 +120,8 @@ dc@54200000 { clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&disp1_dvfs_opp_table>; + power-domains = <&pd_core>;

nvidia,head = <0>;

@@ -138,6 +150,8 @@ dc@54240000 { clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&disp2_dvfs_opp_table>; + power-domains = <&pd_core>;

nvidia,head = <1>;

@@ -242,6 +256,169 @@ tegra_car: clock@60006000 { reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + clocks { + 2d { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&gr2d_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_GR2D>; + power-domains = <&pd_core>; + }; + + 3d { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&gr3d_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + }; + + dsi { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&dsi_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_DSI>; + power-domains = <&pd_core>; + }; + + epp { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&epp_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_EPP>; + power-domains = <&pd_core>; + }; + + hdmi { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&hdmi_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_HDMI>; + power-domains = <&pd_core>; + }; + + host1x { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&host1x_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + power-domains = <&pd_core>; + }; + + ide { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&ide_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_IDE>; + power-domains = <&pd_core>; + }; + + mipi { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&mipi_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_MIPI>; + power-domains = <&pd_core>; + }; + + mpe { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&mpe_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + }; + + ndflash { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&ndflash_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + power-domains = <&pd_core>; + }; + + nor { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&nor_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + power-domains = <&pd_core>; + }; + + pex { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&pcie_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_PEX>; + power-domains = <&pd_core>; + }; + + sdmmc1 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + power-domains = <&pd_core>; + }; + + sdmmc2 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&sdmmc2_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + power-domains = <&pd_core>; + }; + + sdmmc3 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + power-domains = <&pd_core>; + }; + + sdmmc4 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&sdmmc4_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + power-domains = <&pd_core>; + }; + + sclk { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&sclk_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&pd_core>; + }; + + tvo { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&tvo_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_TVO>; + power-domains = <&pd_core>; + }; + + usbd { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&usbd_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_USBD>; + power-domains = <&pd_core>; + }; + + usb2 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&usb2_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_USB2>; + power-domains = <&pd_core>; + }; + + usb3 { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&usb3_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_USB3>; + power-domains = <&pd_core>; + }; + + vde { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&vde_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + }; + + vi { + compatible = "nvidia,tegra20-clock"; + operating-points-v2 = <&vi_dvfs_opp_table>; + clocks = <&tegra_car TEGRA20_CLK_VI>; + power-domains = <&pd_core>; + }; + }; };

flow-controller@60007000 { @@ -319,6 +496,8 @@ vde@6001a000 { clocks = <&tegra_car TEGRA20_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; + operating-points-v2 = <&vde_dvfs_opp_table>; + power-domains = <&pd_vde>; };

apbmisc@70000800 { @@ -643,6 +822,40 @@ tegra_pmc: pmc@7000e400 { clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; + + powergates { + pd_3d: 3d { + clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car TEGRA20_CLK_GR3D>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car TEGRA20_CLK_VI>, + <&tegra_car TEGRA20_CLK_CSI>; + resets = <&tegra_car TEGRA20_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; };

mc: memory-controller@7000f000 { @@ -662,6 +875,7 @@ emc: memory-controller@7000f400 { reg = <0x7000f400 0x400>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EMC>; + power-domains = <&pd_core>; #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; @@ -887,6 +1101,12 @@ mmc@c8000600 { status = "disabled"; };

+ pd_core: core-domain { + compatible = "nvidia,tegra20-core-domain"; + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>;

Allow lower core voltages on Acer A500.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 78b307370a46..6b851cab0efa 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -578,7 +578,7 @@ sys_reg: sys {

vdd_core: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1300000>; regulator-coupled-with = <&rtc_vdd &vdd_cpu>; regulator-coupled-max-spread = <170000 550000>; @@ -619,7 +619,7 @@ ldo1 {

rtc_vdd: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1300000>; regulator-coupled-with = <&vdd_core &vdd_cpu>; regulator-coupled-max-spread = <170000 550000>;

Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.

Signed-off-by: Dmitry Osipenko digetx@gmail.com --- arch/arm/boot/dts/tegra20-ventana.dts | 40 ++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 14ace2ef749c..c2d9f38960bc 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -2,8 +2,10 @@ /dts-v1/;

#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> #include "tegra20.dtsi" #include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi"

/ { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -527,9 +529,10 @@ ldo_rtc { }; };

- temperature-sensor@4c { + nct1008: temperature-sensor@4c { compatible = "onnn,nct1008"; reg = <0x4c>; + #thermal-sensor-cells = <1>; }; };

@@ -615,10 +618,13 @@ clk32k_in: clock@0 {

cpus { cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; };

cpu@1 { + cpu-supply = <&vdd_cpu>; operating-points-v2 = <&cpu0_opp_table>; }; }; @@ -717,4 +723,36 @@ sound { <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 50C */ + temperature = <50000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; };