This patch series aims to support the MIPI DSI encoder found in the RZ/G2L SoC. It currently supports DSI mode only.
This unit supports MIPI Alliance Specification for Display Serial Interface (DSI) Specification. This unit provides a solution for transmitting MIPI DSI compliant digital video and packets. Normative References are below. * MIPI Alliance Specification for Display Serial Interface Version 1.3.1 * MIPI Alliance Specification for D-PHY Version 2.1
The following are key features of this unit.
* 1 channel * The number of Lane: 4-lane * Support up to Full HD (1920 × 1080), 60 fps (RGB888) * Maximum Bandwidth: 1.5 Gbps per lane * Support Output Data Format: RGB666 / RGB888
v1->v2: * Added full path for dsi-controller.yaml * Modeled DSI + D-PHY as single block and updated reg property * Fixed typo D_PHY->D-PHY * Updated description * Added interrupts and interrupt-names and updated the example * Driver rework based on dt-binding changes (DSI + D-PHY) as single block * Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi * Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write and rzg2l_mipi_dsi_link_write * Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read RFC->v1: * Added a ref to dsi-controller.yaml. * Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG and dropped DRM as it is implied by DRM_BRIDGE * Used devm_reset_control_get_exclusive() for reset handle * Removed bool hsclkmode from struct rzg2l_mipi_dsi * Added error check for pm, using pm_runtime_resume_and_get() instead of pm_runtime_get_sync() * Added check for unsupported formats in rzg2l_mipi_dsi_host_attach() * Avoided read-modify-write stopping hsclock * Used devm_platform_ioremap_resource for resource allocation * Removed unnecessary assert call from probe and remove. * wrap the line after the PTR_ERR() in probe() * Updated reset failure messages in probe * Fixed the typo arstc->prstc * Made hex constants to lower case. RFC: * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.... * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612....
Biju Das (2): dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings drm: rcar-du: Add RZ/G2L DSI driver
.../bindings/display/bridge/renesas,dsi.yaml | 175 +++++ drivers/gpu/drm/rcar-du/Kconfig | 8 + drivers/gpu/drm/rcar-du/Makefile | 1 + drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c | 686 ++++++++++++++++++ drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 ++++ 5 files changed, 1019 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com --- v1->v2: * Added full path for dsi-controller.yaml * Modeled DSI + D-PHY as single block and updated reg property * Fixed typo D_PHY->D-PHY * Updated description * Added interrupts and interrupt-names and updated the example RFC->v1: * Added a ref to dsi-controller.yaml. RFC:- * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.... --- .../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 000000000000..eebbf617c484 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L MIPI DSI Encoder + +maintainers: + - Biju Das biju.das.jz@bp.renesas.com + +description: | + This binding describes the MIPI DSI encoder embedded in the Renesas + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with + up to four data lanes. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + enum: + - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L + + reg: + maxItems: 1 + + interrupts: + items: + - description: Sequence operation channel 0 interrupt + - description: Sequence operation channel 1 interrupt + - description: Video-Input operation channel 1 interrupt + - description: DSI Packet Receive interrupt + - description: DSI Fatal Error interrupt + - description: DSI D-PHY PPI interrupt + - description: Debug interrupt + + interrupt-names: + items: + - const: seq0 + - const: seq1 + - const: vin1 + - const: rcv + - const: ferr + - const: ppi + - const: debug + + clocks: + items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode Receive clock + + clock-names: + items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + + resets: + items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + + reset-names: + items: + - const: rst + - const: arst + - const: prst + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + dsi0: dsi@10850000 { + compatible = "renesas,rzg2l-mipi-dsi"; + reg = <0x10850000 0x20000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; + }; +...
On Mon, 28 Mar 2022 07:49:30 +0100, Biju Das wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
v1->v2:
- Added full path for dsi-controller.yaml
- Modeled DSI + D-PHY as single block and updated reg property
- Fixed typo D_PHY->D-PHY
- Updated description
- Added interrupts and interrupt-names and updated the example
RFC->v1:
- Added a ref to dsi-controller.yaml.
RFC:-
.../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
Reviewed-by: Rob Herring robh@kernel.org
Hi Biju,
Thank you for the patch.
On Mon, Mar 28, 2022 at 07:49:30AM +0100, Biju Das wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
v1->v2:
- Added full path for dsi-controller.yaml
- Modeled DSI + D-PHY as single block and updated reg property
- Fixed typo D_PHY->D-PHY
- Updated description
- Added interrupts and interrupt-names and updated the example
RFC->v1:
- Added a ref to dsi-controller.yaml.
RFC:-
.../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 000000000000..eebbf617c484 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the Renesas
- RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
- up to four data lanes.
+allOf:
- $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L- reg:
- maxItems: 1
- interrupts:
- items:
- description: Sequence operation channel 0 interrupt- description: Sequence operation channel 1 interrupt- description: Video-Input operation channel 1 interrupt- description: DSI Packet Receive interrupt- description: DSI Fatal Error interrupt- description: DSI D-PHY PPI interrupt- description: Debug interrupt- interrupt-names:
- items:
- const: seq0- const: seq1- const: vin1- const: rcv- const: ferr- const: ppi- const: debug- clocks:
- items:
- description: DSI D-PHY PLL multiplied clock- description: DSI D-PHY system clock- description: DSI AXI bus clock- description: DSI Register access clock- description: DSI Video clock- description: DSI D-PHY Escape mode Receive clock
Isn't this the escape mode *transmit* clock ?
- clock-names:
- items:
- const: pllclk- const: sysclk- const: aclk- const: pclk- const: vclk- const: lpclk- resets:
- items:
- description: MIPI_DSI_CMN_RSTB- description: MIPI_DSI_ARESET_N- description: MIPI_DSI_PRESET_N- reset-names:
- items:
- const: rst- const: arst- const: prst- power-domains:
- maxItems: 1
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- properties:
port@0:$ref: /schemas/graph.yaml#/properties/portdescription: Parallel input portport@1:$ref: /schemas/graph.yaml#/$defs/port-baseunevaluatedProperties: falsedescription: DSI output portproperties:endpoint:$ref: /schemas/media/video-interfaces.yaml#unevaluatedProperties: falseproperties:data-lanes:minItems: 1maxItems: 4
You should specify the acceptable values, especially given that the hardware doesn't seem to support lane reordering.
required:- data-lanes- required:
- port@0- port@1+required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
- power-domains
- ports
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/r9a07g044-cpg.h>
Could you please swap those two lines to get them sorted alphabetically ?
With these comments addressed,
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
- dsi0: dsi@10850000 {
compatible = "renesas,rzg2l-mipi-dsi";reg = <0x10850000 0x20000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "seq0", "seq1", "vin1", "rcv","ferr", "ppi", "debug";clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,<&cpg R9A07G044_MIPI_DSI_ARESET_N>,<&cpg R9A07G044_MIPI_DSI_PRESET_N>;reset-names = "rst", "arst", "prst";power-domains = <&cpg>;ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;dsi0_in: endpoint {remote-endpoint = <&du_out_dsi0>;};};port@1 {reg = <1>;dsi0_out: endpoint {data-lanes = <1 2 3 4>;remote-endpoint = <&adv7535_in>;};};};- };
+...
Hi Laurent,
Thanks for the feedback.
Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
Hi Biju,
Thank you for the patch.
On Mon, Mar 28, 2022 at 07:49:30AM +0100, Biju Das wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
v1->v2:
- Added full path for dsi-controller.yaml
- Modeled DSI + D-PHY as single block and updated reg property
- Fixed typo D_PHY->D-PHY
- Updated description
- Added interrupts and interrupt-names and updated the example
RFC->v1:
- Added a ref to dsi-controller.yaml.
RFC:-
.../bindings/display/bridge/renesas,dsi.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 000000000000..eebbf617c484 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam +++ l @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id:
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the Renesas
- RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
+with
- up to four data lanes.
+allOf:
- $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L- reg:
- maxItems: 1
- interrupts:
- items:
- description: Sequence operation channel 0 interrupt- description: Sequence operation channel 1 interrupt- description: Video-Input operation channel 1 interrupt- description: DSI Packet Receive interrupt- description: DSI Fatal Error interrupt- description: DSI D-PHY PPI interrupt- description: Debug interrupt- interrupt-names:
- items:
- const: seq0- const: seq1- const: vin1- const: rcv- const: ferr- const: ppi- const: debug- clocks:
- items:
- description: DSI D-PHY PLL multiplied clock- description: DSI D-PHY system clock- description: DSI AXI bus clock- description: DSI Register access clock- description: DSI Video clock- description: DSI D-PHY Escape mode Receive clockIsn't this the escape mode *transmit* clock ?
Yep, There is a mismatch between clk document and hardware manual. I have reported this issue to HW team for fixing the clk document.
- clock-names:
- items:
- const: pllclk- const: sysclk- const: aclk- const: pclk- const: vclk- const: lpclk- resets:
- items:
- description: MIPI_DSI_CMN_RSTB- description: MIPI_DSI_ARESET_N- description: MIPI_DSI_PRESET_N- reset-names:
- items:
- const: rst- const: arst- const: prst- power-domains:
- maxItems: 1
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- properties:
port@0:$ref: /schemas/graph.yaml#/properties/portdescription: Parallel input portport@1:$ref: /schemas/graph.yaml#/$defs/port-baseunevaluatedProperties: falsedescription: DSI output portproperties:endpoint:$ref: /schemas/media/video-interfaces.yaml#unevaluatedProperties: falseproperties:data-lanes:minItems: 1maxItems: 4You should specify the acceptable values, especially given that the hardware doesn't seem to support lane reordering.
OK.
required:- data-lanes- required:
- port@0- port@1+required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
- power-domains
- ports
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/r9a07g044-cpg.h>
Could you please swap those two lines to get them sorted alphabetically ?
OK.
Cheers, Biju
With these comments addressed,
Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com
- dsi0: dsi@10850000 {
compatible = "renesas,rzg2l-mipi-dsi";reg = <0x10850000 0x20000>;interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "seq0", "seq1", "vin1", "rcv","ferr", "ppi", "debug";clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk","lpclk";
resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,<&cpg R9A07G044_MIPI_DSI_ARESET_N>,<&cpg R9A07G044_MIPI_DSI_PRESET_N>;reset-names = "rst", "arst", "prst";power-domains = <&cpg>;ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;dsi0_in: endpoint {remote-endpoint = <&du_out_dsi0>;};};port@1 {reg = <1>;dsi0_out: endpoint {data-lanes = <1 2 3 4>;remote-endpoint = <&adv7535_in>;};};};- };
+...
-- Regards,
Laurent Pinchart
Hi Biju,
On Mon, Mar 28, 2022 at 8:49 AM Biju Das biju.das.jz@bp.renesas.com wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
Thanks for your patch!
--- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the Renesas
- RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
- up to four data lanes.
+allOf:
- $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
Do you want to define SoC-specific compatible values, or can the IP revision be read from the hardware?
The rest LGTM (I'm no MIPI-DSI expert), so Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert,
Thanks for the feedback.
Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
Hi Biju,
On Mon, Mar 28, 2022 at 8:49 AM Biju Das biju.das.jz@bp.renesas.com wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
Thanks for your patch!
--- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam +++ l @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +---
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the Renesas
- RZ/G2L alike family of SoC's. The encoder can operate in DSI mode,
+with
- up to four data lanes.
+allOf:
- $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2LDo you want to define SoC-specific compatible values, or can the IP revision be read from the hardware?
There is no IP revision register for DSI. "rzg2l-mipi-dsi" is generic Compatible for both RZ/G2L and RZ/V2L.
So I can add SoC compatible for both these SoC's along with generic one.
Regards, Biju
The rest LGTM (I'm no MIPI-DSI expert), so Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi All,
Gentle ping. Are we happy with this patch series? Please let me know.
Cheers, Biju
Subject: [PATCH v2 0/2] Add RZ/G2L DSI driver
This patch series aims to support the MIPI DSI encoder found in the RZ/G2L SoC. It currently supports DSI mode only.
This unit supports MIPI Alliance Specification for Display Serial Interface (DSI) Specification. This unit provides a solution for transmitting MIPI DSI compliant digital video and packets. Normative References are below.
- MIPI Alliance Specification for Display Serial Interface Version 1.3.1
- MIPI Alliance Specification for D-PHY Version 2.1
The following are key features of this unit.
- 1 channel
- The number of Lane: 4-lane
- Support up to Full HD (1920 × 1080), 60 fps (RGB888)
- Maximum Bandwidth: 1.5 Gbps per lane
- Support Output Data Format: RGB666 / RGB888
v1->v2:
- Added full path for dsi-controller.yaml
- Modeled DSI + D-PHY as single block and updated reg property
- Fixed typo D_PHY->D-PHY
- Updated description
- Added interrupts and interrupt-names and updated the example
- Driver rework based on dt-binding changes (DSI + D-PHY) as single block
- Replaced link_mmio and phy_mmio with mmio in struct rzg2l_mipi_dsi
- Replaced rzg2l_mipi_phy_write with rzg2l_mipi_dsi_phy_write and rzg2l_mipi_dsi_link_write
- Replaced rzg2l_mipi_phy_read->rzg2l_mipi_dsi_link_read
RFC->v1:
- Added a ref to dsi-controller.yaml.
- Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG and dropped DRM as it is implied by DRM_BRIDGE
- Used devm_reset_control_get_exclusive() for reset handle
- Removed bool hsclkmode from struct rzg2l_mipi_dsi
- Added error check for pm, using pm_runtime_resume_and_get() instead of pm_runtime_get_sync()
- Added check for unsupported formats in rzg2l_mipi_dsi_host_attach()
- Avoided read-modify-write stopping hsclock
- Used devm_platform_ioremap_resource for resource allocation
- Removed unnecessary assert call from probe and remove.
- wrap the line after the PTR_ERR() in probe()
- Updated reset failure messages in probe
- Fixed the typo arstc->prstc
- Made hex constants to lower case.
RFC:
Biju Das (2): dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings drm: rcar-du: Add RZ/G2L DSI driver
.../bindings/display/bridge/renesas,dsi.yaml | 175 +++++ drivers/gpu/drm/rcar-du/Kconfig | 8 + drivers/gpu/drm/rcar-du/Makefile | 1 + drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c | 686 ++++++++++++++++++ drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h | 149 ++++ 5 files changed, 1019 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
-- 2.17.1
dri-devel@lists.freedesktop.org
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Biju Das -
Geert Uytterhoeven -
Laurent Pinchart -
Rob Herring