On Thu, Jun 10, 2021 at 01:46:24PM -0700, John.C.Harrison@Intel.com wrote:

From: John Harrison John.C.Harrison@Intel.com

Implement support for fetching the hardware description table from the GuC. The call is made twice - once without a destination buffer to query the size and then a second time to fill in the buffer.

This patch also adds a header file which lists all the attribute values currently defined for the table. This is included for reference as these are not currently used by the i915 driver itself.

Note that the table is only available on ADL-P and later platforms.

Cc: Michal Wajdeczko michal.wajdeczko@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@intel.com Signed-off-by: John Harrison John.C.Harrison@Intel.com

---

drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gt/intel_hwconfig_types.h | 102 +++++++++++ .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 + .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 + drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 167 ++++++++++++++++++ .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h | 19 ++ drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 + 9 files changed, 304 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_hwconfig_types.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2adb6b420c7c..8e957ca7c9f1 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -187,6 +187,7 @@ i915-y += gt/uc/intel_uc.o \ gt/uc/intel_guc_log.o \ gt/uc/intel_guc_log_debugfs.o \ gt/uc/intel_guc_submission.o \

•  gt/uc/intel_guc_hwconfig.o \
  

  gt/uc/intel_huc.o \ gt/uc/intel_huc_debugfs.o \ gt/uc/intel_huc_fw.o

diff --git a/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h b/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h new file mode 100644 index 000000000000..b09c0f65b93a --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_hwconfig_types.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: MIT */ +/*

• • Copyright © 2020 Intel Corporation
• */

+#ifndef _INTEL_HWCONFIG_TYPES_H_ +#define _INTEL_HWCONFIG_TYPES_H_

+/**

• • enum intel_hwconfig - Global definition of hwconfig table attributes
• • Intel devices provide a KLV (Key/Length/Value) table containing
• • the static hardware configuration for that platform.
• • This header defines the current attribute keys for this KLV.
• */

+enum intel_hwconfig {

• INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
• INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
• INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
• INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
• INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
• INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
• INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
• INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
• INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
• INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
• INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
• INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
• INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
• INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
• INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
• INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
• INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
• INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
• INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
• INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
• INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
• INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
• INTEL_HWCONFIG_MAX_RCS, /* 23 */
• INTEL_HWCONFIG_MAX_CCS, /* 24 */
• INTEL_HWCONFIG_MAX_VCS, /* 25 */
• INTEL_HWCONFIG_MAX_VECS, /* 26 */
• INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
• INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
• INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
• INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
• INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
• INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
• INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
• INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
• INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
• INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
• INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
• INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
• INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
• INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
• INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
• INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
• INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
• INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
• INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
• INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
• INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
• INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
• INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
• INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
• INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
• INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
• INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
• INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
• INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
• INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
• INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
• INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
• INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
• INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
• INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
• INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
• INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
• INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
• INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
• __INTEL_HWCONFIG_LIMIT

+};

+enum {

• INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
• INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,

+};

+#define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0) +#define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1) +#define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2)

+#endif /* _INTEL_HWCONFIG_TYPES_H_ */ diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index 90efef8a73e4..075f56a040b7 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -19,6 +19,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,

• INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100, INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, INTEL_GUC_ACTION_LIMIT

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h index 488b6061ee89..f9e2a6aaef4a 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h @@ -8,6 +8,10 @@

enum intel_guc_response_status { INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,

• INTEL_GUC_RESPONSE_NOT_SUPPORTED = 0x20,
• INTEL_GUC_RESPONSE_NO_ATTRIBUTE_TABLE = 0x201,
• INTEL_GUC_RESPONSE_NO_DECRYPTION_KEY = 0x202,
• INTEL_GUC_RESPONSE_DECRYPTION_FAILED = 0x204, INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,

};

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index f147cb389a20..01839d5eb130 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -407,13 +407,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, /* * No GuC command should ever take longer than 10ms. * Fast commands should still complete in 10us.

• * Except for the hwconfig table query, which takes ~50ms.
  

  */ ret = __intel_wait_for_register_fw(uncore, guc_send_reg(guc, 0), INTEL_GUC_MSG_TYPE_MASK, INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT,

• 			   10, 10, &status);
  

• 			   10, 100, &status);
  

  /* If GuC explicitly returned an error, convert it to -EIO */ if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status)) ret = -EIO;

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 4abc59f6f3cd..8307de463af0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -12,6 +12,7 @@ #include "intel_guc_ct.h" #include "intel_guc_log.h" #include "intel_guc_reg.h" +#include "intel_guc_hwconfig.h" #include "intel_uc_fw.h" #include "i915_utils.h" #include "i915_vma.h" @@ -27,6 +28,7 @@ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct;

• struct intel_guc_hwconfig hwconfig;

  /* intel_guc_recv interrupt related state */ spinlock_t irq_lock;

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c new file mode 100644 index 000000000000..938b1edb7209 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: MIT +/*

• • Copyright © 2020 Intel Corporation
• */

+#include "gt/intel_gt.h" +#include "gt/intel_hwconfig_types.h" +#include "i915_drv.h" +#include "i915_memcpy.h" +#include "intel_guc_hwconfig.h"

+static +inline struct intel_guc *hwconfig_to_guc(struct intel_guc_hwconfig *hwconfig) +{

• return container_of(hwconfig, struct intel_guc, hwconfig);

+}

+/**

• • GuC has a blob containing hardware configuration information (hwconfig).
• • This is formatted as a simple and flexible KLV (Key/Length/Value) table.
• • For example, a minimal version could be:
• • enum device_attr {

• • ATTR_SOME_VALUE = 0,
    

• • ATTR_SOME_MASK  = 1,
    

• • };
• • static const u32 hwconfig[] = {

• • ATTR_SOME_VALUE,
    

• • 1,		// Value Length in DWords
    

• • 8,		// Value
    

• • ATTR_SOME_MASK,
    

• • 3,
    

• • 0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000,
    

• • };
• • The attribute ids are defined in a hardware spec. The current list as
• • known to the i915 driver can be found in i915/gt/intel_guc_hwconfig_types.h
• */

+static int __guc_action_get_hwconfig(struct intel_guc_hwconfig *hwconfig,

• 		     u32 ggtt_offset, u32 ggtt_size)
  

+{

• struct intel_guc *guc = hwconfig_to_guc(hwconfig);
• struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
• u32 action[] = {

• INTEL_GUC_ACTION_GET_HWCONFIG,
  

• ggtt_offset,
  

• ggtt_size,
  

• (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915),
  

• };
• int ret;
• ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
• if (ret == -ENXIO)

• return -ENOENT;
  

• if (!ggtt_size && !ret)

• ret = -EINVAL;
  

• return ret;

+}

+static int guc_hwconfig_discover_size(struct intel_guc_hwconfig *hwconfig) +{

• int ret;
• /* Sending a query with too small a table will return the size of the table */
• ret = __guc_action_get_hwconfig(hwconfig, 0, 0);
• if (ret < 0)

• return ret;
  

• hwconfig->size = ret;
• return 0;

+}

+static int guc_hwconfig_fill_buffer(struct intel_guc_hwconfig *hwconfig) +{

• struct intel_guc *guc = hwconfig_to_guc(hwconfig);
• struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
• u32 ggtt_offset;
• int ret;
• struct i915_vma *vma;
• void *vaddr;
• GEM_BUG_ON(!hwconfig->size);
• ret = intel_guc_allocate_and_map_vma(guc, hwconfig->size, &vma, &vaddr);
• if (ret) {

• drm_err(&i915->drm, "HWConfig: Failed to allocate buffer: %d!\n", ret);
  

• return ret;
  

• }
• ggtt_offset = intel_guc_ggtt_offset(guc, vma);
• ret = __guc_action_get_hwconfig(hwconfig, ggtt_offset, hwconfig->size);
• if (ret >= 0)

• memcpy(hwconfig->ptr, vaddr, hwconfig->size);
  

• i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP);
• return ret;

+}

+static bool has_table(struct drm_i915_private *i915) +{

• if (IS_ALDERLAKE_P(i915)) {

• if (IS_ADLP_GT_STEP(i915, STEP_A0, STEP_A0))
  

• 	return 0;
  

• return 1;
  

• }
• return 0;

+}

+/**

• • intel_guc_hwconfig_init - Initialize the HWConfig
• • Retrieve the HWConfig table from the GuC and save it away in a local memory
• • allocation. It can then be queried on demand by other users later on.
• */

+int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig) +{

• struct intel_guc *guc = hwconfig_to_guc(hwconfig);
• struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
• int ret;
• if (!has_table(i915))

• return 0;
  

• ret = guc_hwconfig_discover_size(hwconfig);
• if (ret)

• return ret;
  

• hwconfig->ptr = kmalloc(hwconfig->size, GFP_KERNEL);
• if (!hwconfig->ptr) {

• hwconfig->size = 0;
  

• return -ENOMEM;
  

• }
• ret = guc_hwconfig_fill_buffer(hwconfig);
• if (ret < 0) {

• kfree(hwconfig->ptr);
  

• hwconfig->size = 0;
  

• hwconfig->ptr = NULL;
  

• return ret;
  

• }
• return 0;

+}

+/**

• • intel_guc_hwconfig_fini - Finalize the HWConfig
• • Free up the memory allocation holding the table.
• */

+void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig) +{

• if (!hwconfig->size)

• return;
  

• kfree(hwconfig->ptr);
• hwconfig->size = 0;
• hwconfig->ptr = NULL;

+} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h new file mode 100644 index 000000000000..91e96d88d713 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/*

• • Copyright © 2020 Intel Corporation
• */

+#ifndef _INTEL_GUC_HWCONFIG_H_ +#define _INTEL_GUC_HWCONFIG_H_

+#include <linux/types.h>

+struct intel_guc_hwconfig {

• u32 size;
• void *ptr;

+};

+int intel_guc_hwconfig_init(struct intel_guc_hwconfig *hwconfig); +void intel_guc_hwconfig_fini(struct intel_guc_hwconfig *hwconfig);

+#endif /* _INTEL_GUC_HWCONFIG_H_ */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 6d8b9233214e..b289693f9767 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -502,6 +502,10 @@ static int __uc_init_hw(struct intel_uc *uc)

intel_huc_auth(huc);

• ret = intel_guc_hwconfig_init(&guc->hwconfig);

As discussed on another thread, shouldn't we move this above guc_enable_communication() to not mix MMIO and CTB communication?

Matt

• if (ret)

• goto err_log_capture;
  

• if (intel_uc_uses_guc_submission(uc)) intel_guc_submission_enable(guc);

@@ -552,6 +556,8 @@ static void __uc_fini_hw(struct intel_uc *uc) if (intel_uc_uses_guc_submission(uc)) intel_guc_submission_disable(guc);

• intel_guc_hwconfig_fini(&guc->hwconfig);
• __uc_sanitize(uc);

}

-- 2.25.1

On 10.06.2021 22:46, John.C.Harrison@Intel.com wrote:

From: Rodrigo Vivi rodrigo.vivi@intel.com

GuC contains a consolidated table with a bunch of information about the current device.

Previously, this information was spread and hardcoded to all the components including GuC, i915 and various UMDs. The goal here is to consolidate the data into GuC in a way that all interested components can grab the very latest and synchronized information using a simple query.

As per most of the other queries, this one can be called twice. Once with item.length=0 to determine the exact buffer size, then allocate the user memory and call it again for to retrieve the table data. For example: struct drm_i915_query_item item = { .query_id = DRM_I915_QUERY_HWCONCFIG_TABLE; }; query.items_ptr = (int64_t) &item; query.num_items = 1;

ioctl(fd, DRM_IOCTL_I915_QUERY, query, sizeof(query));

if (item.length <= 0) return -ENOENT;

data = malloc(item.length); item.data_ptr = (int64_t) &data; ioctl(fd, DRM_IOCTL_I915_QUERY, query, sizeof(query));

// Parse the data as appropriate...

The returned array is a simple and flexible KLV (Key/Length/Value) formatted table. For example, it could be just: enum device_attr { ATTR_SOME_VALUE = 0, ATTR_SOME_MASK = 1, };

static const u32 hwconfig[] = { ATTR_SOME_VALUE, 1, // Value Length in DWords 8, // Value

  ATTR_SOME_MASK,
  3,
  0x00FFFFFFFF, 0xFFFFFFFF, 0xFF000000,

};

same example was already added to code in previous patch maybe just refer to that documentation ?

The attribute ids are defined in a hardware spec. The current list as known to the i915 driver can be found in i915/gt/intel_guc_hwconfig_types.h

previous patch introduced i915/gt/intel_hwconfig_types.h

also, i915 seems to be not using any/many of them directly, so it could happen that GuC will return new/updated klvs, so shouldn't we make this klv list more external and maybe even define as uabi header?

Cc: Tvrtko Ursulin tvrtko.ursulin@linux.intel.com Cc: Kenneth Graunke kenneth.w.graunke@intel.com Cc: Michal Wajdeczko michal.wajdeczko@intel.com Cc: Slawomir Milczarek slawomir.milczarek@intel.com Signed-off-by: Rodrigo Vivi rodrigo.vivi@intel.com Signed-off-by: John Harrison John.C.Harrison@Intel.com

---

drivers/gpu/drm/i915/i915_query.c | 23 +++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index e49da36c62fb..96bd8fb3e895 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -480,12 +480,35 @@ static int query_memregion_info(struct drm_i915_private *i915, return total_length; }

+static int query_hwconfig_table(struct drm_i915_private *i915,

• 		struct drm_i915_query_item *query_item)
  

+{

• struct intel_gt *gt = &i915->gt;
• struct intel_guc_hwconfig *hwconfig = &gt->uc.guc.hwconfig;
• if (!hwconfig->size || !hwconfig->ptr)

• return -ENODEV;
  

shouldn't we also have:

if (query_item->flags != 0) return -EINVAL;

• if (query_item->length == 0)

• return hwconfig->size;
  

• if (query_item->length < hwconfig->size)

• return -EINVAL;
  

• if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),

• 	 hwconfig->ptr, hwconfig->size))
  

• return -EFAULT;
  

• return hwconfig->size;

+}

static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, query_engine_info, query_perf_config, query_memregion_info,

• query_hwconfig_table,

};

int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index c2c7759b7d2e..87d369cae22a 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2233,6 +2233,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_ENGINE_INFO 2 #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 +#define DRM_I915_QUERY_HWCONFIG_TABLE 5

hmm, not sure is this single line satisfies below "well documented" requirement ;)

/* Must be kept compact -- no holes and well documented */

/**

On Thu, Jun 10, 2021 at 01:46:26PM -0700, John.C.Harrison@Intel.com wrote:

From: John Harrison John.C.Harrison@Intel.com

Various UMDs need to know the L3 bank count. So add a query API for it.

Signed-off-by: John Harrison John.C.Harrison@Intel.com

drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/i915_query.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + include/uapi/drm/i915_drm.h | 1 + 5 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 2161bf01ef8b..708bb3581d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,

intel_sseu_dump(&info->sseu, p); }

+int intel_gt_get_l3bank_count(struct intel_gt *gt)

Small nit, this function is ..'l3bank_count' while the define for query is ..'L3_BANK_COUNT'. I'm thinking this function should have a space between l3 & bank for consistency.

+{

• struct drm_i915_private *i915 = gt->i915;
• intel_wakeref_t wakeref;
• u32 fuse3;
• if (GRAPHICS_VER(i915) < 12)

• return -ENODEV;
  

• with_intel_runtime_pm(gt->uncore->rpm, wakeref)

• fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
  

• return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));

+} diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 7ec395cace69..46aa1cf4cf30 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)

void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); +int intel_gt_get_l3bank_count(struct intel_gt *gt);

void intel_gt_watchdog_work(struct work_struct *work);

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 96bd8fb3e895..0e92bb2d21b2 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -10,6 +10,7 @@ #include "i915_perf.h" #include "i915_query.h" #include <uapi/drm/i915_drm.h> +#include "gt/intel_gt.h"

static int copy_query_item(void *query_hdr, size_t query_sz, u32 total_length, @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915, return hwconfig->size; }

+static int query_l3banks(struct drm_i915_private *i915,

• 	 struct drm_i915_query_item *query_item)
  

+{

• u32 banks;
• if (query_item->length == 0)

• return sizeof(banks);
  

• if (query_item->length < sizeof(banks))

• return -EINVAL;
  

• banks = intel_gt_get_l3bank_count(&i915->gt);
• if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),

• 	 &banks, sizeof(banks)))
  

• return -EFAULT;
  

• return sizeof(banks);

+}

static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_perf_config, query_memregion_info, query_hwconfig_table,

• query_l3banks,

Another nit, for consistency query_l3banks -> query_l3_bank_count.

With these nits fixed: Reviewed-by: Matthew Brost matthew.brost@intel.com

};

int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eb13c601d680..e9ba88fe3db7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) #define GEN10_L3BANK_PAIR_COUNT 4 #define GEN10_L3BANK_MASK 0x0F +#define GEN12_GT_L3_MODE_MASK 0xFF

#define GEN8_EU_DISABLE0 _MMIO(0x9134) #define GEN8_EU_DIS0_S0_MASK 0xffffff diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 87d369cae22a..20d18cca5066 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2234,6 +2234,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 #define DRM_I915_QUERY_HWCONFIG_TABLE 5 +#define DRM_I915_QUERY_L3_BANK_COUNT 6 /* Must be kept compact -- no holes and well documented */

/**

2.25.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On 10/06/2021 23:46, John.C.Harrison@Intel.com wrote:

From: John Harrison John.C.Harrison@Intel.com

Various UMDs need to know the L3 bank count. So add a query API for it.

Signed-off-by: John Harrison John.C.Harrison@Intel.com

drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/i915_query.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + include/uapi/drm/i915_drm.h | 1 + 5 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 2161bf01ef8b..708bb3581d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,

intel_sseu_dump(&info->sseu, p); }

+int intel_gt_get_l3bank_count(struct intel_gt *gt) +{

• struct drm_i915_private *i915 = gt->i915;
• intel_wakeref_t wakeref;
• u32 fuse3;
• if (GRAPHICS_VER(i915) < 12)

• return -ENODEV;
  

• with_intel_runtime_pm(gt->uncore->rpm, wakeref)

• fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
  

• return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));

+} diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 7ec395cace69..46aa1cf4cf30 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)

void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); +int intel_gt_get_l3bank_count(struct intel_gt *gt);

void intel_gt_watchdog_work(struct work_struct *work);

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 96bd8fb3e895..0e92bb2d21b2 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -10,6 +10,7 @@ #include "i915_perf.h" #include "i915_query.h" #include <uapi/drm/i915_drm.h> +#include "gt/intel_gt.h"

static int copy_query_item(void *query_hdr, size_t query_sz, u32 total_length, @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915, return hwconfig->size; }

+static int query_l3banks(struct drm_i915_private *i915,

• 	 struct drm_i915_query_item *query_item)
  

+{

• u32 banks;
• if (query_item->length == 0)

• return sizeof(banks);
  

• if (query_item->length < sizeof(banks))

• return -EINVAL;
  

• banks = intel_gt_get_l3bank_count(&i915->gt);
• if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),

• 	 &banks, sizeof(banks)))
  

• return -EFAULT;
  

• return sizeof(banks);

+}

• static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info,

@@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_perf_config, query_memregion_info, query_hwconfig_table,

• query_l3banks, };

  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eb13c601d680..e9ba88fe3db7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) #define GEN10_L3BANK_PAIR_COUNT 4 #define GEN10_L3BANK_MASK 0x0F +#define GEN12_GT_L3_MODE_MASK 0xFF

#define GEN8_EU_DISABLE0 _MMIO(0x9134) #define GEN8_EU_DIS0_S0_MASK 0xffffff diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 87d369cae22a..20d18cca5066 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2234,6 +2234,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 #define DRM_I915_QUERY_HWCONFIG_TABLE 5 +#define DRM_I915_QUERY_L3_BANK_COUNT 6

A little bit of documentation about the format of the return data would be nice :)

-Lionel

/* Must be kept compact -- no holes and well documented */

/**

On Thu, Jun 10, 2021 at 10:46 PM John.C.Harrison@intel.com wrote:

From: John Harrison John.C.Harrison@Intel.com

Various UMDs need to know the L3 bank count. So add a query API for it.

Please link to both the igt test submission for this (there's not even a Test-with: on the cover letter) and the merge requests for the various UMD which uses new uapi. Also as other mentioned, full uapi kerneldoc is needed too. Please fill in any gaps in the existing docs that relate to your addition directly (like we've e.g. done for the extension chaining when adding lmem support).

Thanks, Daniel

Signed-off-by: John Harrison John.C.Harrison@Intel.com

drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/i915_query.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + include/uapi/drm/i915_drm.h | 1 + 5 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 2161bf01ef8b..708bb3581d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,

    intel_sseu_dump(&info->sseu, p);

}

+int intel_gt_get_l3bank_count(struct intel_gt *gt) +{

•   struct drm_i915_private *i915 = gt->i915;
  

•   intel_wakeref_t wakeref;
  

•   u32 fuse3;
  

•   if (GRAPHICS_VER(i915) < 12)
  

•           return -ENODEV;
  

•   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
  

•           fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
  

•   return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
  

+} diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 7ec395cace69..46aa1cf4cf30 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)

void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); +int intel_gt_get_l3bank_count(struct intel_gt *gt);

void intel_gt_watchdog_work(struct work_struct *work);

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 96bd8fb3e895..0e92bb2d21b2 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -10,6 +10,7 @@ #include "i915_perf.h" #include "i915_query.h" #include <uapi/drm/i915_drm.h> +#include "gt/intel_gt.h"

static int copy_query_item(void *query_hdr, size_t query_sz, u32 total_length, @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915, return hwconfig->size; }

+static int query_l3banks(struct drm_i915_private *i915,

•                    struct drm_i915_query_item *query_item)
  

+{

•   u32 banks;
  

•   if (query_item->length == 0)
  

•           return sizeof(banks);
  

•   if (query_item->length < sizeof(banks))
  

•           return -EINVAL;
  

•   banks = intel_gt_get_l3bank_count(&i915->gt);
  

•   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
  

•                    &banks, sizeof(banks)))
  

•           return -EFAULT;
  

•   return sizeof(banks);
  

+}

static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_perf_config, query_memregion_info, query_hwconfig_table,

•   query_l3banks,
  

};

int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eb13c601d680..e9ba88fe3db7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) #define GEN10_L3BANK_PAIR_COUNT 4 #define GEN10_L3BANK_MASK 0x0F +#define GEN12_GT_L3_MODE_MASK 0xFF

#define GEN8_EU_DISABLE0 _MMIO(0x9134) #define GEN8_EU_DIS0_S0_MASK 0xffffff diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 87d369cae22a..20d18cca5066 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2234,6 +2234,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 #define DRM_I915_QUERY_HWCONFIG_TABLE 5 +#define DRM_I915_QUERY_L3_BANK_COUNT 6 /* Must be kept compact -- no holes and well documented */

    /**

-- 2.25.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Thu, Jul 15, 2021 at 03:16:08PM -0700, John Harrison wrote:

On 6/16/2021 03:25, Daniel Vetter wrote:

...

On Thu, Jun 10, 2021 at 10:46 PM John.C.Harrison@intel.com wrote:

...

From: John Harrison John.C.Harrison@Intel.com

Various UMDs need to know the L3 bank count. So add a query API for it.

Please link to both the igt test submission for this (there's not even a Test-with: on the cover letter)

Is there a wiki page that describes all such tags? That is not one I was aware of and I can't find anything in the Kernel patch submission wiki or DRM maintainers wiki that mentions it.

It's in the CI docs (linked from the main page too)

https://intel-gfx-ci.01.org/test-with.html

...

and the merge requests for the various UMD which uses new uapi.

Is there a particular tag to use for this?

I think often just a link to the merge request in the cover letter. Sometimes people also put the link in the uapi patch itself in the commit message. Which I think would be best. -Daniel

John.

...

Also as other mentioned, full uapi kerneldoc is needed too. Please fill in any gaps in the existing docs that relate to your addition directly (like we've e.g. done for the extension chaining when adding lmem support).

Thanks, Daniel

...

Signed-off-by: John Harrison John.C.Harrison@Intel.com

drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/i915_query.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + include/uapi/drm/i915_drm.h | 1 + 5 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 2161bf01ef8b..708bb3581d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,

     intel_sseu_dump(&info->sseu, p);

}

+int intel_gt_get_l3bank_count(struct intel_gt *gt) +{

•   struct drm_i915_private *i915 = gt->i915;
  

•   intel_wakeref_t wakeref;
  

•   u32 fuse3;
  

•   if (GRAPHICS_VER(i915) < 12)
  

•           return -ENODEV;
  

•   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
  

•           fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
  

•   return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
  

+} diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 7ec395cace69..46aa1cf4cf30 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)

void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p); +int intel_gt_get_l3bank_count(struct intel_gt *gt);

void intel_gt_watchdog_work(struct work_struct *work);

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 96bd8fb3e895..0e92bb2d21b2 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -10,6 +10,7 @@ #include "i915_perf.h" #include "i915_query.h" #include <uapi/drm/i915_drm.h> +#include "gt/intel_gt.h"

static int copy_query_item(void *query_hdr, size_t query_sz, u32 total_length, @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915, return hwconfig->size; }

+static int query_l3banks(struct drm_i915_private *i915,

•                    struct drm_i915_query_item *query_item)
  

+{

•   u32 banks;
  

•   if (query_item->length == 0)
  

•           return sizeof(banks);
  

•   if (query_item->length < sizeof(banks))
  

•           return -EINVAL;
  

•   banks = intel_gt_get_l3bank_count(&i915->gt);
  

•   if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
  

•                    &banks, sizeof(banks)))
  

•           return -EFAULT;
  

•   return sizeof(banks);
  

+}

• static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info,

@@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_perf_config, query_memregion_info, query_hwconfig_table,

•   query_l3banks,
  

  };

  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eb13c601d680..e9ba88fe3db7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) #define GEN10_L3BANK_PAIR_COUNT 4 #define GEN10_L3BANK_MASK 0x0F +#define GEN12_GT_L3_MODE_MASK 0xFF

#define GEN8_EU_DISABLE0 _MMIO(0x9134) #define GEN8_EU_DIS0_S0_MASK 0xffffff diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 87d369cae22a..20d18cca5066 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2234,6 +2234,7 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_PERF_CONFIG 3 #define DRM_I915_QUERY_MEMORY_REGIONS 4 #define DRM_I915_QUERY_HWCONFIG_TABLE 5 +#define DRM_I915_QUERY_L3_BANK_COUNT 6 /* Must be kept compact -- no holes and well documented */

     /**

-- 2.25.1

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx