[drm-tip:drm-tip 3/9] drivers/gpu/drm/i915/gt/intel_engine_cs.c:1428:31: error: 'struct intel_context' has no member named 'lrc_desc' - dri-devel - freedesktop.org experimental mailing list

7 May 2020


      tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   6c0ee41a7c3201ef2a89800234803a95f65989be
commit: e81df648fc5bcd0fa702df401e02b7914c76ff71 [3/9] Merge remote-tracking branch 'drm/drm-next' into drm-tip
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce:
        git checkout e81df648fc5bcd0fa702df401e02b7914c76ff71
        # save the attached .config to linux build tree
        make ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot lkp@intel.com
Note: the drm-tip/drm-tip HEAD 6c0ee41a7c3201ef2a89800234803a95f65989be builds fine.
      It only hurts bisectibility.
All error/warnings (new ones prefixed by >>):
In file included from include/asm-generic/bug.h:19:0,
                    from arch/x86/include/asm/bug.h:83,
                    from include/linux/bug.h:5,
                    from include/linux/seq_file.h:7,
                    from include/drm/drm_print.h:31,
                    from drivers/gpu/drm/i915/gt/intel_engine_cs.c:25:
   drivers/gpu/drm/i915/gt/intel_engine_cs.c: In function 'intel_engine_print_registers':
...
...
drivers/gpu/drm/i915/gt/intel_engine_cs.c:1428:31: error: 'struct intel_context' has no member named 'lrc_desc'
upper_32_bits(rq->context->lrc_desc));
                                  ^
   include/linux/kernel.h:183:35: note: in definition of macro 'upper_32_bits'
    #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
                                      ^
   drivers/gpu/drm/i915/gt/intel_engine_cs.c:1440:31: error: 'struct intel_context' has no member named 'lrc_desc'
         upper_32_bits(rq->context->lrc_desc));
                                  ^
   include/linux/kernel.h:183:35: note: in definition of macro 'upper_32_bits'
    #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
                                      ^
--
   drivers/gpu/drm/i915/gt/intel_lrc.c: In function '__execlists_schedule_in':
...
...
drivers/gpu/drm/i915/gt/intel_lrc.c:1256:35: error: 'struct intel_engine_execlists' has no member named 'ccid'
ce->lrc.ccid |= engine->execlists.ccid;
                                      ^
   In file included from include/linux/interrupt.h:6:0,
                    from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
   drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'timeslice_yield':
...
...
drivers/gpu/drm/i915/gt/intel_lrc.c:1804:34: error: 'struct intel_context' has no member named 'lrc_desc'
return upper_32_bits(rq->context->lrc_desc) == READ_ONCE(el->yield);
                                     ^
   include/linux/kernel.h:183:35: note: in definition of macro 'upper_32_bits'
    #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
                                      ^
   drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'active_context':
   drivers/gpu/drm/i915/gt/intel_lrc.c:2850:32: error: 'struct intel_context' has no member named 'lrc_desc'
      if (upper_32_bits(rq->context->lrc_desc) == ccid) {
                                   ^
   include/linux/kernel.h:183:35: note: in definition of macro 'upper_32_bits'
    #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
                                      ^
   drivers/gpu/drm/i915/gt/intel_lrc.c:2859:32: error: 'struct intel_context' has no member named 'lrc_desc'
      if (upper_32_bits(rq->context->lrc_desc) == ccid) {
                                   ^
   include/linux/kernel.h:183:35: note: in definition of macro 'upper_32_bits'
    #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
                                      ^
   drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'intel_execlists_submission_setup':
   drivers/gpu/drm/i915/gt/intel_lrc.c:4668:12: error: 'struct intel_engine_execlists' has no member named 'ccid'
      execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
               ^~
   drivers/gpu/drm/i915/gt/intel_lrc.c:4669:12: error: 'struct intel_engine_execlists' has no member named 'ccid'
      execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
               ^~
   drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'timeslice_yield':
...
...
drivers/gpu/drm/i915/gt/intel_lrc.c:1805:1: warning: control reaches end of non-void function [-Wreturn-type]
}
    ^
vim +1428 drivers/gpu/drm/i915/gt/intel_engine_cs.c
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1318  
eca153603f2f020 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-18  1319  static void intel_engine_print_registers(struct intel_engine_cs *engine,
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1320  					 struct drm_printer *m)
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1321  {
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1322  	struct drm_i915_private *dev_priv = engine->i915;
c36eebd9ba5d70b drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-09  1323  	struct intel_engine_execlists * const execlists = &engine->execlists;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1324  	u64 addr;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1325  
b26496ae786d5f3 drivers/gpu/drm/i915/gt/intel_engine_cs.c Stuart Summers         2019-08-13  1326  	if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1327  		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1328  	if (HAS_EXECLISTS(dev_priv)) {
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1329  		drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1330  			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1331  		drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1332  			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
c4e8ba7390346a7 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-04-07  1333  	}
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1334  	drm_printf(m, "\tRING_START: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1335  		   ENGINE_READ(engine, RING_START));
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1336  	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1337  		   ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1338  	drm_printf(m, "\tRING_TAIL:  0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1339  		   ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
3c75de5b983a0a1 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-26  1340  	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1341  		   ENGINE_READ(engine, RING_CTL),
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1342  		   ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
3c75de5b983a0a1 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-26  1343  	if (INTEL_GEN(engine->i915) > 2) {
3c75de5b983a0a1 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-26  1344  		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1345  			   ENGINE_READ(engine, RING_MI_MODE),
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1346  			   ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
3c75de5b983a0a1 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-26  1347  	}
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1348  
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1349  	if (INTEL_GEN(dev_priv) >= 6) {
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1350  		drm_printf(m, "\tRING_IMR:   0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1351  			   ENGINE_READ(engine, RING_IMR));
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1352  		drm_printf(m, "\tRING_ESR:   0x%08x\n",
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1353  			   ENGINE_READ(engine, RING_ESR));
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1354  		drm_printf(m, "\tRING_EMR:   0x%08x\n",
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1355  			   ENGINE_READ(engine, RING_EMR));
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1356  		drm_printf(m, "\tRING_EIR:   0x%08x\n",
70a76a9b8e9d553 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-01-28  1357  			   ENGINE_READ(engine, RING_EIR));
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1358  	}
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1359  
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1360  	addr = intel_engine_get_active_head(engine);
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1361  	drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1362  		   upper_32_bits(addr), lower_32_bits(addr));
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1363  	addr = intel_engine_get_last_batch_head(engine);
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1364  	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1365  		   upper_32_bits(addr), lower_32_bits(addr));
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1366  	if (INTEL_GEN(dev_priv) >= 8)
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1367  		addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1368  	else if (INTEL_GEN(dev_priv) >= 4)
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1369  		addr = ENGINE_READ(engine, RING_DMA_FADD);
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1370  	else
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1371  		addr = ENGINE_READ(engine, DMA_FADD_I8XX);
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1372  	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1373  		   upper_32_bits(addr), lower_32_bits(addr));
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1374  	if (INTEL_GEN(dev_priv) >= 4) {
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1375  		drm_printf(m, "\tIPEIR: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1376  			   ENGINE_READ(engine, RING_IPEIR));
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1377  		drm_printf(m, "\tIPEHR: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1378  			   ENGINE_READ(engine, RING_IPEHR));
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1379  	} else {
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1380  		drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1381  		drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
a0cf579080a89a4 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-18  1382  	}
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1383  
fb5c551ad510e4a drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-11-20  1384  	if (HAS_EXECLISTS(dev_priv)) {
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1385  		struct i915_request * const *port, *rq;
0ca88ba0d6347cf drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2019-01-28  1386  		const u32 *hws =
0ca88ba0d6347cf drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2019-01-28  1387  			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1388  		const u8 num_entries = execlists->csb_size;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1389  		unsigned int idx;
df4f94e810fc270 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-08-21  1390  		u8 read, write;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1391  
3a7a92aba8fb771 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-23  1392  		drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1393  			   yesno(test_bit(TASKLET_STATE_SCHED,
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1394  					  &engine->execlists.tasklet.state)),
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1395  			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
3a7a92aba8fb771 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-23  1396  			   repr_timer(&engine->execlists.preempt),
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1397  			   repr_timer(&engine->execlists.timer));
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1398  
df4f94e810fc270 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-08-21  1399  		read = execlists->csb_head;
df4f94e810fc270 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-08-21  1400  		write = READ_ONCE(*execlists->csb_write);
df4f94e810fc270 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-08-21  1401  
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1402  		drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1403  			   ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1404  			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1405  			   read, write, num_entries);
2229adc81380c46 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-16  1406  
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1407  		if (read >= num_entries)
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1408  			read = 0;
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1409  		if (write >= num_entries)
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1410  			write = 0;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1411  		if (read > write)
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1412  			write += num_entries;
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1413  		while (read < write) {
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1414  			idx = ++read % num_entries;
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1415  			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
7d4c75d9097a003 drivers/gpu/drm/i915/intel_engine_cs.c    Mika Kuoppala          2019-04-05  1416  				   idx, hws[idx * 2], hws[idx * 2 + 1]);
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1417  		}
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1418  
c36eebd9ba5d70b drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-09  1419  		execlists_active_lock_bh(execlists);
fecffa4668cf62e drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-11-11  1420  		rcu_read_lock();
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1421  		for (port = execlists->active; (rq = *port); port++) {
489645d522dfa96 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-02-18  1422  			char hdr[160];
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1423  			int len;
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1424  
61f874d6e001a9e drivers/gpu/drm/i915/gt/intel_engine_cs.c Takashi Iwai           2020-03-11  1425  			len = scnprintf(hdr, sizeof(hdr),
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1426  					"\t\tActive[%d]:  ccid:%08x, ",
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1427  					(int)(port - execlists->active),
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31 @1428  					upper_32_bits(rq->context->lrc_desc));
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1429  			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
61f874d6e001a9e drivers/gpu/drm/i915/gt/intel_engine_cs.c Takashi Iwai           2020-03-11  1430  			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1431  			print_request(m, rq, hdr);
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1432  		}
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1433  		for (port = execlists->pending; (rq = *port); port++) {
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1434  			char hdr[160];
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1435  			int len;
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1436  
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1437  			len = scnprintf(hdr, sizeof(hdr),
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1438  					"\t\tPending[%d]: ccid:%08x, ",
22b7a426bbe1ebe drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-06-20  1439  					(int)(port - execlists->pending),
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1440  					upper_32_bits(rq->context->lrc_desc));
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1441  			len += print_ring(hdr + len, sizeof(hdr) - len, rq);
606727842d8b167 drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2020-03-31  1442  			scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
e8a70cab253cf4c drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-12-08  1443  			print_request(m, rq, hdr);
f636edb214a5ffd drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-09  1444  		}
fecffa4668cf62e drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-11-11  1445  		rcu_read_unlock();
c36eebd9ba5d70b drivers/gpu/drm/i915/gt/intel_engine_cs.c Chris Wilson           2019-10-09  1446  		execlists_active_unlock_bh(execlists);
a27d5a44ec87a01 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-15  1447  	} else if (INTEL_GEN(dev_priv) > 6) {
a27d5a44ec87a01 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-15  1448  		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1449  			   ENGINE_READ(engine, RING_PP_DIR_BASE));
a27d5a44ec87a01 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-15  1450  		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1451  			   ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
a27d5a44ec87a01 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-15  1452  		drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
baba6e572b38ecd drivers/gpu/drm/i915/intel_engine_cs.c    Daniele Ceraolo Spurio 2019-03-25  1453  			   ENGINE_READ(engine, RING_PP_DIR_DCLV));
a27d5a44ec87a01 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2017-10-15  1454  	}
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1455  }
3ceda3a4a856336 drivers/gpu/drm/i915/intel_engine_cs.c    Chris Wilson           2018-02-12  1456
:::::: The code at line 1428 was first introduced by commit
:::::: 606727842d8b167fecd7cacfda6bded90d93754c drm/i915/gt: Include the execlists CCID of each port in the engine dump
:::::: TO: Chris Wilson chris@chris-wilson.co.uk
:::::: CC: Chris Wilson chris@chris-wilson.co.uk
---
0-DAY CI Kernel Test Service, Intel Corporation
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