When adding support for A64 HDMI PHY in 4.19, we assumed that the two PLL-VIDEOs can both feed the HDMI PHY clock. However experiments show that the mux bit discovered in R40 blob is not applicable on A64. This is not discovered, as normally with a single display pipeline only PLL-VIDEO0 will be used.
In this patchset the second PLL is dropped, and a binding specially for R40 HDMI PHY is added (which seems to have the mux).
PATCH 1 and 2 are dropping second PLL for A64 HDMI PHY, and PATCH 3 to 5 are adding R40 HDMI PHY binding.
This patchset targets v4.19 fixes tree, because the binding is introduced in v4.19, and if we don't fix it there a wrong binding will be left in a stable version released.
Icenowy Zheng (5): dt-bindings: sun4i-drm: drop second PLL from A64 HDMI PHY binding drm: sun4i: drop second PLL from A64 HDMI PHY dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY drm/sun4i: add support for R40 HDMI PHY ARM: sun8i: dts: drop A64 HDMI PHY fallback compatible from R40 DT
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++-- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 5 deletions(-)
By experiments it seems that the A64 HDMI PHY is not able to use the second video PLL as the clock parent.
Drop pll-1 from the device tree binding of A64 HDMI PHY.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 - 1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index f8773ecb7525..62034039cee1 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -114,7 +114,6 @@ Required properties:
H3 and A64 HDMI PHY require additional clocks: - pll-0: parent of phy clock - - pll-1: second possible phy clock parent (A64 only)
TV Encoder ----------
On Fri, Sep 07, 2018 at 03:22:30PM +0800, Icenowy Zheng wrote:
By experiments it seems that the A64 HDMI PHY is not able to use the second video PLL as the clock parent.
Drop pll-1 from the device tree binding of A64 HDMI PHY.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 - 1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index f8773ecb7525..62034039cee1 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -114,7 +114,6 @@ Required properties:
H3 and A64 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- pll-1: second possible phy clock parent (A64 only)
You shouldn't need to do this. The DT is about the hardware. The fact that we haven't figured out how to use it is quite irrelevant, and can change in the future, unlike this binding.
Maxime
The A64 HDMI PHY seems to be not able to use the second video PLL as clock parent in experiments.
Drop the support for the second PLL from A64 HDMI PHY driver.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 82502b351aec..a564b5dfe082 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -398,7 +398,6 @@ static struct regmap_config sun8i_hdmi_phy_regmap_config = {
static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { .has_phy_clk = true, - .has_second_pll = true, .phy_init = &sun8i_hdmi_phy_init_h3, .phy_disable = &sun8i_hdmi_phy_disable_h3, .phy_config = &sun8i_hdmi_phy_config_h3,
The Allwinner R40 HDMI PHY is currently the only one that seems to be able to select between two PLL inputs.
Add a compatible string for it, and the pll-1 clock input definition.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 62034039cee1..a750ff0f068d 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -103,6 +103,7 @@ Required properties: - compatible: value must be one of: * allwinner,sun8i-a83t-hdmi-phy * allwinner,sun8i-h3-hdmi-phy + * allwinner,sun8i-r40-hdmi-phy * allwinner,sun50i-a64-hdmi-phy - reg: base address and size of memory-mapped region - clocks: phandles to the clocks feeding the HDMI PHY @@ -112,8 +113,9 @@ Required properties: - resets: phandle to the reset controller driving the PHY - reset-names: must be "phy"
-H3 and A64 HDMI PHY require additional clocks: +H3, A64 and R40 HDMI PHY require additional clocks: - pll-0: parent of phy clock + - pll-1: second possible phy clock parent (R40 only)
TV Encoder ----------
The R40 SoC has a HDMI PHY that is possible to mux two video PLLs.
Add support for it.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index a564b5dfe082..471993097ced 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -416,6 +416,14 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { .phy_config = &sun8i_hdmi_phy_config_h3, };
+static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { + .has_phy_clk = true, + .has_second_pll = true, + .phy_init = &sun8i_hdmi_phy_init_h3, + .phy_disable = &sun8i_hdmi_phy_disable_h3, + .phy_config = &sun8i_hdmi_phy_config_h3, +}; + static const struct of_device_id sun8i_hdmi_phy_of_table[] = { { .compatible = "allwinner,sun50i-a64-hdmi-phy", @@ -429,6 +437,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = { .compatible = "allwinner,sun8i-h3-hdmi-phy", .data = &sun8i_h3_hdmi_phy, }, + { + .compatible = "allwinner,sun8i-r40-hdmi-phy", + .data = &sun8i_r40_hdmi_phy, + }, { /* sentinel */ } };
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io --- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@ };
hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun8i-r40-hdmi-phy", - "allwinner,sun50i-a64-hdmi-phy"; + compatible = "allwinner,sun8i-r40-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, <&ccu 7>, <&ccu 16>;
On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@ };
hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy","allwinner,sun50i-a64-hdmi-phy";
compatible = "allwinner,sun8i-r40-hdmi-phy";
If you could use the A64 phy before, you can still use it now.
Maxime
Dne ponedeljek, 10. september 2018 ob 16:23:54 CEST je Maxime Ripard napisal(a):
On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@
};hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy","allwinner,sun50i-a64-hdmi-phy";
compatible = "allwinner,sun8i-r40-hdmi-phy";If you could use the A64 phy before, you can still use it now.
Not exactly. Given that we don't know how to switch between HDMI PHY clock parents on A64 (if it is actually connected at all, there is no information about that in manual and AW didn't answered our questions, despite asking them through different channels), A64 compatible will be associated with quirk, which will tell that only one clock parent is usable.
However, R40 HDMI PHY has definetly two clock parents, as it was tested by me and Icenowy and we know how to switch between them without issues. Technically, we could have A64 compatible there, but that would mean only single PHY parent is considered instead of two.
Best regards, Jernej
On Mon, Sep 10, 2018 at 04:32:30PM +0200, Jernej Škrabec wrote:
Dne ponedeljek, 10. september 2018 ob 16:23:54 CEST je Maxime Ripard napisal(a):
On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@
};hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy","allwinner,sun50i-a64-hdmi-phy";
compatible = "allwinner,sun8i-r40-hdmi-phy";If you could use the A64 phy before, you can still use it now.
Not exactly. Given that we don't know how to switch between HDMI PHY clock parents on A64 (if it is actually connected at all, there is no information about that in manual and AW didn't answered our questions, despite asking them through different channels), A64 compatible will be associated with quirk, which will tell that only one clock parent is usable.
However, R40 HDMI PHY has definetly two clock parents, as it was tested by me and Icenowy and we know how to switch between them without issues. Technically, we could have A64 compatible there, but that would mean only single PHY parent is considered instead of two.
The DT change above would mean that you can't operate the R40 phy in the same way than the A64's. From what you're telling me now, this isn't exactly what is going on: you can operate the R40 phy just like the A64: with a single PLL instead of two. You operate in a degraded and non-optimal mode, but it still works.
And it's exactly what the DT is already saying.
Maxime
在 2018-09-17一的 16:54 +0200，Maxime Ripard写道：
On Mon, Sep 10, 2018 at 04:32:30PM +0200, Jernej Škrabec wrote:
Dne ponedeljek, 10. september 2018 ob 16:23:54 CEST je Maxime Ripard napisal(a):
On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@
};hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy",
"allwinner,sun50i-a64-hdmi-phy";
compatible = "allwinner,sun8i-r40-hdmi-phy";
If you could use the A64 phy before, you can still use it now.
Not exactly. Given that we don't know how to switch between HDMI PHY clock parents on A64 (if it is actually connected at all, there is no information about that in manual and AW didn't answered our questions, despite asking them through different channels), A64 compatible will be associated with quirk, which will tell that only one clock parent is usable.
However, R40 HDMI PHY has definetly two clock parents, as it was tested by me and Icenowy and we know how to switch between them without issues. Technically, we could have A64 compatible there, but that would mean only single PHY parent is considered instead of two.
The DT change above would mean that you can't operate the R40 phy in the same way than the A64's. From what you're telling me now, this isn't exactly what is going on: you can operate the R40 phy just like the A64: with a single PLL instead of two. You operate in a degraded and non-optimal mode, but it still works.
The status of R40 HDMI PHY input mux is not determined when use A64 driver, which makes it not working when the bootloader initializes it to use the second PLL (the A64 driver will assume the parent is the first PLL).
And it's exactly what the DT is already saying.
Maxime
On Tue, Sep 18, 2018 at 6:57 AM Icenowy Zheng icenowy@aosc.io wrote:
在 2018-09-17一的 16:54 +0200，Maxime Ripard写道：
On Mon, Sep 10, 2018 at 04:32:30PM +0200, Jernej Škrabec wrote:
Dne ponedeljek, 10. september 2018 ob 16:23:54 CEST je Maxime Ripard napisal(a):
On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
The R40 HDMI PHY seems to be different to the A64 one, the A64 one has no input mux, but the R40 one has.
Drop the A64 fallback compatible from the HDMI PHY node in R40 DT.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index ffd9f00f74a4..5f547c161baf 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -800,8 +800,7 @@
}; hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy",
"allwinner,sun50i-a64-hdmi-phy";
compatible = "allwinner,sun8i-r40-hdmi-phy";
If you could use the A64 phy before, you can still use it now.
Not exactly. Given that we don't know how to switch between HDMI PHY clock parents on A64 (if it is actually connected at all, there is no information about that in manual and AW didn't answered our questions, despite asking them through different channels), A64 compatible will be associated with quirk, which will tell that only one clock parent is usable.
However, R40 HDMI PHY has definetly two clock parents, as it was tested by me and Icenowy and we know how to switch between them without issues. Technically, we could have A64 compatible there, but that would mean only single PHY parent is considered instead of two.
The DT change above would mean that you can't operate the R40 phy in the same way than the A64's. From what you're telling me now, this isn't exactly what is going on: you can operate the R40 phy just like the A64: with a single PLL instead of two. You operate in a degraded and non-optimal mode, but it still works.
I suppose it's a slightly different semantic. While we have no definite data regarding the A64, there are some possibilities:
1. The muxing mechanism isn't present on the A64, and the HDMI PHY only takes one clock.
2. The muxing is present, but only the first parent is connected. Switching to the second input causes it to stop working.
3. Same as above, but both parents are connected to video0-pll. This might be indistinguishable from 1., even if checking whether the bit modifications stick or not.
In any case, I think this deserves proper experimentation, and subsequent documentation in the bindings of our "assumptions" (i.e. educated guess) about what the hardware is doing.
The status of R40 HDMI PHY input mux is not determined when use A64 driver, which makes it not working when the bootloader initializes it to use the second PLL (the A64 driver will assume the parent is the first PLL).
That doesn't sound good. But it really depends on what we assume the A64 is doing.
ChenYu
And it's exactly what the DT is already saying.
Maxime
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On Fri, Sep 7, 2018 at 3:22 PM Icenowy Zheng icenowy@aosc.io wrote:
When adding support for A64 HDMI PHY in 4.19, we assumed that the two PLL-VIDEOs can both feed the HDMI PHY clock. However experiments show that the mux bit discovered in R40 blob is not applicable on A64. This is not discovered, as normally with a single display pipeline only PLL-VIDEO0 will be used.
In this patchset the second PLL is dropped, and a binding specially for R40 HDMI PHY is added (which seems to have the mux).
PATCH 1 and 2 are dropping second PLL for A64 HDMI PHY, and PATCH 3 to 5 are adding R40 HDMI PHY binding.
This patchset targets v4.19 fixes tree, because the binding is introduced in v4.19, and if we don't fix it there a wrong binding will be left in a stable version released.
Please add fixes tags.
The patches look good, though I'm not sure about patches 3 and 4 going in fixes.
ChenYu
Icenowy Zheng (5): dt-bindings: sun4i-drm: drop second PLL from A64 HDMI PHY binding drm: sun4i: drop second PLL from A64 HDMI PHY dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY drm/sun4i: add support for R40 HDMI PHY ARM: sun8i: dts: drop A64 HDMI PHY fallback compatible from R40 DT
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++-- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +-- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 5 deletions(-)
-- 2.18.0
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dri-devel@lists.freedesktop.org
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Maxime Ripard