Add this series to present MediaTek display binding for MT8195. The reason I send this series is Jason and Nancy's binding patches are never received by devicetree mail server. Therefore, I help them to resend binding patches.
All of these patches are reviewed in other series: [1]: message id: 20220415083911.5186-1-jason-jh.lin@mediatek.com [2]: message id: 20220416020749.29010-1-nancy.lin@mediatek.com
This series depends on Yong's MT8195 IOMMU series: [3]: message id: 20220407075726.17771-2-yong.wu@mediatek.com Without this patch, some patches of this series will build failed.
Nancy.Lin (3): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit dt-bindings: mediatek: add ethdr definition for mt8195
jason-jh.lin (2): dt-bindings: arm: mediatek: mmsys: add power and gce properties dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 32 ++++ .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ .../display/mediatek/mediatek,mdp-rdma.yaml | 86 ++++++++++ include/dt-bindings/reset/mt8195-resets.h | 12 ++ 4 files changed, 288 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
From: "jason-jh.lin" jason-jh.lin@mediatek.com
Power: 1. Add description for power-domains property.
GCE: 1. Add description for mboxes property. 2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: CK Hu ck.hu@mediatek.com --- .../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index b31d90dc9eb4..6c2c3edcd443 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -41,6 +41,30 @@ properties: reg: maxItems: 1
+ power-domains: + description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mboxes: + description: + Using mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. See + Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details. + $ref: /schemas/types.yaml#/definitions/phandle-array + + mediatek,gce-client-reg: + description: + The register of client driver can be configured by gce with 4 arguments + defined in this property, such as phandle of gce, subsys id, + register offset and size. + Each subsys id is mapping to a base address of display function blocks + register which is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + "#clock-cells": const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples: - | + #include <dt-bindings/power/mt8173-power.h> + #include <dt-bindings/gce/mt8173-gce.h> + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; };
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "jason-jh.lin" jason-jh.lin@mediatek.com
Power:
- Add description for power-domains property.
GCE:
- Add description for mboxes property.
- Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: CK Hu ck.hu@mediatek.com
Applied, thanks.
Matthias
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index b31d90dc9eb4..6c2c3edcd443 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -41,6 +41,30 @@ properties: reg: maxItems: 1
- power-domains:
- description:
A phandle and PM domain specifier as defined by bindingsof the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yaml for details.- mboxes:
- description:
Using mailbox to communicate with GCE, it should have thisproperty and list of phandle, mailbox specifiers. SeeDocumentation/devicetree/bindings/mailbox/mtk-gce.txt for details.- $ref: /schemas/types.yaml#/definitions/phandle-array
- mediatek,gce-client-reg:
- description:
The register of client driver can be configured by gce with 4 argumentsdefined in this property, such as phandle of gce, subsys id,register offset and size.Each subsys id is mapping to a base address of display function blocksregister which is defined in the gce headerinclude/dt-bindings/gce/<chip>-gce.h.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
- "#clock-cells": const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples: - |
- #include <dt-bindings/power/mt8173-power.h>
- #include <dt-bindings/gce/mt8173-gce.h>
mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>;power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>;mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,<&gce 1 CMDQ_THR_PRIO_HIGHEST>;mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; };
On Tue, Apr 19, 2022 at 11:32:33AM +0800, Rex-BC Chen wrote:
From: "jason-jh.lin" jason-jh.lin@mediatek.com
Power:
- Add description for power-domains property.
GCE:
- Add description for mboxes property.
- Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: CK Hu ck.hu@mediatek.com
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index b31d90dc9eb4..6c2c3edcd443 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -41,6 +41,30 @@ properties: reg: maxItems: 1
- power-domains:
How many and what are they.
- description:
A phandle and PM domain specifier as defined by bindingsof the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yaml for details.
Drop. Don't need generic descriptions of common properties.
- mboxes:
How many?
- description:
Using mailbox to communicate with GCE, it should have this
If using?
property and list of phandle, mailbox specifiers. SeeDocumentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
Drop
- $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type.
- mediatek,gce-client-reg:
- description:
The register of client driver can be configured by gce with 4 argumentsdefined in this property, such as phandle of gce, subsys id,register offset and size.Each subsys id is mapping to a base address of display function blocksregister which is defined in the gce headerinclude/dt-bindings/gce/<chip>-gce.h.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
This needs to define exact sizes.
items: - items: - description: phandle to GCE - description: subsy id - description: register offset - description: register size
- "#clock-cells": const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/power/mt8173-power.h>
- #include <dt-bindings/gce/mt8173-gce.h>
- mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>;mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,<&gce 1 CMDQ_THR_PRIO_HIGHEST>;mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;-- 2.18.0
Hi Rob,
Thanks for the reviews. Since this patch has already applied in:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commi...
I'll send a fixup-patch for your commnet.
On Tue, 2022-04-26 at 13:31 -0500, Rob Herring wrote:
On Tue, Apr 19, 2022 at 11:32:33AM +0800, Rex-BC Chen wrote:
From: "jason-jh.lin" jason-jh.lin@mediatek.com
Power:
- Add description for power-domains property.
GCE:
- Add description for mboxes property.
- Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu ck.hu@mediatek.com
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam l b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam l index b31d90dc9eb4..6c2c3edcd443 100644
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam l +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam l @@ -41,6 +41,30 @@ properties: reg: maxItems: 1
- power-domains:
How many and what are they.
maxItems: 1 description: Each mmsys belongs to a power-domains, so we can add the power- domains property to make it clearer, and also bind to the power controller.
- description:
A phandle and PM domain specifier as defined by bindingsof the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yamlfor details.
Drop. Don't need generic descriptions of common properties.
OK, I'll drop this.
- mboxes:
How many?
minItems: 1
- description:
Using mailbox to communicate with GCE, it should have thisIf using?
description: If using mailbox to communicate with GCE, it should have this property. GCE will help configure the hardware settings for the current mmsys data pipeline.
property and list of phandle, mailbox specifiers. SeeDocumentation/devicetree/bindings/mailbox/mtk-gce.txt fordetails.
Drop
OK, I'll drop this.
- $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type.
OK, I'll drop this.
- mediatek,gce-client-reg:
- description:
The register of client driver can be configured by gce with4 arguments
defined in this property, such as phandle of gce, subsys id,register offset and size.Each subsys id is mapping to a base address of displayfunction blocks
register which is defined in the gce headerinclude/dt-bindings/gce/<chip>-gce.h.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
This needs to define exact sizes.
items:
- items:
- description: phandle to GCE
- description: subsy id
- description: register offset
- description: register size
OK, I'll fix it like this:
mediatek,gce-client-reg: minItems: 1 items: - items: - description: phandle to GCE - description: subsys id - description: register offset - description: register size
Regards, Jason-JH.Lin
- "#clock-cells": const: 1
@@ -56,9 +80,16 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/power/mt8173-power.h>
- #include <dt-bindings/gce/mt8173-gce.h>
- mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>; #clock-cells = <1>; #reset-cells = <1>;mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,<&gce 1 CMDQ_THR_PRIO_HIGHEST>;mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;-- 2.18.0
From: "jason-jh.lin" jason-jh.lin@mediatek.com
In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as vdosys0, vdosys1, vppsys0 and vppsys1. Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own mmio base address, they could be identified by their different address during probe time.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 6c2c3edcd443..6ad023eec193 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys + - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items:
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "jason-jh.lin" jason-jh.lin@mediatek.com
In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as vdosys0, vdosys1, vppsys0 and vppsys1. Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own mmio base address, they could be identified by their different address during probe time.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
Applied, thanks
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 6c2c3edcd443..6ad023eec193 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys
- mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon - items:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com --- .../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MDP RDMA + +maintainers: + - Matthias Brugger matthias.bgg@gmail.com + +description: | + The mediatek MDP RDMA stands for Read Direct Memory Access. + It provides real time data to the back-end panel driver, such as DSI, + DPI and DP_INTF. + It contains one line buffer to store the sufficient pixel data. + RDMA device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt8195-vdo1-rdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + clocks: + items: + - description: RDMA Clock + + iommus: + description: + This property should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + #include <dt-bindings/gce/mt8195-gce.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + vdo1_rdma0: mdp-rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + };
On Tue, 19 Apr 2022 11:32:35 +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.example.dts:27:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory 27 | #include <dt-bindings/memory/mt8195-memory-port.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, 2022-04-19 at 20:12 +0800, Rob Herring wrote:
On Tue, 19 Apr 2022 11:32:35 +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml: $id: relative path/filename doesn't match actual path or filename expected: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/m...
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.example.dts:27:18: fatal error: dt-bindings/memory/mt8195- memory-port.h: No such file or directory 27 | #include <dt-bindings/memory/mt8195-memory-port.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/__;!!CTRNKA9w...
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hello Rob,
As mentioned in cover letter, this patch is basd on Yong's patch: message id: 20220407075726.17771-2-yong.wu@mediatek.com Without this patch, some patches of this series will build failed.
For Yong's series, I think it's just waiting for accepted by maintainers. Moreover, we really need your suggestion and even approvement for these display binding patches.
Thanks for your big support!
BRs, Rex
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek MDP RDMA
+maintainers:
- Matthias Brugger matthias.bgg@gmail.com
I don't think I would be the correct person to maintain this. This should be the person that is maintaining the driver.
Regards, Matthias
+description: |
- The mediatek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+properties:
- compatible:
- oneOf:
- items:- const: mediatek,mt8195-vdo1-rdma- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yaml for details.- clocks:
- items:
- description: RDMA Clock- iommus:
- description:
This property should point to the respective IOMMU block with master port as argument,see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.- mediatek,gce-client-reg:
- description:
The register of display function block to be set by gce. There are 4 arguments,such as gce node, subsys id, offset and register size. The subsys id that ismapping to the register of display function blocks is defined in the gce headerinclude/include/dt-bindings/gce/<chip>-gce.h of each chips.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+required:
- compatible
- reg
- power-domains
- clocks
- iommus
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- soc {
#address-cells = <2>;#size-cells = <2>;vdo1_rdma0: mdp-rdma@1c104000 {compatible = "mediatek,mt8195-vdo1-rdma";reg = <0 0x1c104000 0 0x1000>;interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;};- };
Matthias Brugger matthias.bgg@gmail.com 於 2022年4月19日 週二 下午10:57寫道：
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek MDP RDMA
+maintainers:
- Matthias Brugger matthias.bgg@gmail.com
I don't think I would be the correct person to maintain this. This should be the person that is maintaining the driver.
Agree. This should be
Chun-Kuang Hu chunkuang.hu@kernel.org Philipp Zabel p.zabel@pengutronix.de
Regards, Chun-Kuang.
Regards, Matthias
+description: |
- The mediatek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+properties:
- compatible:
- oneOf:
- items:- const: mediatek,mt8195-vdo1-rdma- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yaml for details.- clocks:
- items:
- description: RDMA Clock- iommus:
- description:
This property should point to the respective IOMMU block with master port as argument,see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.- mediatek,gce-client-reg:
- description:
The register of display function block to be set by gce. There are 4 arguments,such as gce node, subsys id, offset and register size. The subsys id that ismapping to the register of display function blocks is defined in the gce headerinclude/include/dt-bindings/gce/<chip>-gce.h of each chips.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+required:
- compatible
- reg
- power-domains
- clocks
- iommus
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- soc {
#address-cells = <2>;#size-cells = <2>;vdo1_rdma0: mdp-rdma@1c104000 {compatible = "mediatek,mt8195-vdo1-rdma";reg = <0 0x1c104000 0 0x1000>;interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;};- };
On Tue, 2022-04-19 at 23:51 +0800, Chun-Kuang Hu wrote:
Matthias Brugger matthias.bgg@gmail.com 於 2022年4月19日 週二 下午10:57寫道：
On 19/04/2022 05:32, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp -rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp -rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp -rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/media...
+$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...
+title: MediaTek MDP RDMA
+maintainers:
- Matthias Brugger matthias.bgg@gmail.com
I don't think I would be the correct person to maintain this. This should be the person that is maintaining the driver.
Agree. This should be
Chun-Kuang Hu chunkuang.hu@kernel.org Philipp Zabel p.zabel@pengutronix.de
Regards, Chun-Kuang.
Regards, Matthias
Hello Chun-Kuang and Matthias,
OK, I will update the list in next version.
BRs, Rex
+description: |
- The mediatek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such
as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel
data.
- RDMA device node must be siblings to the central MMSYS_CONFIG
node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.
yaml for details.
+properties:
- compatible:
- oneOf:
- items:- const: mediatek,mt8195-vdo1-rdma- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by
bindings of
the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yamlfor details.
- clocks:
- items:
- description: RDMA Clock- iommus:
- description:
This property should point to the respective IOMMU blockwith master port as argument,
seeDocumentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
- mediatek,gce-client-reg:
- description:
The register of display function block to be set by gce.There are 4 arguments,
such as gce node, subsys id, offset and register size. Thesubsys id that is
mapping to the register of display function blocks isdefined in the gce header
include/include/dt-bindings/gce/<chip>-gce.h of eachchips.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+required:
- compatible
- reg
- power-domains
- clocks
- iommus
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- soc {
#address-cells = <2>;#size-cells = <2>;vdo1_rdma0: mdp-rdma@1c104000 {compatible = "mediatek,mt8195-vdo1-rdma";reg = <0 0x1c104000 0 0x1000>;interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX0x4000 0x1000>;
};- };
On Tue, Apr 19, 2022 at 11:32:35AM +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
How does this compare to the mediatek,mt8183-mdp3-rdma or mediatek,mt8195-disp-rdma?
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek MDP RDMA
+maintainers:
- Matthias Brugger matthias.bgg@gmail.com
+description: |
- The mediatek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+properties:
- compatible:
- oneOf:
- items:- const: mediatek,mt8195-vdo1-rdma- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yaml for details.- clocks:
- items:
- description: RDMA Clock- iommus:
- description:
This property should point to the respective IOMMU block with master port as argument,see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.- mediatek,gce-client-reg:
- description:
The register of display function block to be set by gce. There are 4 arguments,such as gce node, subsys id, offset and register size. The subsys id that ismapping to the register of display function blocks is defined in the gce headerinclude/include/dt-bindings/gce/<chip>-gce.h of each chips.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+required:
- compatible
- reg
- power-domains
- clocks
- iommus
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- soc {
#address-cells = <2>;#size-cells = <2>;vdo1_rdma0: mdp-rdma@1c104000 {compatible = "mediatek,mt8195-vdo1-rdma";reg = <0 0x1c104000 0 0x1000>;interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;};- };
-- 2.18.0
Hi Rob,
Thanks for the review.
On Tue, 2022-04-26 at 15:25 -0500, Rob Herring wrote:
On Tue, Apr 19, 2022 at 11:32:35AM +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 RDMA definition.
How does this compare to the mediatek,mt8183-mdp3-rdma or mediatek,mt8195-disp-rdma?
1. The mediatek,mt8195-vdo1-rdma is a completely different HW engine with mediatek,mt8195-disp-rdma. 2. The mediatek,mt8195-vdo1-rdma is similar to mt8183-mdp3-rdma but with different compression support and tile size.
Regards, Nancy
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
.../display/mediatek/mediatek,mdp-rdma.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml new file mode 100644 index 000000000000..6ab773569462 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- rdma.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/media...
+$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...
+title: MediaTek MDP RDMA
+maintainers:
- Matthias Brugger matthias.bgg@gmail.com
+description: |
- The mediatek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as
DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG
node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya
ml for details.
+properties:
- compatible:
- oneOf:
- items:- const: mediatek,mt8195-vdo1-rdma- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by
bindings of
the power controller specified by phandle. SeeDocumentation/devicetree/bindings/power/power-domain.yamlfor details.
- clocks:
- items:
- description: RDMA Clock- iommus:
- description:
This property should point to the respective IOMMU blockwith master port as argument,
seeDocumentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
- mediatek,gce-client-reg:
- description:
The register of display function block to be set by gce.There are 4 arguments,
such as gce node, subsys id, offset and register size. Thesubsys id that is
mapping to the register of display function blocks isdefined in the gce header
include/include/dt-bindings/gce/<chip>-gce.h of each chips.- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+required:
- compatible
- reg
- power-domains
- clocks
- iommus
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- soc {
#address-cells = <2>;#size-cells = <2>;vdo1_rdma0: mdp-rdma@1c104000 {compatible = "mediatek,mt8195-vdo1-rdma";reg = <0 0x1c104000 0 0x1000>;interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX0x4000 0x1000>;
};- };
-- 2.18.0
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com --- include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..aab8d74496a6 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */ +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com --- .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml new file mode 100644 index 000000000000..e8303c28a361 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Ethdr Device Tree Bindings + +maintainers: + - Chun-Kuang Hu chunkuang.hu@kernel.org + - Philipp Zabel p.zabel@pengutronix.de + +description: | + ETHDR is designed for HDR video and graphics conversion in the external display path. + It handles multiple HDR input types and performs tone mapping, color space/color + format conversion, and then combine different layers, output the required HDR or + SDR signal to the subsequent display path. This engine is composed of two video + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed + registers from DRAM and set them to HW in the v-blanking period. + +properties: + compatible: + items: + - const: mediatek,mt8195-disp-ethdr + reg: + maxItems: 7 + reg-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + interrupts: + minItems: 1 + iommus: + description: The compatible property is DMA function blocks. + Should point to the respective IOMMU block with master port as argument, + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for + details. + minItems: 1 + maxItems: 2 + clocks: + items: + - description: mixer clock + - description: video frontend 0 clock + - description: video frontend 1 clock + - description: graphic frontend 0 clock + - description: graphic frontend 1 clock + - description: video backend clock + - description: autodownload and menuload clock + - description: video frontend 0 async clock + - description: video frontend 1 async clock + - description: graphic frontend 0 async clock + - description: graphic frontend 1 async clock + - description: video backend async clock + - description: ethdr top clock + clock-names: + items: + - const: mixer + - const: vdo_fe0 + - const: vdo_fe1 + - const: gfx_fe0 + - const: gfx_fe1 + - const: vdo_be + - const: adl_ds + - const: vdo_fe0_async + - const: vdo_fe1_async + - const: gfx_fe0_async + - const: gfx_fe1_async + - const: vdo_be_async + - const: ethdr_top + power-domains: + maxItems: 1 + resets: + maxItems: 5 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: The register of display function block to be set by gce. + There are 4 arguments in this property, gce node, subsys id, offset and + register size. The subsys id is defined in the gce header of each chips + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of + display function block. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/power/mt8195-power.h> + #include <dt-bindings/reset/mt8195-resets.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11b000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + }; + }; + +...
On Tue, 19 Apr 2022 11:32:37 +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:26:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory 26 | #include <dt-bindings/memory/mt8195-memory-port.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, 2022-04-19 at 20:12 +0800, Rob Herring wrote:
On Tue, 19 Apr 2022 11:32:37 +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
.../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y aml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa mple.dts:26:18: fatal error: dt-bindings/memory/mt8195-memory-port.h: No such file or directory 26 | #include <dt-bindings/memory/mt8195-memory-port.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa mple.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/__;!!CTRNKA9w...
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hello Rob,
As mentioned in [3/5], this patch is also basd on Yong's patch: message id: 20220407075726.17771-2-yong.wu@mediatek.com Without this patch, some patches of this series will build failed.
Thanks!
BRs, Rex
On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
.../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml new file mode 100644 index 000000000000..e8303c28a361 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek Ethdr Device Tree Bindings
+maintainers:
- Chun-Kuang Hu chunkuang.hu@kernel.org
- Philipp Zabel p.zabel@pengutronix.de
+description: |
No need for '|' unless you have formatting to preserve.
- ETHDR is designed for HDR video and graphics conversion in the external display path.
- It handles multiple HDR input types and performs tone mapping, color space/color
- format conversion, and then combine different layers, output the required HDR or
- SDR signal to the subsequent display path. This engine is composed of two video
- frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
- DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
- registers from DRAM and set them to HW in the v-blanking period.
+properties:
- compatible:
- items:
- const: mediatek,mt8195-disp-ethdr
blank line between DT properties.
- reg:
- maxItems: 7
- reg-names:
- items:
- const: mixer- const: vdo_fe0- const: vdo_fe1- const: gfx_fe0- const: gfx_fe1- const: vdo_be- const: adl_ds- interrupts:
- minItems: 1
maxItems: 1
- iommus:
- description: The compatible property is DMA function blocks.
Should point to the respective IOMMU block with master port as argument,see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml fordetails.- minItems: 1
- maxItems: 2
- clocks:
- items:
- description: mixer clock- description: video frontend 0 clock- description: video frontend 1 clock- description: graphic frontend 0 clock- description: graphic frontend 1 clock- description: video backend clock- description: autodownload and menuload clock- description: video frontend 0 async clock- description: video frontend 1 async clock- description: graphic frontend 0 async clock- description: graphic frontend 1 async clock- description: video backend async clock- description: ethdr top clock- clock-names:
- items:
- const: mixer- const: vdo_fe0- const: vdo_fe1- const: gfx_fe0- const: gfx_fe1- const: vdo_be- const: adl_ds- const: vdo_fe0_async- const: vdo_fe1_async- const: gfx_fe0_async- const: gfx_fe1_async- const: vdo_be_async- const: ethdr_top- power-domains:
- maxItems: 1
- resets:
- maxItems: 5
Need to define what they are and order.
- mediatek,gce-client-reg:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: The register of display function block to be set by gce.
There are 4 arguments in this property, gce node, subsys id, offset andregister size. The subsys id is defined in the gce header of each chipsinclude/include/dt-bindings/gce/<chip>-gce.h, mapping to the register ofdisplay function block.
Need to define each cell:
minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ...
Seems odd this property is optional...
+required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- power-domains
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/reset/mt8195-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;disp_ethdr@1c114000 {compatible = "mediatek,mt8195-disp-ethdr";reg = <0 0x1c114000 0 0x1000>,<0 0x1c115000 0 0x1000>,<0 0x1c117000 0 0x1000>,<0 0x1c119000 0 0x1000>,<0 0x1c11a000 0 0x1000>,<0 0x1c11b000 0 0x1000>,<0 0x1c11b000 0 0x1000>;reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1","vdo_be", "adl_ds";mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,<&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,<&vdosys1 CLK_VDO1_HDR_VDO_BE>,<&vdosys1 CLK_VDO1_26M_SLOW>,<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,<&topckgen CLK_TOP_ETHDR>;clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1","vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async","gfx_fe0_async", "gfx_fe1_async","vdo_be_async","ethdr_top";power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,<&iommu_vpp M4U_PORT_L3_HDR_ADL>;interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;};- };
+...
2.18.0
Hi Rob,
Thanks for the review.
On Mon, 2022-04-25 at 11:34 -0500, Rob Herring wrote:
On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote:
From: "Nancy.Lin" nancy.lin@mediatek.com
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
.../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y aml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml new file mode 100644 index 000000000000..e8303c28a361 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/m...
+$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...
+title: MediaTek Ethdr Device Tree Bindings
+maintainers:
- Chun-Kuang Hu chunkuang.hu@kernel.org
- Philipp Zabel p.zabel@pengutronix.de
+description: |
No need for '|' unless you have formatting to preserve.
OK, I will remove it.
- ETHDR is designed for HDR video and graphics conversion in the
external display path.
- It handles multiple HDR input types and performs tone mapping,
color space/color
- format conversion, and then combine different layers, output the
required HDR or
- SDR signal to the subsequent display path. This engine is
composed of two video
- frontends, two graphic frontends, one video backend and a mixer.
ETHDR has two
- DMA function blocks, DS and ADL. These two function blocks read
the pre-programmed
- registers from DRAM and set them to HW in the v-blanking period.
+properties:
- compatible:
- items:
- const: mediatek,mt8195-disp-ethdrblank line between DT properties.
OK, I will add blank line between DT properties.
- reg:
- maxItems: 7
- reg-names:
- items:
- const: mixer- const: vdo_fe0- const: vdo_fe1- const: gfx_fe0- const: gfx_fe1- const: vdo_be- const: adl_ds- interrupts:
- minItems: 1
maxItems: 1
OK, I will fix it.
- iommus:
- description: The compatible property is DMA function blocks.
Should point to the respective IOMMU block with master portas argument,
seeDocumentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
details.- minItems: 1
- maxItems: 2
- clocks:
- items:
- description: mixer clock- description: video frontend 0 clock- description: video frontend 1 clock- description: graphic frontend 0 clock- description: graphic frontend 1 clock- description: video backend clock- description: autodownload and menuload clock- description: video frontend 0 async clock- description: video frontend 1 async clock- description: graphic frontend 0 async clock- description: graphic frontend 1 async clock- description: video backend async clock- description: ethdr top clock- clock-names:
- items:
- const: mixer- const: vdo_fe0- const: vdo_fe1- const: gfx_fe0- const: gfx_fe1- const: vdo_be- const: adl_ds- const: vdo_fe0_async- const: vdo_fe1_async- const: gfx_fe0_async- const: gfx_fe1_async- const: vdo_be_async- const: ethdr_top- power-domains:
- maxItems: 1
- resets:
- maxItems: 5
Need to define what they are and order.
OK. I will fix it in the next revision.
- mediatek,gce-client-reg:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: The register of display function block to be set
by gce.
There are 4 arguments in this property, gce node, subsys id,offset and
register size. The subsys id is defined in the gce header ofeach chips
include/include/dt-bindings/gce/<chip>-gce.h, mapping to theregister of
display function block.Need to define each cell:
minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ...
Seems odd this property is optional...
Yes, I miss the required properties, will fix them.
Since my email server spam problem is fixed. I will send these binding patches in my vdosys1 series [1]. (The fixes will be in the next revision v18)
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=632713
Regards, Nancy
+required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- power-domains
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/reset/mt8195-resets.h>
- soc {
#address-cells = <2>;#size-cells = <2>;disp_ethdr@1c114000 {compatible = "mediatek,mt8195-disp-ethdr";reg = <0 0x1c114000 0 0x1000>,<0 0x1c115000 0 0x1000>,<0 0x1c117000 0 0x1000>,<0 0x1c119000 0 0x1000>,<0 0x1c11a000 0 0x1000>,<0 0x1c11b000 0 0x1000>,<0 0x1c11b000 0 0x1000>;reg-names = "mixer", "vdo_fe0", "vdo_fe1","gfx_fe0", "gfx_fe1",
"vdo_be", "adl_ds";mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX0x4000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0x5000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0x7000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0x9000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0xa000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0xb000 0x1000>,
<&gce0 SUBSYS_1c11XXXX0xc000 0x1000>;
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,<&vdosys1 CLK_VDO1_HDR_VDO_BE>,<&vdosys1 CLK_VDO1_26M_SLOW>,<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,<&topckgen CLK_TOP_ETHDR>;clock-names = "mixer", "vdo_fe0", "vdo_fe1","gfx_fe0", "gfx_fe1",
"vdo_be", "adl_ds", "vdo_fe0_async","vdo_fe1_async",
"gfx_fe0_async","gfx_fe1_async","vdo_be_async",
"ethdr_top";power-domains = <&spmMT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,<&iommu_vpp M4U_PORT_L3_HDR_ADL>;interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>;/* disp mixer */
resets = <&vdosys1MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
<&vdosys1MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
<&vdosys1MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
<&vdosys1MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
<&vdosys1MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};- };
+...
2.18.0
dri-devel@lists.freedesktop.org
-
Chun-Kuang Hu -
Jason-JH Lin -
Matthias Brugger -
Nancy.Lin -
Rex-BC Chen -
Rob Herring