Changes since v6: - Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned. - Config the "hs_packet_end_aligned" in ANX7725 .attach().
Changes since v5: - Search the anx7625 compatible as flag to control dsi output aligned.
Changes since v4: - Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before "drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".
- Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".
Jitao Shi (3): drm/dsi: transer dsi hs packet aligned drm/mediatek: implment the dsi hs packets aligned drm/bridge: anx7625: config hs packets end aligned to avoid screen shift
drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ include/drm/drm_mipi_dsi.h | 2 ++ 3 files changed, 13 insertions(+)
Some DSI devices reqire the hs packet starting and ending at same time on all dsi lanes. So use a flag to those devices.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index af7ba8071eb0..8e8563792682 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,7 @@ struct mipi_dsi_device_info { * @lp_rate: maximum lane frequency for low power mode in hertz, this should * be set to the real limits of the hardware, zero is only accepted for * legacy drivers + * @hs_packet_end_aligned: transfer dsi hs packet ending aligned */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +190,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate; + bool hs_packet_end_aligned; };
#define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年9月16日 週四 上午6:31寫道：
Some DSI devices reqire the hs packet starting and ending at same time on all dsi lanes. So use a flag to those devices.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index af7ba8071eb0..8e8563792682 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
- @lp_rate: maximum lane frequency for low power mode in hertz, this should
- be set to the real limits of the hardware, zero is only accepted for
- legacy drivers
*/
- @hs_packet_end_aligned: transfer dsi hs packet ending aligned
struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +190,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate;
bool hs_packet_end_aligned;};
#define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
2.25.1
Hi sirs
Pls help to review this change.
Best Regards Jitao.
On Tue, 2021-10-05 at 07:53 +0800, Chun-Kuang Hu wrote:
Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年9月16日 週四 上午6:31寫道：
Some DSI devices reqire the hs packet starting and ending at same time on all dsi lanes. So use a flag to those devices.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index af7ba8071eb0..8e8563792682 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
- @lp_rate: maximum lane frequency for low power mode in hertz,
this should
- be set to the real limits of the hardware, zero is only
accepted for
- legacy drivers
*/
- @hs_packet_end_aligned: transfer dsi hs packet ending aligned
struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +190,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate;
bool hs_packet_end_aligned;};
#define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
2.25.1
Hi, Dave & Daniel:
This patch looks good to me, how do you think about it?
Regards, Chun-Kuang.
Jitao Shi jitao.shi@mediatek.com 於 2021年11月4日 週四 上午11:36寫道：
Hi sirs
Pls help to review this change.
Best Regards Jitao.
On Tue, 2021-10-05 at 07:53 +0800, Chun-Kuang Hu wrote:
Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年9月16日 週四 上午6:31寫道：
Some DSI devices reqire the hs packet starting and ending at same time on all dsi lanes. So use a flag to those devices.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
include/drm/drm_mipi_dsi.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index af7ba8071eb0..8e8563792682 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
- @lp_rate: maximum lane frequency for low power mode in hertz,
this should
- be set to the real limits of the hardware, zero is only
accepted for
- legacy drivers
*/
- @hs_packet_end_aligned: transfer dsi hs packet ending aligned
struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -189,6 +190,7 @@ struct mipi_dsi_device { unsigned long mode_flags; unsigned long hs_rate; unsigned long lp_rate;
bool hs_packet_end_aligned;};
#define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
2.25.1
Some dsi devices require the packets on lanes aligned at the end, or the screen will shift or scroll.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 93b40c245f00..9d72e6dce0bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk;
u32 data_rate; + /* force dsi line end without dsi_null data */ + bool hs_packet_end_aligned;
unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); }
+ if (dsi->hs_packet_end_aligned) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -793,6 +802,7 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host, dsi->lanes = device->lanes; dsi->format = device->format; dsi->mode_flags = device->mode_flags; + dsi->hs_packet_end_aligned = device->hs_packet_end_aligned;
return 0; }
Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年9月16日 週四 上午6:31寫道：
Some dsi devices require the packets on lanes aligned at the end, or the screen will shift or scroll.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 93b40c245f00..9d72e6dce0bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk;
u32 data_rate;
/* force dsi line end without dsi_null data */bool hs_packet_end_aligned; unsigned long mode_flags; enum mipi_dsi_pixel_format format;@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); }
if (dsi->hs_packet_end_aligned) {horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;}writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);@@ -793,6 +802,7 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host, dsi->lanes = device->lanes; dsi->format = device->format; dsi->mode_flags = device->mode_flags;
dsi->hs_packet_end_aligned = device->hs_packet_end_aligned; return 0;}
2.25.1
This device requires the packets on lanes aligned at the end to fix screen shift or scroll.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 14d73fb1dd15..d76fb63fa9f7 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE; + dsi->hs_packet_end_aligned = true;
if (mipi_dsi_attach(dsi) < 0) { DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
Hi Xin,
Please help to review the changes in anx7625.c
On Thu, 2021-09-16 at 06:31 +0800, Jitao Shi wrote:
This device requires the packets on lanes aligned at the end to fix screen shift or scroll.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 14d73fb1dd15..d76fb63fa9f7 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
dsi->hs_packet_end_aligned = true;
if (mipi_dsi_attach(dsi) < 0) { DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
On Mon, Nov 01, 2021 at 11:16:15AM +0800, Jitao Shi wrote:
Hi Xin,
Please help to review the changes in anx7625.c
On Thu, 2021-09-16 at 06:31 +0800, Jitao Shi wrote:
This device requires the packets on lanes aligned at the end to fix screen shift or scroll.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 14d73fb1dd15..d76fb63fa9f7 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
- dsi->hs_packet_end_aligned = true;
Looks good, it's OK for me. Reviewed-by: Xin Ji xji@analogixsemi.com
if (mipi_dsi_attach(dsi) < 0) { DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
On Tue, 2 Nov 2021 at 02:56, Xin Ji xji@analogixsemi.com wrote:
On Mon, Nov 01, 2021 at 11:16:15AM +0800, Jitao Shi wrote:
Hi Xin,
Please help to review the changes in anx7625.c
On Thu, 2021-09-16 at 06:31 +0800, Jitao Shi wrote:
This device requires the packets on lanes aligned at the end to fix screen shift or scroll.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/bridge/analogix/anx7625.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 14d73fb1dd15..d76fb63fa9f7 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1327,6 +1327,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
- dsi->hs_packet_end_aligned = true;
Looks good, it's OK for me. Reviewed-by: Xin Ji xji@analogixsemi.com
Acked-by: Robert Foss robert.foss@linaro.org
dri-devel@lists.freedesktop.org
-
Chun-Kuang Hu -
Jitao Shi -
Robert Foss -
Xin Ji