This is how a typical display color hardware pipeline looks like: +-------------------------------------------+ | RAM | | +------+ +---------+ +---------+ | | | FB 1 | | FB 2 | | FB N | | | +------+ +---------+ +---------+ | +-------------------------------------------+ | Plane Color Hardware Block | +--------------------------------------------+ | +---v-----+ +---v-------+ +---v------+ | | | Plane A | | Plane B | | Plane N | | | | DeGamma | | Degamma | | Degamma | | | +---+-----+ +---+-------+ +---+------+ | | | | | | | +---v-----+ +---v-------+ +---v------+ | | |Plane A | | Plane B | | Plane N | | | |CSC/CTM | | CSC/CTM | | CSC/CTM | | | +---+-----+ +----+------+ +----+-----+ | | | | | | | +---v-----+ +----v------+ +----v-----+ | | | Plane A | | Plane B | | Plane N | | | | Gamma | | Gamma | | Gamma | | | +---+-----+ +----+------+ +----+-----+ | | | | | | +--------------------------------------------+ +------v--------------v---------------v-------| || || || Pipe Blender || +--------------------+------------------------+ | | | | +-----------v----------+ | | | Pipe DeGamma | | | | | | | +-----------+----------+ | | | Pipe Color | | +-----------v----------+ Hardware | | | Pipe CSC/CTM | | | | | | | +-----------+----------+ | | | | | +-----------v----------+ | | | Pipe Gamma | | | | | | | +-----------+----------+ | | | | +---------------------------------------------+ | v Pipe Output
This patch series adds properties for plane color features. It adds properties for degamma used to linearize data, CSC used for gamut conversion, and gamma used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to another, one color space to another etc.
Usersapce can take smart blending decisions and utilize these hardware supported plane color features to get accurate color profile. The same can help in consistent color quality from source to panel taking advantage of advanced color features in hardware.
These patches just add the property interfaces and enable helper functions.
This series adds Intel Gen9 specific plane gamma feature. We can build up and add other platform/hardware specific implementation on top of this series
Note: This is just to get a design feedback whether these interfaces look ok. Based on community feedback on interfaces, we will implement IGT tests to validate plane color features. This is un-tested currently.
Userspace implementation using these properties have been done in drm hwcomposer by "Alexandru-Cosmin Gheorghe Alexandru-Cosmin.Gheorghe@arm.com" from ARM. A merge request has been opened by Alexandru for drm_hwcomposer, implementing the property changes for the same. Please review that as well: https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/merge_requests/...
v2: Dropped legacy gamma table for plane as suggested by Maarten. Added Gen9/BDW plane gamma feature and rebase on tot.
v3: Added a new drm_color_lut_ext structure to accommodate 32 bit precision entries, pointed to by Brian, Starkey for HDR usecases. Addressed Sean,Paul comments and moved plane color properties to drm_plane instead of mode_config. Added property documentation as suggested by Daniel, Vetter. Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov.
v4: Rebase
v5: Added "Display Color Hardware Pipeline" flow to kernel documentation as suggested by "Ville Syrjala" and "Brian Starkey". Moved the property creation to drm_color_mgmt.c file to consolidate all color operations at one place. Addressed Alexandru's review comments.
v6: Rebase. Added support for ICL Color features. Enhanced Lut precision to accept input values in u32.32 format. This is needed for higher precision required in HDR data processing.
v7: Fixed Lut roundup and extraction function in patch 1 and address definitions for Degamma index in patch 10. Rest of the patches are just rebased.
Uma Shankar (16): drm: Add Enhanced Gamma LUT precision structure drm: Add Plane Degamma properties drm: Add Plane CTM property drm: Add Plane Gamma properties drm: Define helper function for plane color enabling drm/i915: Enable plane color features drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms drm/i915: Load plane color luts from atomic flip drm/i915: Add plane color capabilities drm/i915/icl: Add ICL Plane Degamma Register definition drm/i915/icl: Enable Plane Degamma drm/i915/icl: Add Plane Gamma Register Definitions drm/i915/icl: Implement Plane Gamma drm/i915: Enable Plane Gamma/Degamma drm/i915: Define Plane CSC Registers drm/i915: Enable Plane CSC
Documentation/gpu/drm-kms.rst | 99 +++++++++ drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 12 ++ drivers/gpu/drm/drm_atomic_uapi.c | 29 +++ drivers/gpu/drm/drm_color_mgmt.c | 138 ++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_pci.c | 5 +- drivers/gpu/drm/i915/i915_reg.h | 153 ++++++++++++++ drivers/gpu/drm/i915/intel_atomic_plane.c | 3 + drivers/gpu/drm/i915/intel_color.c | 331 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_device_info.h | 5 + drivers/gpu/drm/i915/intel_display.c | 13 +- drivers/gpu/drm/i915/intel_drv.h | 11 + drivers/gpu/drm/i915/intel_sprite.c | 11 + include/drm/drm_color_mgmt.h | 6 + include/drm/drm_plane.h | 61 ++++++ include/uapi/drm/drm_mode.h | 15 ++ 17 files changed, 894 insertions(+), 5 deletions(-)
Existing LUT precision structure is having only 16 bit precision. This is not enough for upcoming enhanced hardwares and advance usecases like HDR processing. Hence added a new structure with 32 bit precision values. Also added the code, for extracting the same from values passed from userspace.
v4: Rebase
v5: Relocated the helper function to drm_color_mgmt.c. Declared the same in a header file (Alexandru Gheorghe)
v6: Enhanced gamma lut structure to take U32.32 format as input. This is needed for HDR usecase which require higher precision.
v7: Addressed Maarten's review comments and fixed the calculation.
Signed-off-by: Uma Shankar uma.shankar@intel.com Reviewed-by: Alexandru Gheorghe alexandru-cosmin.gheorghe@arm.com --- drivers/gpu/drm/drm_color_mgmt.c | 20 ++++++++++++++++++++ include/drm/drm_color_mgmt.h | 1 + include/uapi/drm/drm_mode.h | 15 +++++++++++++++ 3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index d5d34d0..79ff874 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -128,6 +128,26 @@ uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision) } EXPORT_SYMBOL(drm_color_lut_extract);
+/* + * Added to accommodate enhanced LUT precision. + * Max LUT precision is 32 bits. + */ +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision) +{ + u64 val = user_input & 0xffffffff; + u32 max = 0xffffffff >> (32 - bit_precision); + + /* Round only if we're not using full precision. */ + if (bit_precision < 32) { + val += 1UL << (32 - bit_precision - 1); + val >>= 32 - bit_precision; + } + + return ((user_input & 0xffffffff00000000) | + clamp_val(val, 0, max)); +} +EXPORT_SYMBOL(drm_color_lut_extract_ext); + /** * drm_crtc_enable_color_mgmt - enable color management properties * @crtc: DRM CRTC diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index d1c662d..c9d2746 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -30,6 +30,7 @@ struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision); +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision);
void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, uint degamma_lut_size, diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 09d7296..ca81410 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -629,6 +629,21 @@ struct drm_color_lut { __u16 reserved; };
+/* + * Creating 64 bit palette entries for better data + * precision. This will be required for HDR and + * similar color processing usecases. + */ +struct drm_color_lut_ext { + /* + * Data is U32.32 fixed point format. + */ + __u64 red; + __u64 green; + __u64 blue; + __u64 reserved; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
On Fri, Mar 29, 2019 at 01:45:59AM +0530, Uma Shankar wrote:
Hi Uma
When can we merge these plane color-mgmt support into upstream ? or can we merge the DRM-CORE part patches firstly?
thanks james
Add Plane Degamma as a blob property and plane degamma size as a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Added "Display Color Hardware Pipeline" flow to kernel documentation as suggested by "Ville Syrjala" and "Brian Starkey". Moved the property creation to drm_color_mgmt.c file to consolidate all color operations at one place.
v6: Fixed checkpatch issues with --strict as parameter.
Signed-off-by: Uma Shankar uma.shankar@intel.com Reviewed-by: Alexandru Gheorghe alexandru-cosmin.gheorghe@arm.com --- Documentation/gpu/drm-kms.rst | 90 +++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 5 ++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++ drivers/gpu/drm/drm_color_mgmt.c | 43 +++++++++++++-- include/drm/drm_plane.h | 24 +++++++++ 6 files changed, 170 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 23a3c98..9e64df5 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -473,12 +473,102 @@ FB_DAMAGE_CLIPS Color Management Properties ---------------------------
+Below is how a typical hardware pipeline for color +will look like: + +.. kernel-render:: DOT + :alt: Display Color Pipeline + :caption: Display Color Pipeline Overview + + digraph "KMS" { + node [shape=box] + + subgraph cluster_static { + style=dashed + label="Display Color Hardware Blocks" + + node [bgcolor=grey style=filled] + "Plane Degamma A" -> "Plane CSC/CTM A" + "Plane CSC/CTM A" -> "Plane Gamma A" + "Pipe Blender" [color=lightblue,style=filled, width=5.25, height=0.75]; + "Plane Gamma A" -> "Pipe Blender" + "Pipe Blender" -> "Pipe DeGamma" + "Pipe DeGamma" -> "Pipe CSC/CTM" + "Pipe CSC/CTM" -> "Pipe Gamma" + "Pipe Gamma" -> "Pipe Output" + } + + subgraph cluster_static { + style=dashed + + node [shape=box] + "Plane Degamma B" -> "Plane CSC/CTM B" + "Plane CSC/CTM B" -> "Plane Gamma B" + "Plane Gamma B" -> "Pipe Blender" + } + + subgraph cluster_static { + style=dashed + + node [shape=box] + "Plane Degamma C" -> "Plane CSC/CTM C" + "Plane CSC/CTM C" -> "Plane Gamma C" + "Plane Gamma C" -> "Pipe Blender" + } + + subgraph cluster_fb { + style=dashed + label="RAM" + + node [shape=box width=1.7 height=0.2] + + "FB 1" -> "Plane Degamma A" + "FB 2" -> "Plane Degamma B" + "FB 3" -> "Plane Degamma C" + } + } + +In real world usecases, + +1. Plane Degamma can be used to linearize a non linear gamma +encoded framebuffer. This is needed to do any linear math like +color space conversion. For ex, linearize frames encoded in SRGB +or by HDR curve. + +2. Later Plane CTM block can convert the content to some different +colorspace. For ex, SRGB to BT2020 etc. + +3. Plane Gamma block can be used later to re-apply the non-linear +curve. This can also be used to apply Tone Mapping for HDR usecases. + +All the layers or framebuffers need to be converted to same color +space and format before blending. The plane color hardware blocks +can help with this. Once the Data is blended, similar color processing +can be done on blended output using pipe color hardware blocks. + +DRM Properties have been created to define and expose all these +hardware blocks to userspace. A userspace application (compositor +or any color app) can use these interfaces and define policies to +efficiently use the display hardware for such color operations. + +Pipe Color Management Properties +--------------------------------- + .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :doc: overview
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :export:
+Plane Color Management Properties +--------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: Plane Color Properties + +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: export + Tile Group Property -------------------
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 5eb4013..6336542 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -655,6 +655,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed);
if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 59ffb6b..a8fb7f9 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -243,6 +243,10 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->fence = NULL; state->commit = NULL; state->fb_damage_clips = NULL; + + if (state->degamma_lut) + drm_property_blob_get(state->degamma_lut); + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
@@ -289,6 +293,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_crtc_commit_put(state->commit);
drm_property_blob_put(state->fb_damage_clips); + drm_property_blob_put(state->degamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index ea797d4..b21fba5 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -572,6 +572,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->degamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->degamma_lut, + val, -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -635,6 +642,9 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->degamma_lut_property) { + *val = (state->degamma_lut) ? + state->degamma_lut->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 79ff874..8ccefd8 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -29,11 +29,11 @@ /** * DOC: overview * - * Color management or color space adjustments is supported through a set of 5 - * properties on the &drm_crtc object. They are set up by calling + * Pipe Color management or color space adjustments is supported through a + * set of 5 properties on the &drm_crtc object. They are set up by calling * drm_crtc_enable_color_mgmt(). * - * "DEGAMMA_LUT”: + * "DEGAMMA_LUT * Blob property to set the degamma lookup table (LUT) mapping pixel data * from the framebuffer before it is given to the transformation matrix. * The data is interpreted as an array of &struct drm_color_lut elements. @@ -484,6 +484,43 @@ int drm_plane_create_color_properties(struct drm_plane *plane, EXPORT_SYMBOL(drm_plane_create_color_properties);
/** + * DOC: Plane Color Properties + * + * Plane Color management or color space adjustments is supported + * through a set of 5 properties on the &drm_plane object. + * + * degamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply degamma curve using the h/w plane degamma processing + * engine, thereby making the content as linear for further color + * processing. + * + * degamma_lut_size_property: + * Range Property to indicate size of the plane degamma LUT. + */ +int drm_plane_color_create_prop(struct drm_device *dev, + struct drm_plane *plane) +{ + struct drm_property *prop; + + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + plane->degamma_lut_property = prop; + + prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE, + "PLANE_DEGAMMA_LUT_SIZE", 0, + UINT_MAX); + if (!prop) + return -ENOMEM; + plane->degamma_lut_size_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_plane_color_create_prop); + +/** * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check * @tests: bitmask of tests to run diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 6078c70..757f1e8 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -195,6 +195,14 @@ struct drm_plane_state { */ bool visible;
+ /* @degamma_lut: + * + * Lookup table for converting framebuffer pixel data before apply the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *degamma_lut; + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. @@ -205,6 +213,8 @@ struct drm_plane_state {
/** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + u8 color_mgmt_changed : 1; };
static inline struct drm_rect @@ -705,6 +715,18 @@ struct drm_plane { * See drm_plane_create_color_properties(). */ struct drm_property *color_range_property; + + /** + * @degamma_lut_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to linear gamma. + */ + struct drm_property *degamma_lut_property; + + /** + * @degamma_lut_size_property: Optional Plane property for the + * size of the degamma LUT as supported by the driver (read-only). + */ + struct drm_property *degamma_lut_size_property; };
#define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -754,6 +776,8 @@ static inline u32 drm_plane_mask(const struct drm_plane *plane) int drm_mode_plane_set_obj_prop(struct drm_plane *plane, struct drm_property *property, uint64_t value); +int drm_plane_color_create_prop(struct drm_device *dev, + struct drm_plane *plane);
/** * drm_plane_find - find a &drm_plane
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar uma.shankar@intel.com Reviewed-by: Alexandru Gheorghe alexandru-cosmin.gheorghe@arm.com --- Documentation/gpu/drm-kms.rst | 3 +++ drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 11 +++++++++++ include/drm/drm_plane.h | 15 +++++++++++++++ 5 files changed, 43 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 9e64df5..14f79f1 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -569,6 +569,9 @@ Plane Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :doc: export
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: ctm_property + Tile Group Property -------------------
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index a8fb7f9..c5664aa 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -246,6 +246,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,
if (state->degamma_lut) drm_property_blob_get(state->degamma_lut); + if (state->ctm) + drm_property_blob_get(state->ctm); + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); @@ -294,6 +297,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips); drm_property_blob_put(state->degamma_lut); + drm_property_blob_put(state->ctm); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index b21fba5..495152a 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -579,6 +579,14 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->ctm_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->ctm, + val, + sizeof(struct drm_color_ctm), -1, + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -645,6 +653,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, } else if (property == plane->degamma_lut_property) { *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; + } else if (property == plane->ctm_property) { + *val = (state->ctm) ? state->ctm->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 8ccefd8..9747ac7 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -497,6 +497,11 @@ int drm_plane_create_color_properties(struct drm_plane *plane, * * degamma_lut_size_property: * Range Property to indicate size of the plane degamma LUT. + * + * ctm_property: + * Blob property which allows a userspace to provide CTM coefficients + * to do color space conversion or any other enhancement by doing a + * matrix multiplication using the h/w CTM processing engine */ int drm_plane_color_create_prop(struct drm_device *dev, struct drm_plane *plane) @@ -516,6 +521,12 @@ int drm_plane_color_create_prop(struct drm_device *dev, return -ENOMEM; plane->degamma_lut_size_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_CTM", 0); + if (!prop) + return -ENOMEM; + plane->ctm_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_color_create_prop); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 757f1e8..38b52a2 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -204,6 +204,14 @@ struct drm_plane_state { struct drm_property_blob *degamma_lut;
/** + * @ctm: + * + * Color transformation matrix. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is a &struct drm_color_ctm. + */ + struct drm_property_blob *ctm; + + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. * @@ -727,6 +735,13 @@ struct drm_plane { * size of the degamma LUT as supported by the driver (read-only). */ struct drm_property *degamma_lut_size_property; + + /** + * @plane_ctm_property: Optional Plane property to set the + * matrix used to convert colors after the lookup in the + * degamma LUT. + */ + struct drm_property *ctm_property; };
#define obj_to_plane(x) container_of(x, struct drm_plane, base)
Add plane gamma as blob property and size as a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar uma.shankar@intel.com Reviewed-by: Alexandru Gheorghe alexandru-cosmin.gheorghe@arm.com --- Documentation/gpu/drm-kms.rst | 6 ++++++ drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 9 +++++++++ drivers/gpu/drm/drm_color_mgmt.c | 22 ++++++++++++++++++++++ include/drm/drm_plane.h | 22 ++++++++++++++++++++++ 5 files changed, 62 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 14f79f1..0877faf 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -572,6 +572,12 @@ Plane Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :doc: ctm_property
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: gamma_lut_property + +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: gamma_lut_size_property + Tile Group Property -------------------
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index c5664aa..2739c27 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -248,6 +248,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, drm_property_blob_get(state->degamma_lut); if (state->ctm) drm_property_blob_get(state->ctm); + if (state->gamma_lut) + drm_property_blob_get(state->gamma_lut);
state->color_mgmt_changed = false; } @@ -298,6 +300,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->fb_damage_clips); drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); + drm_property_blob_put(state->gamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 495152a..3eb9423 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -587,6 +587,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->gamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->gamma_lut, + val, -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -655,6 +662,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->degamma_lut->base.id : 0; } else if (property == plane->ctm_property) { *val = (state->ctm) ? state->ctm->base.id : 0; + } else if (property == plane->gamma_lut_property) { + *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 9747ac7..f168609 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -502,6 +502,15 @@ int drm_plane_create_color_properties(struct drm_plane *plane, * Blob property which allows a userspace to provide CTM coefficients * to do color space conversion or any other enhancement by doing a * matrix multiplication using the h/w CTM processing engine + * + * gamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply gamma/tone-mapping curve using the h/w plane gamma + * processing engine, thereby making the content as non-linear + * or to perform any tone mapping operation for HDR usecases. + * + * gamma_lut_size_property: + * Range Property to indicate size of the plane gamma LUT. */ int drm_plane_color_create_prop(struct drm_device *dev, struct drm_plane *plane) @@ -527,6 +536,19 @@ int drm_plane_color_create_prop(struct drm_device *dev, return -ENOMEM; plane->ctm_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_GAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + plane->gamma_lut_property = prop; + + prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE, + "PLANE_GAMMA_LUT_SIZE", 0, + UINT_MAX); + if (!prop) + return -ENOMEM; + plane->gamma_lut_size_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_color_create_prop); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 38b52a2..45571ae 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -212,6 +212,15 @@ struct drm_plane_state { struct drm_property_blob *ctm;
/** + * @gamma_lut: + * + * Lookup table for converting pixel data after the color conversion + * matrix @ctm. See drm_plane_enable_color_mgmt(). The blob (if not + * NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *gamma_lut; + + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. * @@ -742,6 +751,19 @@ struct drm_plane { * degamma LUT. */ struct drm_property *ctm_property; + + /** + * @plane_gamma_lut_property: Optional Plane property to set the LUT + * used to convert the colors, after the CTM matrix, to the common + * gamma space chosen for blending. + */ + struct drm_property *gamma_lut_property; + + /** + * @plane_gamma_lut_size_property: Optional Plane property for the size + * of the gamma LUT as supported by the driver (read-only). + */ + struct drm_property *gamma_lut_size_property; };
#define obj_to_plane(x) container_of(x, struct drm_plane, base)
Define helper function to enable Plane color features to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar uma.shankar@intel.com Reviewed-by: Alexandru Gheorghe alexandru-cosmin.gheorghe@arm.com --- drivers/gpu/drm/drm_color_mgmt.c | 42 ++++++++++++++++++++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 5 +++++ 2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index f168609..9cedd27 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -484,6 +484,48 @@ int drm_plane_create_color_properties(struct drm_plane *plane, EXPORT_SYMBOL(drm_plane_create_color_properties);
/** + * drm_plane_enable_color_mgmt - enable color management properties + * @plane: DRM Plane + * @plane_degamma_lut_size: the size of the degamma lut (before CSC) + * @plane_has_ctm: whether to attach ctm_property for CSC matrix + * @plane_gamma_lut_size: the size of the gamma lut (after CSC) + * + * This function lets the driver enable the color correction + * properties on a plane. This includes 3 degamma, csc and gamma + * properties that userspace can set and 2 size properties to inform + * the userspace of the lut sizes. Each of the properties are + * optional. The gamma and degamma properties are only attached if + * their size is not 0 and ctm_property is only attached if has_ctm is + * true. + */ +void drm_plane_enable_color_mgmt(struct drm_plane *plane, + u32 plane_degamma_lut_size, + bool plane_has_ctm, + u32 plane_gamma_lut_size) +{ + if (plane_degamma_lut_size) { + drm_object_attach_property(&plane->base, + plane->degamma_lut_property, 0); + drm_object_attach_property(&plane->base, + plane->degamma_lut_size_property, + plane_degamma_lut_size); + } + + if (plane_has_ctm) + drm_object_attach_property(&plane->base, + plane->ctm_property, 0); + + if (plane_gamma_lut_size) { + drm_object_attach_property(&plane->base, + plane->gamma_lut_property, 0); + drm_object_attach_property(&plane->base, + plane->gamma_lut_size_property, + plane_gamma_lut_size); + } +} +EXPORT_SYMBOL(drm_plane_enable_color_mgmt); + +/** * DOC: Plane Color Properties * * Plane Color management or color space adjustments is supported diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index c9d2746..8726cee 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -71,6 +71,11 @@ int drm_plane_create_color_properties(struct drm_plane *plane, enum drm_color_encoding default_encoding, enum drm_color_range default_range);
+void drm_plane_enable_color_mgmt(struct drm_plane *plane, + u32 plane_degamma_lut_size, + bool plane_has_ctm, + u32 plane_gamma_lut_size); + /** * enum drm_color_lut_tests - hw-specific LUT tests to perform *
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call drm_plane_color_create_prop function, which will in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/intel_color.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_device_info.h | 5 +++++ drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ 4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 25c264e..51c1456 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -55,6 +55,7 @@ #include <drm/drm_util.h> #include <drm/drm_dsc.h> #include <drm/drm_connector.h> +#include <drm/drm_plane.h> #include <drm/i915_mei_hdcp_interface.h>
#include "i915_fixed.h" @@ -339,6 +340,11 @@ struct drm_i915_display_funcs { * involved with the same commit. */ void (*load_luts)(const struct intel_crtc_state *crtc_state); + /* Add Plane Color callbacks */ + void (*load_plane_csc_matrix)(const struct drm_plane_state + *plane_state); + void (*load_plane_luts)(const struct drm_plane_state + *plane_state); };
#define CSR_VERSION(major, minor) ((major) << 16 | (minor)) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 467fd1a..0f8cb18 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -869,6 +869,21 @@ int intel_color_check(struct intel_crtc_state *crtc_state) return 0; }
+void intel_plane_color_init(struct drm_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + drm_plane_color_create_prop(plane->dev, plane); + + /* Enable color management support when we have degamma or gamma LUTs. */ + if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 || + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) + drm_plane_enable_color_mgmt(plane, + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size, + true, + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size); +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 7e04b48..91c5925 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -194,6 +194,11 @@ struct intel_device_info { u32 degamma_lut_tests; u32 gamma_lut_tests; } color; + + struct plane_color_luts { + u16 plane_degamma_lut_size; + u16 plane_gamma_lut_size; + } plane_color; };
struct intel_runtime_info { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7b29..7c7dbb8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -658,6 +658,14 @@ struct intel_plane_state { */ u32 slave;
+ /* + * Use reduced/limited/broadcast rbg range, compressing from the full + * range fed into the crtcs. + */ + bool limited_color_range; + /* Gamma mode programmed on the plane */ + u32 gamma_mode; + struct drm_intel_sprite_colorkey ckey; };
@@ -2536,6 +2544,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ int intel_color_check(struct intel_crtc_state *crtc_state); void intel_color_commit(const struct intel_crtc_state *crtc_state); void intel_color_load_luts(const struct intel_crtc_state *crtc_state); +void intel_plane_color_init(struct drm_plane *plane);
/* intel_lspcon.c */ bool lspcon_init(struct intel_digital_port *intel_dig_port);
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 5 +++- drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++ drivers/gpu/drm/i915/intel_color.c | 57 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 4 +++ drivers/gpu/drm/i915/intel_sprite.c | 4 +++ 5 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a7e1611..e4d7e22 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -117,7 +117,10 @@ }
#define BDW_COLORS \ - .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } + .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \ + .plane_color = { .plane_degamma_lut_size = 0, \ + .plane_gamma_lut_size = 16 } + #define CHV_COLORS \ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c866379..e896798 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -257,6 +257,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv))
+/* Plane Gamma Registers */ +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) +#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) + #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ if (__builtin_constant_p(mask)) \ @@ -10156,6 +10160,27 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Plane Gamma in Gen9+ */ +#define _PLANE_GAMC_1_A 0x701d0 +#define _PLANE_GAMC_1_B 0x711d0 +#define _PLANE_GAMC_2_A 0x702d0 +#define _PLANE_GAMC_2_B 0x712d0 +#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B) +#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B) +#define PLANE_GAMC(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe)) + +#define _PLANE_GAMC16_1_A 0x70210 +#define _PLANE_GAMC16_1_B 0x71210 +#define _PLANE_GAMC16_2_A 0x70310 +#define _PLANE_GAMC16_2_B 0x71310 +#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \ + _PLANE_GAMC16_1_B) +#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \ + _PLANE_GAMC16_2_B) +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ + _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 0f8cb18..c756cd9 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -562,6 +562,59 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state) } }
+static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size = + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size; + + if (state->gamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u32 word = + drm_color_lut_extract_ext(lut[i].red, 10) << 20 | + drm_color_lut_extract_ext(lut[i].green, 10) << 10 | + drm_color_lut_extract_ext(lut[i].blue, 10); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), word); + } + + /* Program the max register to clamp values > 1.0. */ + i = lut_size - 1; + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), + drm_color_lut_extract_ext(lut[i].red, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), + drm_color_lut_extract_ext(lut[i].green, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), + drm_color_lut_extract_ext(lut[i].blue, 16)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), + (v << 20) | (v << 10) | v); + } + + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1); + } +} + +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ +static void broadwell_load_plane_luts(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + + bdw_load_plane_gamma_lut(state, + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); +} + static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -873,6 +926,10 @@ void intel_plane_color_init(struct drm_plane *plane) { struct drm_i915_private *dev_priv = to_i915(plane->dev);
+ if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || + IS_BROXTON(dev_priv)) + dev_priv->display.load_plane_luts = broadwell_load_plane_luts; + drm_plane_color_create_prop(plane->dev, plane);
/* Enable color management support when we have degamma or gamma LUTs. */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8576a7f..2775c3f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14412,6 +14412,10 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, DRM_MODE_ROTATE_0, supported_rotations);
+ /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 65de738..766e03e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -2333,6 +2333,10 @@ struct intel_plane * BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE));
+ /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
Load plane color luts as part of atomic plane updates. This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +++ drivers/gpu/drm/i915/intel_color.c | 8 ++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 9d32a6f..32269bd 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -271,6 +271,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state, struct intel_plane_state *new_plane_state = intel_atomic_get_new_plane_state(state, plane);
+ if (new_plane_state->base.color_mgmt_changed) + intel_color_load_plane_luts(&new_plane_state->base); + if (new_plane_state->base.visible) { intel_update_plane(plane, new_crtc_state, new_plane_state); } else if (new_plane_state->slave) { diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index c756cd9..b56c3999 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -841,6 +841,14 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) return cgm_mode; }
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) +{ + struct drm_device *dev = plane_state->plane->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + dev_priv->display.load_plane_luts(plane_state); +} + int intel_color_check(struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7c7dbb8..a17e6a4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2545,6 +2545,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ void intel_color_commit(const struct intel_crtc_state *crtc_state); void intel_color_load_luts(const struct intel_crtc_state *crtc_state); void intel_plane_color_init(struct drm_plane *plane); +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */ bool lspcon_init(struct intel_digital_port *intel_dig_port);
Add Plane color capabilties, support for degamma and gamma added.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/intel_color.c | 12 +++++------- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_sprite.c | 11 +++++++++-- 4 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index b56c3999..afb1d00 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -930,7 +930,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state) return 0; }
-void intel_plane_color_init(struct drm_plane *plane) +void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size, + u32 gamma_lut_size) { struct drm_i915_private *dev_priv = to_i915(plane->dev);
@@ -941,12 +942,9 @@ void intel_plane_color_init(struct drm_plane *plane) drm_plane_color_create_prop(plane->dev, plane);
/* Enable color management support when we have degamma or gamma LUTs. */ - if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 || - INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) - drm_plane_enable_color_mgmt(plane, - INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size, - true, - INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size); + if (degamma_lut_size != 0 || gamma_lut_size != 0) + drm_plane_enable_color_mgmt(plane, degamma_lut_size, + true, gamma_lut_size); }
void intel_color_init(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2775c3f..fc43c37 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14413,8 +14413,8 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, supported_rotations);
/* Add Plane Color properties */ - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) - intel_plane_color_init(&plane->base); + if (IS_BROADWELL(dev_priv)) + intel_plane_color_init(&plane->base, 0, 16);
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a17e6a4..3a68191 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2544,7 +2544,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ int intel_color_check(struct intel_crtc_state *crtc_state); void intel_color_commit(const struct intel_crtc_state *crtc_state); void intel_color_load_luts(const struct intel_crtc_state *crtc_state); -void intel_plane_color_init(struct drm_plane *plane); +void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size, + u32 gamma_lut_size); void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */ diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 766e03e..41fdc12 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -2334,8 +2334,15 @@ struct intel_plane * BIT(DRM_MODE_BLEND_COVERAGE));
/* Add Plane Color properties */ - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) - intel_plane_color_init(&plane->base); + if (INTEL_GEN(dev_priv) <= 10) + intel_plane_color_init(&plane->base, 0, 16); + + if (INTEL_GEN(dev_priv) >= 11) { + if (icl_is_hdr_plane(dev_priv, plane_id)) + intel_plane_color_init(&plane->base, 128, 33); + else + intel_plane_color_init(&plane->base, 33, 33); + }
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
Add register definitions for ICL Plane Degamma.
v2: Fixed register definitions for Degamma Index, spotted by Matt Roper.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e896798..ed02963 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10181,6 +10181,48 @@ enum skl_power_gate { #define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+/* Plane Color Register for Gen11+ */ +/* Plane Degamma Registers */ +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) + +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_INDEX_4_A 0x704D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_4_B 0x714D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_5_A 0x705D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_5_B 0x715D0 +#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B) + +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_5(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B) + +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_4_A 0x704D4 +#define _PLANE_PRE_CSC_GAMC_DATA_4_B 0x714D4 +#define _PLANE_PRE_CSC_GAMC_DATA_5_A 0x705D4 +#define _PLANE_PRE_CSC_GAMC_DATA_5_B 0x715D4 +#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B) +#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B) + +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\ + _PLANE_PRE_CSC_GAMC_DATA_5(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/intel_color.c | 86 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index afb1d00..504c046 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -615,6 +615,89 @@ static void broadwell_load_plane_luts(const struct drm_plane_state *state) INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); }
+static void icl_load_plane_degamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + lut_size = 128; + if (state->degamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(lut[i].red, + 24); + u32 lut_val = (word & 0x7ffffffff) >> 8; + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + drm_color_lut_extract_ext(lut[i].red, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + drm_color_lut_extract_ext(lut[i].green, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + drm_color_lut_extract_ext(lut[i].blue, 24)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + (1 << 24) - 1); + } + } else { + lut_size = 32; + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), + lut[i].green); + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } + } +} + +/* Loads the palette/gamma unit for the CRTC on Gen11+. */ +static void icl_load_plane_luts(const struct drm_plane_state *state) +{ + icl_load_plane_degamma_lut(state, 0); +} + static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -978,6 +1061,9 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_commit = ilk_color_commit; }
+ if (INTEL_GEN(dev_priv) >= 11) + dev_priv->display.load_plane_luts = icl_load_plane_luts; + /* Enable color management support when we have degamma & gamma LUTs. */ if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
Add Plane Gamma Register definitions for ICL+
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 42 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ed02963..5f5c18a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10222,7 +10222,47 @@ enum skl_power_gate {
#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\ _PLANE_PRE_CSC_GAMC_DATA_5(pipe)) - +/* Plane Gamma Registers */ +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701D8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711D8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702D8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712D8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B) + +#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe),\ + _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_INDEX_4_A 0x704D8 +#define _PLANE_POST_CSC_GAMC_INDEX_4_B 0x714D8 +#define _PLANE_POST_CSC_GAMC_INDEX_5_A 0x705D8 +#define _PLANE_POST_CSC_GAMC_INDEX_5_B 0x715D8 +#define _PLANE_POST_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_4_A, _PLANE_POST_CSC_GAMC_INDEX_4_B) +#define _PLANE_POST_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe, _PLANE_POSt_CSC_GAMC_INDEX_5_A, _PLANE_POST_CSC_GAMC_INDEX_5_B) + +#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_4(pipe),\ + _PLANE_POSt_CSC_GAMC_INDEX_5(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701DC +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711DC +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702DC +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712DC +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, _PLANE_POST_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, _PLANE_POST_CSC_GAMC_DATA_ENH_2_B) + +#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe),\ + _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_4_A 0x704DC +#define _PLANE_POST_CSC_GAMC_DATA_4_B 0x714DC +#define _PLANE_POST_CSC_GAMC_DATA_5_A 0x705DC +#define _PLANE_POST_CSC_GAMC_DATA_5_B 0x715DC +#define _PLANE_POST_CSC_GAMC_DATA_4(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_4_A, _PLANE_POST_CSC_GAMC_DATA_4_B) +#define _PLANE_POST_CSC_GAMC_DATA_5(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_5_A, _PLANE_POST_CSC_GAMC_DATA_5_B) + +#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\ + _PLANE_POST_CSC_GAMC_DATA_5(pipe)) +/* Plane Gamma Registers */ /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 504c046..22790b4 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -692,10 +692,85 @@ static void icl_load_plane_degamma_lut(const struct drm_plane_state *state, } }
+static void icl_load_plane_gamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + lut_size = 32; + if (icl_is_hdr_plane(dev_priv, plane)) { + if (state->degamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(lut[i].red, 24); + u32 lut_val = (word & 0x7ffffffff) >> 8; + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + drm_color_lut_extract_ext(lut[i].red, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + drm_color_lut_extract_ext(lut[i].green, 24)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + drm_color_lut_extract_ext(lut[i].blue, 24)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1), + (1 << 24) - 1); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2), + (1 << 24) - 1); + } + } else { + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), + lut[i].green); + + /* Program the max register to clamp values > 1.0. */ + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i), v); + } + + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1), + (1 << 16)); + I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2), + (1 << 16)); + } + } +} + /* Loads the palette/gamma unit for the CRTC on Gen11+. */ static void icl_load_plane_luts(const struct drm_plane_state *state) { icl_load_plane_degamma_lut(state, 0); + icl_load_plane_gamma_lut(state, 0); }
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
Update the plane gamma and degamma feature in the plane state and eventually program to PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_color.c | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 6 +++++- 3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f5c18a..40bde4b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6757,6 +6757,7 @@ enum { #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) +#define PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE (1 << 14) #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 22790b4..aa73f88 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -769,8 +769,14 @@ static void icl_load_plane_gamma_lut(const struct drm_plane_state *state, /* Loads the palette/gamma unit for the CRTC on Gen11+. */ static void icl_load_plane_luts(const struct drm_plane_state *state) { + struct intel_plane_state *plane_state = + to_intel_plane_state(state); + icl_load_plane_degamma_lut(state, 0); icl_load_plane_gamma_lut(state, 0); + + plane_state->gamma_mode |= PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE; + plane_state->gamma_mode |= ~PLANE_COLOR_PLANE_GAMMA_DISABLE; }
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fc43c37..6b37052 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3815,7 +3815,11 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->base.plane); u32 plane_color_ctl = 0;
- plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + if (INTEL_GEN(dev_priv) <= 11) + plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + else + plane_color_ctl |= plane_state->gamma_mode; + plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 40bde4b..657232bd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10263,6 +10263,50 @@ enum skl_power_gate {
#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\ _PLANE_POST_CSC_GAMC_DATA_5(pipe)) + +/* Plane CSC Registers */ +#define _PLANE_CSC_RY_GY_1_A 0x70210 +#define _PLANE_CSC_RY_GY_2_A 0x70310 + +#define _PLANE_CSC_RY_GY_1_B 0x71210 +#define _PLANE_CSC_RY_GY_2_B 0x71310 + +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ + _PLANE_CSC_RY_GY_1_B) +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ + _PLANE_INPUT_CSC_RY_GY_2_B) + +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) + +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228 +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328 + +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228 +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328 + +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ + _PLANE_CSC_PREOFF_HI_1_B) +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ + _PLANE_CSC_PREOFF_HI_2_B) +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ + (index) * 4) + +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 + +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 + +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ + _PLANE_CSC_POSTOFF_HI_1_B) +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ + _PLANE_CSC_POSTOFF_HI_2_B) +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ + (index) * 4) /* Plane Gamma Registers */ /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
Implement plane CSC on ICL.
Signed-off-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_color.c | 86 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 3 ++ 3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 657232bd..f82a5bc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6750,6 +6750,7 @@ enum { #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */ #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index aa73f88..ed21d98 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -606,6 +606,90 @@ static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, } }
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u16 coeffs[9] = {}; + u16 postoff = 0; + int i; + + if (state->ctm) { + struct drm_color_ctm *ctm = state->ctm->data; + const u64 *input; + + input = ctm->matrix; + + /* + * Convert fixed point S31.32 input to format supported by the + * hardware. + */ + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { + u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; + + /* + * Clamp input value to min/max supported by + * hardware. + */ + abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); + + /* sign bit */ + if (CTM_COEFF_NEGATIVE(input[i])) + coeffs[i] |= 1 << 15; + + if (abs_coeff < CTM_COEFF_0_125) + coeffs[i] |= (3 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 12); + else if (abs_coeff < CTM_COEFF_0_25) + coeffs[i] |= (2 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 11); + else if (abs_coeff < CTM_COEFF_0_5) + coeffs[i] |= (1 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 10); + else if (abs_coeff < CTM_COEFF_1_0) + coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); + else if (abs_coeff < CTM_COEFF_2_0) + coeffs[i] |= (7 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 8); + else + coeffs[i] |= (6 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 7); + } + } else { + /* + * Load an identity matrix if no coefficients are provided. + * + * TODO: Check what kind of values actually come out of the + * pipe with these coeff/postoff values and adjust to get the + * best accuracy. Perhaps we even need to take the bpc value + * into consideration. + */ + for (i = 0; i < 3; i++) + coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0; + } + + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 0), + coeffs[0] << 16 | coeffs[1]); + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 1), coeffs[2] << 16); + + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 3), + coeffs[3] << 16 | coeffs[4]); + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 4), coeffs[5] << 16); + + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 5), + coeffs[6] << 16 | coeffs[7]); + I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 6), coeffs[8] << 16); + + I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 0), 0); + I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 1), 0); + I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 2), 0); + + I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 0), postoff); + I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 1), postoff); + I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 2), postoff); +} + /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ static void broadwell_load_plane_luts(const struct drm_plane_state *state) { @@ -777,6 +861,8 @@ static void icl_load_plane_luts(const struct drm_plane_state *state)
plane_state->gamma_mode |= PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE; plane_state->gamma_mode |= ~PLANE_COLOR_PLANE_GAMMA_DISABLE; + + icl_load_plane_csc_matrix(state); }
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6b37052..83c9d51 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3834,6 +3834,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; }
+ if (plane_state->base.ctm) + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; + return plane_color_ctl; }
On Thu, 28 Mar 2019 at 16:50, Uma Shankar uma.shankar@intel.com wrote:
I can't find any comments on this one.
What's the status of this?
Thanks, Eze
Hi Eze, This was blocked due to lack of a userspace consumer. Since its adds a new UAPI, we need a userspace consumer using this for it to get merge. We have some folks signed up in Intel who can help here. Hopefully we can see some movement on this soon.
Regards, Uma Shankar
On Wed, 2019-06-19 at 06:20 +0000, Shankar, Uma wrote:
Hi Uma,
Thanks a lot for your reply.
We do have a userspace consumer in chromeos [1]. This is being shipped since some time now, and I have been (perhaps too silently) waiting for this series to be merged.
Let me try to rebase at least the uAPI bits, on top of rockchip changes and re-submit.
Do we have IGT tests already written for it? Otherwise, I'll take care of that as well.
Thanks, Eze
[1] https://chromium.googlesource.com/chromium/src/+/lkgr/ui/ozone/platform/drm/...
On Wed, Jun 19, 2019 at 10:18:18AM -0300, Ezequiel Garcia wrote:
I don't think the proposed uapi will be good enough and instead we need something like the gamma_mode prop for planes as well. Eg. even bunch of Intel platforms have plane gamma where the input points are not evenly spaced, so we again have the problem of either lying to userspace and throwing away a bunch of the user provided LUT entries, or we add the gamma_mode prop that actually describes the LUT capabilities.
Another idea that was thrown around was supporting hardware that supports only hardcoded gamma curves. We need to describe those somehow and let userspace select the right one.
dri-devel@lists.freedesktop.org
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Ezequiel Garcia -
Ezequiel Garcia -
james qian wang (Arm Technology China) -
Shankar, Uma -
Uma Shankar
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Ville Syrjälä