On Mon, Aug 10, 2020 at 3:27 PM Jordan Crouse jcrouse@codeaurora.org wrote:

Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue.

GPU submissions can access the active context via the submitqueue instead of requiring it to be passed around from function to function.

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org

drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++--- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- drivers/gpu/drm/msm/msm_drv.c | 3 ++- drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++ drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 8 ++++---- drivers/gpu/drm/msm/msm_gpu.c | 9 ++++----- drivers/gpu/drm/msm/msm_gpu.h | 7 +++---- drivers/gpu/drm/msm/msm_submitqueue.c | 8 +++++++- 11 files changed, 39 insertions(+), 30 deletions(-)

[snip]

diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 972490b14ba5..9c573c4269cb 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -142,6 +142,7 @@ struct msm_gem_submit { bool valid; /* true if no cmdstream patching needed */ bool in_rb; /* "sudo" mode, copy cmds into RB */ struct msm_ringbuffer *ring;

•   struct msm_file_private *ctx;
  

So, it looks like this is (currently) unused, and everything is instead using submit->queue->ctx

That said, changing this so the submit also holds a ref to the ctx seems to fix the intermittent splat I can trigger by repeatedly hanging the gpu. Which (from the pile of additional tracepoints I've added on top of this series) seems to be related to re-playing submits after the userspace process has crashed and/or closed the device.

It seems like the reference the submit holds to the queue should keep the ctx (and therefore address space) alive, but I need to dig through that a bit more.

BR, -R

    unsigned int nr_cmds;
    unsigned int nr_bos;
    u32 ident;         /* A "identifier" for the submit for logging */

On Mon, Aug 10, 2020 at 04:26:53PM -0600, Jordan Crouse wrote:

Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled.

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org

This patch adds a hard dependency on IOMMU_IO_PGTABLE (for alloc_io_pgtable_ops and free_io_pgtable_ops).

Guenter

---

drivers/gpu/drm/msm/msm_gpummu.c | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 190 ++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 16 ++- 3 files changed, 205 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c index 310a31b05faa..aab121f4beb7 100644 --- a/drivers/gpu/drm/msm/msm_gpummu.c +++ b/drivers/gpu/drm/msm/msm_gpummu.c @@ -102,7 +102,7 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) }

gpummu->gpu = gpu;

• msm_mmu_init(&gpummu->base, dev, &funcs);

• msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU);

  return &gpummu->base;

} diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 1b6635504069..bc04dda8a198 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -4,15 +4,201 @@

• Author: Rob Clark robdclark@gmail.com

*/

+#include <linux/io-pgtable.h> #include "msm_drv.h" #include "msm_mmu.h"

struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain;

• atomic_t pagetables;

};

#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)

+struct msm_iommu_pagetable {

• struct msm_mmu base;
• struct msm_mmu *parent;
• struct io_pgtable_ops *pgtbl_ops;
• phys_addr_t ttbr;
• u32 asid;

+}; +static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu) +{

• return container_of(mmu, struct msm_iommu_pagetable, base);

+}

+static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova,

• size_t size)
  

+{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
• size_t unmapped = 0;
• /* Unmap the block one page at a time */
• while (size) {

• unmapped += ops->unmap(ops, iova, 4096, NULL);
  

• iova += 4096;
  

• size -= 4096;
  

• }
• iommu_flush_tlb_all(to_msm_iommu(pagetable->parent)->domain);
• return (unmapped == size) ? 0 : -EINVAL;

+}

+static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,

• struct sg_table *sgt, size_t len, int prot)
  

+{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
• struct scatterlist *sg;
• size_t mapped = 0;
• u64 addr = iova;
• unsigned int i;
• for_each_sg(sgt->sgl, sg, sgt->nents, i) {

• size_t size = sg->length;
  

• phys_addr_t phys = sg_phys(sg);
  

• /* Map the block one page at a time */
  

• while (size) {
  

• 	if (ops->map(ops, addr, phys, 4096, prot, GFP_KERNEL)) {
  

• 		msm_iommu_pagetable_unmap(mmu, iova, mapped);
  

• 		return -EINVAL;
  

• 	}
  

• 	phys += 4096;
  

• 	addr += 4096;
  

• 	size -= 4096;
  

• 	mapped += 4096;
  

• }
  

• }
• return 0;

+}

+static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) +{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct msm_iommu *iommu = to_msm_iommu(pagetable->parent);
• /*

• * If this is the last attached pagetable for the parent,
  

• * disable TTBR0 in the arm-smmu driver
  

• */
  

• if (atomic_dec_return(&iommu->pagetables) == 0)

• iommu_domain_set_attr(iommu->domain,
  

• 	DOMAIN_ATTR_PGTABLE_CFG, NULL);
  

• free_io_pgtable_ops(pagetable->pgtbl_ops);
• kfree(pagetable);

+}

+int msm_iommu_pagetable_params(struct msm_mmu *mmu,

• phys_addr_t *ttbr, int *asid)
  

+{

• struct msm_iommu_pagetable *pagetable;
• if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)

• return -EINVAL;
  

• pagetable = to_pagetable(mmu);
• if (ttbr)

• *ttbr = pagetable->ttbr;
  

• if (asid)

• *asid = pagetable->asid;
  

• return 0;

+}

+static const struct msm_mmu_funcs pagetable_funcs = {

• .map = msm_iommu_pagetable_map,
  

• .unmap = msm_iommu_pagetable_unmap,
  

• .destroy = msm_iommu_pagetable_destroy,
  

+};

+static void msm_iommu_tlb_flush_all(void *cookie) +{ +}

+static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,

• size_t granule, void *cookie)
  

+{ +}

+static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,

• unsigned long iova, size_t granule, void *cookie)
  

+{ +}

+static const struct iommu_flush_ops null_tlb_ops = {

• .tlb_flush_all = msm_iommu_tlb_flush_all,
• .tlb_flush_walk = msm_iommu_tlb_flush_walk,
• .tlb_flush_leaf = msm_iommu_tlb_flush_walk,
• .tlb_add_page = msm_iommu_tlb_add_page,

+};

+struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) +{

• struct msm_iommu *iommu = to_msm_iommu(parent);
• static int next_asid = 16;
• struct msm_iommu_pagetable *pagetable;
• struct io_pgtable_cfg cfg;
• int ret;
• /* Get the pagetable configuration from the domain */
• ret = iommu_domain_get_attr(iommu->domain,

• DOMAIN_ATTR_PGTABLE_CFG, &cfg);
  

• if (ret)

• return ERR_PTR(ret);
  

• pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
• if (!pagetable)

• return ERR_PTR(-ENOMEM);
  

• msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs,

• MSM_MMU_IOMMU_PAGETABLE);
  

• /* The incoming cfg will have the TTBR1 quirk enabled */
• cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1;
• cfg.tlb = &null_tlb_ops;
• pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1,

• &cfg, iommu->domain);
  

• if (!pagetable->pgtbl_ops) {

• kfree(pagetable);
  

• return ERR_PTR(-ENOMEM);
  

• }
• /*

• * If this is the first pagetable that we've allocated, send it back to
  

• * the arm-smmu driver as a trigger to set up TTBR0
  

• */
  

• if (atomic_inc_return(&iommu->pagetables) == 1) {

• ret = iommu_domain_set_attr(iommu->domain,
  

• 	DOMAIN_ATTR_PGTABLE_CFG, &cfg);
  

• if (ret) {
  

• 	free_io_pgtable_ops(pagetable->pgtbl_ops);
  

• 	kfree(pagetable);
  

• 	return ERR_PTR(ret);
  

• }
  

• }
• /* Needed later for TLB flush */
• pagetable->parent = parent;
• pagetable->ttbr = cfg.arm_lpae_s1_cfg.ttbr;
• pagetable->asid = next_asid;
• next_asid = (next_asid + 1) % 255;
• next_asid = min(16, next_asid);
• return &pagetable->base;

+}

static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { @@ -85,9 +271,11 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) return ERR_PTR(-ENOMEM);

iommu->domain = domain;

• msm_mmu_init(&iommu->base, dev, &funcs);

• msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); iommu_set_fault_handler(domain, msm_fault_handler, iommu);

• atomic_set(&iommu->pagetables, 0);

• ret = iommu_attach_device(iommu->domain, dev); if (ret) { kfree(iommu);

diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 3a534ee59bf6..61ade89d9e48 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -17,18 +17,26 @@ struct msm_mmu_funcs { void (*destroy)(struct msm_mmu *mmu); };

+enum msm_mmu_type {

• MSM_MMU_GPUMMU,
• MSM_MMU_IOMMU,
• MSM_MMU_IOMMU_PAGETABLE,

+};

struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev; int (*handler)(void *arg, unsigned long iova, int flags); void *arg;

• enum msm_mmu_type type;

};

static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,

• const struct msm_mmu_funcs *funcs)
  

• const struct msm_mmu_funcs *funcs, enum msm_mmu_type type)
  

{ mmu->dev = dev; mmu->funcs = funcs;

• mmu->type = type;

}

struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); @@ -41,7 +49,13 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, mmu->handler = handler; }

+struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent);

void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, dma_addr_t *tran_error);

+int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,

• int *asid);
  

#endif /* __MSM_MMU_H__ */

On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around.

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index a1d94be7883a..90c9d84e6155 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) * No lock needed in close and there won't * be any more user ioctls coming our way */

• list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node)

• list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) {

• list_del(&entry->node);
  

If you refcount ctx, what does that do for the entries in the submit queue?

"entry" here is kref'ed, but you're popping it off the list regardless of the put ends up freeing the object or not - which afaict would mean leaking the object.

On the other hand, with the current implementation an object with higher refcount with adjacent objects of single refcount would end up with dangling pointers after the put. So in itself this change seems like a net gain, but I'm wondering about the plan described in the commit message.

Regards, Bjorn

msm_submitqueue_put(entry);

• }

}

int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,

2.26.2

On Tue 01 Sep 03:42 UTC 2020, Rob Clark wrote:

On Mon, Aug 31, 2020 at 7:35 PM Bjorn Andersson bjorn.andersson@linaro.org wrote:

...

On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:

...

From: Rob Clark robdclark@chromium.org

Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around.

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index a1d94be7883a..90c9d84e6155 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -49,8 +49,10 @@ void msm_submitqueue_close(struct msm_file_private *ctx) * No lock needed in close and there won't * be any more user ioctls coming our way */

• list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node)
  

• list_for_each_entry_safe(entry, tmp, &ctx->submitqueues, node) {
  

•         list_del(&entry->node);
  

If you refcount ctx, what does that do for the entries in the submit queue?

"entry" here is kref'ed, but you're popping it off the list regardless of the put ends up freeing the object or not - which afaict would mean leaking the object.

What ends up happening is the submit has reference to submit-queue, which has reference to the ctx.. the submitqueue could be alive still pending in-flight submits (in a later patch), but dead from the PoV of userspace interface.

We aren't relying (or at least aren't in the end, and I *think* I didn't miss anything in the middle) relying on ctx->submitqueues list to clean anything up in the end, just track what is still a valid submitqueue from userspace PoV

Looks reasonable, thanks for the explanation.

BR, -R

...

On the other hand, with the current implementation an object with higher refcount with adjacent objects of single refcount would end up with dangling pointers after the put. So in itself this change seems like a net gain, but I'm wondering about the plan described in the commit message.

Regards, Bjorn

...

          msm_submitqueue_put(entry);

• }
  

}

int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,

2.26.2

On Thu, Aug 13, 2020 at 07:41:00PM -0700, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

This interface will be used for drm/msm to coordinate with the qcom_adreno_smmu_impl to enable/disable TTBR0 translation.

Once TTBR0 translation is enabled, the GPU's CP (Command Processor) will directly switch TTBR0 pgtables (and do the necessary TLB inv) synchronized to the GPU's operation. But help from the SMMU driver is needed to initially bootstrap TTBR0 translation, which cannot be done from the GPU.

Since this is a very special case, a private interface is used to avoid adding highly driver specific things to the public iommu interface.

Reviewed-by: Jordan Crouse jcrouse@codeaurora.org

Signed-off-by: Rob Clark robdclark@chromium.org

include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/linux/adreno-smmu-priv.h

diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h new file mode 100644 index 000000000000..a889f28afb42 --- /dev/null +++ b/include/linux/adreno-smmu-priv.h @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (C) 2020 Google, Inc
• */

+#ifndef __ADRENO_SMMU_PRIV_H +#define __ADRENO_SMMU_PRIV_H

+#include <linux/io-pgtable.h>

+/**

• • struct adreno_smmu_priv - private interface between adreno-smmu and GPU
• • @cookie: An opque token provided by adreno-smmu and passed

• •             back into the callbacks
    

• • @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
• • @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A

• •             NULL config disables TTBR0 translation, otherwise
    

• •             TTBR0 translation is enabled with the specified cfg
    

• • The GPU driver (drm/msm) and adreno-smmu work together for controlling
• • the GPU's SMMU instance. This is by necessity, as the GPU is directly
• • updating the SMMU for context switches, while on the other hand we do
• • not want to duplicate all of the initial setup logic from arm-smmu.
• • This private interface is used for the two drivers to coordinate. The
• • cookie and callback functions are populated when the GPU driver attaches
• • it's domain.
• */

+struct adreno_smmu_priv {

• const void *cookie;
• const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
• int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);

+};

+#endif /* __ADRENO_SMMU_PRIV_H */ \ No newline at end of file -- 2.26.2

---

Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn.

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/gpu/drm/msm/adreno/adreno_device.c | 10 ++++------ drivers/gpu/drm/msm/msm_gpu.c | 6 +++--- drivers/gpu/drm/msm/msm_gpu.h | 5 +++++ 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9eeb46bf2a5d..26664e1b30c0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -282,7 +282,7 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) int ret;

if (pdev)

• gpu = platform_get_drvdata(pdev);
  

• gpu = dev_to_gpu(&pdev->dev);
  
  

  if (!gpu) { dev_err_once(dev->dev, "no GPU device was found\n");

@@ -425,7 +425,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) static void adreno_unbind(struct device *dev, struct device *master, void *data) {

• struct msm_gpu *gpu = dev_get_drvdata(dev);

• struct msm_gpu *gpu = dev_to_gpu(dev);

  pm_runtime_force_suspend(dev); gpu->funcs->destroy(gpu);

@@ -490,16 +490,14 @@ static const struct of_device_id dt_match[] = { #ifdef CONFIG_PM static int adreno_resume(struct device *dev) {

• struct platform_device *pdev = to_platform_device(dev);
• struct msm_gpu *gpu = platform_get_drvdata(pdev);

• struct msm_gpu *gpu = dev_to_gpu(dev);

  return gpu->funcs->pm_resume(gpu);

}

static int adreno_suspend(struct device *dev) {

• struct platform_device *pdev = to_platform_device(dev);
• struct msm_gpu *gpu = platform_get_drvdata(pdev);

• struct msm_gpu *gpu = dev_to_gpu(dev);

  return gpu->funcs->pm_suspend(gpu);

} diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index d5645472b25d..6aa9e04e52e7 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -24,7 +24,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) {

• struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));

• struct msm_gpu *gpu = dev_to_gpu(dev); struct dev_pm_opp *opp;

  opp = devfreq_recommended_opp(dev, freq, flags);

@@ -45,7 +45,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, static int msm_devfreq_get_dev_status(struct device *dev, struct devfreq_dev_status *status) {

• struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));

• struct msm_gpu *gpu = dev_to_gpu(dev); ktime_t time;

  if (gpu->funcs->gpu_get_freq)

@@ -64,7 +64,7 @@ static int msm_devfreq_get_dev_status(struct device *dev,

static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) {

• struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));

• struct msm_gpu *gpu = dev_to_gpu(dev);

  if (gpu->funcs->gpu_get_freq) *freq = gpu->funcs->gpu_get_freq(gpu);

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 0db117a7339b..8bda7beaed4b 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -141,6 +141,11 @@ struct msm_gpu { struct msm_gpu_state *crashstate; };

+static inline struct msm_gpu *dev_to_gpu(struct device *dev)

That's a fairly generic name for a driver-global helper :)

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Regards, Bjorn

+{

• return dev_get_drvdata(dev);

+}

/* It turns out that all targets use the same ringbuffer size */ #define MSM_GPU_RINGBUFFER_SZ SZ_32K

#define MSM_GPU_RINGBUFFER_BLKSIZE 32

2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/gpu/drm/msm/adreno/adreno_device.c | 2 -- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 6 +++++- 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 26664e1b30c0..58e03b20e1c7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -417,8 +417,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(gpu); }

• dev_set_drvdata(dev, gpu);
• return 0;

}

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 6aa9e04e52e7..806eb0957280 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -892,7 +892,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, gpu->gpu_cx = NULL;

gpu->pdev = pdev;

• platform_set_drvdata(pdev, gpu);

• platform_set_drvdata(pdev, &gpu->adreno_smmu);

  msm_devfreq_init(gpu);

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 8bda7beaed4b..f91b141add75 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -7,6 +7,7 @@ #ifndef __MSM_GPU_H__ #define __MSM_GPU_H__

+#include <linux/adreno-smmu-priv.h> #include <linux/clk.h> #include <linux/interconnect.h> #include <linux/pm_opp.h> @@ -73,6 +74,8 @@ struct msm_gpu { struct platform_device *pdev; const struct msm_gpu_funcs *funcs;

• struct adreno_smmu_priv adreno_smmu;
• /* performance counters (hw & sw): */ spinlock_t perf_lock; bool perfcntr_active;

@@ -143,7 +146,8 @@ struct msm_gpu {

static inline struct msm_gpu *dev_to_gpu(struct device *dev) {

• return dev_get_drvdata(dev);

• struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
• return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);

}

/* It turns out that all targets use the same ringbuffer size */

2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

Sprinkle a few `const`s where helpers don't need write access.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 59ff3fc5c6c8..27c83333fc50 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -377,7 +377,7 @@ struct arm_smmu_master_cfg { s16 smendx[]; };

-static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg) { u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | @@ -398,13 +398,13 @@ static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) return tcr; }

-static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg) { return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) | FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM); }

-static inline u32 arm_smmu_lpae_vtcr(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg) { return ARM_SMMU_VTCR_RES1 | FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) | -- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Add a special implementation for the SMMU attached to most Adreno GPU target triggered from the qcom,adreno-smmu compatible string.

The new Adreno SMMU implementation will enable split pagetables (TTBR1) for the domain attached to the GPU device (SID 0) and hard code it context bank 0 so the GPU hardware can implement per-instance pagetables.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Co-developed-by: Rob Clark robdclark@chromium.org Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 3 files changed, 151 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c index 88f17cc33023..d199b4bff15d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) of_device_is_compatible(np, "qcom,sm8250-smmu-500")) return qcom_smmu_impl_init(smmu);

• if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu"))

• return qcom_adreno_smmu_impl_init(smmu);
  

• if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) smmu->impl = &mrvl_mmu500_impl;

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index be4318044f96..5640d9960610 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -3,6 +3,7 @@

• Copyright (c) 2019, The Linux Foundation. All rights reserved.

*/

+#include <linux/adreno-smmu-priv.h> #include <linux/of_device.h> #include <linux/qcom_scm.h>

@@ -12,6 +13,132 @@ struct qcom_smmu { struct arm_smmu_device smmu; };

+#define QCOM_ADRENO_SMMU_GPU_SID 0

+static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) +{

• struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
• int i;
• /*

• * The GPU will always use SID 0 so that is a handy way to uniquely
  

• * identify it and configure it for per-instance pagetables
  

• */
  

• for (i = 0; i < fwspec->num_ids; i++) {

• u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
  

• if (sid == QCOM_ADRENO_SMMU_GPU_SID)
  

• 	return true;
  

• }
• return false;

+}

+static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(

• const void *cookie)
  

+{

• struct arm_smmu_domain *smmu_domain = (void *)cookie;
• struct io_pgtable *pgtable =

• io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
  

• return &pgtable->cfg;

+}

+/*

• • Local implementation to configure TTBR0 with the specified pagetable config.
• • The GPU driver will call this to enable TTBR0 when per-instance pagetables
• • are active
• */

+static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,

• const struct io_pgtable_cfg *pgtbl_cfg)
  

+{

• struct arm_smmu_domain *smmu_domain = (void *)cookie;
• struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
• struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
• struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
• /* The domain must have split pagetables already enabled */
• if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)

• return -EINVAL;
  

• /* If the pagetable config is NULL, disable TTBR0 */
• if (!pgtbl_cfg) {

• /* Do nothing if it is already disabled */
  

• if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
  

• 	return -EINVAL;
  

• /* Set TCR to the original configuration */
  

• cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
  

• cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
  

• } else {

• u32 tcr = cb->tcr[0];
  

• /* Don't call this again if TTBR0 is already enabled */
  

• if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
  

• 	return -EINVAL;
  

• tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
  

• tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
  

• cb->tcr[0] = tcr;
  

• cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
  

• cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
  

• }
• arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
• return 0;

+}

+static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,

• struct device *dev, int start, int count)
  

+{

• struct arm_smmu_device *smmu = smmu_domain->smmu;
• /*

• * Assign context bank 0 to the GPU device so the GPU hardware can
  

• * switch pagetables
  

• */
  

• if (qcom_adreno_smmu_is_gpu_device(dev)) {

• start = 0;
  

• count = 1;
  

• } else {

• start = 1;
  

• }
• return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);

+}

+static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,

• struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
  

+{

• struct adreno_smmu_priv *priv;
• /* Only enable split pagetables for the GPU device (SID 0) */
• if (!qcom_adreno_smmu_is_gpu_device(dev))

• return 0;
  

• /*

• * All targets that use the qcom,adreno-smmu compatible string *should*
  

• * be AARCH64 stage 1 but double check because the arm-smmu code assumes
  

• * that is the case when the TTBR1 quirk is enabled
  

• */
  

• if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&

•    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
  

• pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
  

• /*

• * Initialize private interface with GPU:
  

• */
  

• priv = dev_get_drvdata(dev);
• priv->cookie = smmu_domain;
• priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
• priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
• return 0;

+}

static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, { .compatible = "qcom,mdp4" }, @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { .reset = qcom_smmu500_reset, };

-struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) +static const struct arm_smmu_impl qcom_adreno_smmu_impl = {

• .init_context = qcom_adreno_smmu_init_context,
• .def_domain_type = qcom_smmu_def_domain_type,
• .reset = qcom_smmu500_reset,
• .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,

+};

+static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,

• const struct arm_smmu_impl *impl)
  

{ struct qcom_smmu *qsmmu;

@@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)

qsmmu->smmu = *smmu;

• qsmmu->smmu.impl = &qcom_smmu_impl;

• qsmmu->smmu.impl = impl; devm_kfree(smmu->dev, smmu);

  return &qsmmu->smmu;

}

+struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) +{

• return qcom_smmu_create(smmu, &qcom_smmu_impl);

+}

+struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) +{

• return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

+} diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 27c83333fc50..cd75a33967bb 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu);

void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); -- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Every Qcom Adreno GPU has an embedded SMMU for its own use. These devices depend on unique features such as split pagetables, different stall/halt requirements and other settings. Identify them with a compatible string so that they can be identified in the arm-smmu implementation specific code.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Rob Clark robdclark@chromium.org

---

Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..5ec5d0d691f6 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -40,6 +40,10 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500

•  - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
  

•    items:
  

•      - const: qcom,adreno-smmu
  

•      - const: qcom,smmu-v2
   - description: Marvell SoCs implementing "arm,mmu-500"
     items:
       - const: marvell,ap806-smmu-500
  

-- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Co-developed-by: Rob Clark robdclark@chromium.org Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/msm_drv.c | 3 ++- drivers/gpu/drm/msm/msm_drv.h | 20 ++++++++++++++++++++ drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 6 +++--- drivers/gpu/drm/msm/msm_gpu.h | 1 + drivers/gpu/drm/msm/msm_submitqueue.c | 3 +++ 6 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 7d641c7e3514..01845a3b8d52 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -594,6 +594,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) if (!ctx) return -ENOMEM;

• kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx);

  ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;

@@ -615,7 +616,7 @@ static int msm_open(struct drm_device *dev, struct drm_file *file) static void context_close(struct msm_file_private *ctx) { msm_submitqueue_close(ctx);

• kfree(ctx);

• msm_file_private_put(ctx);

}

static void msm_postclose(struct drm_device *dev, struct drm_file *file) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index af259b0573ea..4561bfb5e745 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -57,6 +57,7 @@ struct msm_file_private { struct list_head submitqueues; int queueid; struct msm_gem_address_space *aspace;

• struct kref ref;

};

enum msm_mdp_plane_property { @@ -428,6 +429,25 @@ void msm_submitqueue_close(struct msm_file_private *ctx);

void msm_submitqueue_destroy(struct kref *kref);

+static inline void __msm_file_private_destroy(struct kref *kref) +{

• struct msm_file_private *ctx = container_of(kref,

• struct msm_file_private, ref);
  

• kfree(ctx);

+}

+static inline void msm_file_private_put(struct msm_file_private *ctx) +{

• kref_put(&ctx->ref, __msm_file_private_destroy);

+}

+static inline struct msm_file_private *msm_file_private_get(

• struct msm_file_private *ctx)

+{

• kref_get(&ctx->ref);
• return ctx;

+}

#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 972490b14ba5..9c573c4269cb 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -142,6 +142,7 @@ struct msm_gem_submit { bool valid; /* true if no cmdstream patching needed */ bool in_rb; /* "sudo" mode, copy cmds into RB */ struct msm_ringbuffer *ring;

• struct msm_file_private *ctx; unsigned int nr_cmds; unsigned int nr_bos; u32 ident; /* A "identifier" for the submit for logging */

diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 8cb9aa15ff90..1464b04d25d3 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -27,7 +27,7 @@ #define BO_PINNED 0x2000

static struct msm_gem_submit *submit_create(struct drm_device *dev,

• struct msm_gpu *gpu, struct msm_gem_address_space *aspace,
  

• struct msm_gpu *gpu,
  

  struct msm_gpu_submitqueue *queue, uint32_t nr_bos, uint32_t nr_cmds)

{ @@ -43,7 +43,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, return NULL;

submit->dev = dev;

• submit->aspace = aspace;

• submit->aspace = queue->ctx->aspace; submit->gpu = gpu; submit->fence = NULL; submit->cmd = (void *)&submit->bos[nr_bos];

@@ -677,7 +677,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, } }

• submit = submit_create(dev, gpu, ctx->aspace, queue, args->nr_bos,

• submit = submit_create(dev, gpu, queue, args->nr_bos, args->nr_cmds); if (!submit) { ret = -ENOMEM;

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index f91b141add75..97c527e98391 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -190,6 +190,7 @@ struct msm_gpu_submitqueue { u32 flags; u32 prio; int faults;

• struct msm_file_private *ctx; struct list_head node; struct kref ref;

}; diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index 90c9d84e6155..c3d206105d28 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -12,6 +12,8 @@ void msm_submitqueue_destroy(struct kref *kref) struct msm_gpu_submitqueue *queue = container_of(kref, struct msm_gpu_submitqueue, ref);

• msm_file_private_put(queue->ctx);
• kfree(queue);

}

@@ -83,6 +85,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,

write_lock(&ctx->queuelock);

• queue->ctx = msm_file_private_get(ctx); queue->id = ctx->queueid++;

  if (id)

-- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Now that we can get the ctx from the submitqueue, the extra arg is redundant.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org [split out of previous patch to reduce churny noise] Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++--- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- drivers/gpu/drm/msm/msm_gem_submit.c | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 9 ++++----- drivers/gpu/drm/msm/msm_gpu.h | 6 ++---- 7 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 9e63a190642c..eff2439ea57b 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -43,8 +43,7 @@ static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); }

-static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx)

+static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct msm_drm_private *priv = gpu->dev->dev_private; struct msm_ringbuffer *ring = submit->ring; @@ -57,7 +56,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:

• 	if (priv->lastctx == ctx)
  

• 	if (priv->lastctx == submit->queue->ctx)
  	break;
  /* fall-thru */
  

  case MSM_SUBMIT_CMD_BUF:

@@ -103,8 +102,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit msm_gpu_retire(gpu); }

-static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx)

+static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); @@ -114,7 +112,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) { priv->lastctx = NULL;

• a5xx_submit_in_rb(gpu, submit, ctx);
  

• a5xx_submit_in_rb(gpu, submit);
  

  return; }

@@ -148,7 +146,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:

• 	if (priv->lastctx == ctx)
  

• 	if (priv->lastctx == submit->queue->ctx)
  	break;
  /* fall-thru */
  

  case MSM_SUBMIT_CMD_BUF:

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c5a3e4d4c007..5eabb0109577 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -81,8 +81,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_RING(ring, upper_32_bits(iova)); }

-static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx)

+static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; struct msm_drm_private *priv = gpu->dev->dev_private; @@ -115,7 +114,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:

• 	if (priv->lastctx == ctx)
  

• 	if (priv->lastctx == submit->queue->ctx)
  	break;
  /* fall-thru */
  

  case MSM_SUBMIT_CMD_BUF:

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index d2dbb6968cba..533a34b4cce2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -457,8 +457,7 @@ void adreno_recover(struct msm_gpu *gpu) } }

-void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx)
  

+void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct msm_drm_private *priv = gpu->dev->dev_private; @@ -472,7 +471,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */

• 	if (priv->lastctx == ctx)
  

• 	if (priv->lastctx == submit->queue->ctx)
  	break;
  /* fall-thru */
  

  case MSM_SUBMIT_CMD_BUF:

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e55abae365b5..848632758450 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -269,8 +269,7 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova); int adreno_hw_init(struct msm_gpu *gpu); void adreno_recover(struct msm_gpu *gpu); -void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx);
  

+void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 1464b04d25d3..aa5c60a7132d 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -785,7 +785,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, } }

• msm_gpu_submit(gpu, submit, ctx);

• msm_gpu_submit(gpu, submit);

  args->fence = submit->fence->seqno;

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 806eb0957280..e1a3cbe25a0c 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -520,7 +520,7 @@ static void recover_worker(struct work_struct *work) struct msm_ringbuffer *ring = gpu->rb[i];

	list_for_each_entry(submit, &ring->submits, node)

• 		gpu->funcs->submit(gpu, submit, NULL);
  

• 		gpu->funcs->submit(gpu, submit);
  

  } }

@@ -747,8 +747,7 @@ void msm_gpu_retire(struct msm_gpu *gpu) }

/* add bo's to gpu's ring, and kick gpu: */ -void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx)
  

+void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct drm_device *dev = gpu->dev; struct msm_drm_private *priv = dev->dev_private; @@ -788,8 +787,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); }

• gpu->funcs->submit(gpu, submit, ctx);
• priv->lastctx = ctx;

• gpu->funcs->submit(gpu, submit);

• priv->lastctx = submit->queue->ctx;

  hangcheck_timer_reset(gpu);

} diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 97c527e98391..1f96ac0d9049 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -45,8 +45,7 @@ struct msm_gpu_funcs { int (*hw_init)(struct msm_gpu *gpu); int (*pm_suspend)(struct msm_gpu *gpu); int (*pm_resume)(struct msm_gpu *gpu);

• void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• 	struct msm_file_private *ctx);
  

• void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit); void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); irqreturn_t (*irq)(struct msm_gpu *irq); struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);

@@ -290,8 +289,7 @@ int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);

void msm_gpu_retire(struct msm_gpu *gpu); -void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

• struct msm_file_private *ctx);
  

+void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);

int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, -- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables).

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++++++++-- drivers/gpu/drm/msm/msm_iommu.c | 7 +++++++ 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 533a34b4cce2..34e6242c1767 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -192,9 +192,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type); struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu); struct msm_gem_address_space *aspace;

• u64 start, size;

• aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,

• 0xffffffff - SZ_16M);
  

• /*

• * Use the aperture start or SZ_16M, whichever is greater. This will
  

• * ensure that we align with the allocated pagetable range while still
  

• * allowing room in the lower 32 bits for GMEM and whatnot
  

• */
  

• start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);

• size = iommu->geometry.aperture_end - start + 1;

• aspace = msm_gem_address_space_create(mmu, "gpu",

• start & GENMASK(48, 0), size);
  
  

  if (IS_ERR(aspace) && !IS_ERR(mmu)) mmu->funcs->destroy(mmu);

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 3a381a9674c9..1b6635504069 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -36,6 +36,10 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, struct msm_iommu *iommu = to_msm_iommu(mmu); size_t ret;

• /* The arm-smmu driver expects the addresses to be sign extended */
• if (iova & BIT_ULL(48))

• iova |= GENMASK_ULL(63, 49);
  

• ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot); WARN_ON(!ret);

@@ -46,6 +50,9 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) { struct msm_iommu *iommu = to_msm_iommu(mmu);

• if (iova & BIT_ULL(48))

• iova |= GENMASK_ULL(63, 49);
  

• iommu_unmap(iommu->domain, iova, len);

  return 0;

-- 2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/msm_gpummu.c | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 199 ++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/msm_mmu.h | 16 ++- 3 files changed, 214 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c index 310a31b05faa..aab121f4beb7 100644 --- a/drivers/gpu/drm/msm/msm_gpummu.c +++ b/drivers/gpu/drm/msm/msm_gpummu.c @@ -102,7 +102,7 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) }

gpummu->gpu = gpu;

• msm_mmu_init(&gpummu->base, dev, &funcs);

• msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU);

  return &gpummu->base;

} diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 1b6635504069..697cc0a059d6 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -4,15 +4,210 @@

• Author: Rob Clark robdclark@gmail.com

*/

+#include <linux/adreno-smmu-priv.h> +#include <linux/io-pgtable.h> #include "msm_drv.h" #include "msm_mmu.h"

struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain;

• atomic_t pagetables;

};

#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)

+struct msm_iommu_pagetable {

• struct msm_mmu base;
• struct msm_mmu *parent;
• struct io_pgtable_ops *pgtbl_ops;
• phys_addr_t ttbr;
• u32 asid;

+}; +static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu) +{

• return container_of(mmu, struct msm_iommu_pagetable, base);

+}

+static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova,

• size_t size)
  

+{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
• size_t unmapped = 0;
• /* Unmap the block one page at a time */
• while (size) {

• unmapped += ops->unmap(ops, iova, 4096, NULL);
  

• iova += 4096;
  

• size -= 4096;
  

• }
• iommu_flush_tlb_all(to_msm_iommu(pagetable->parent)->domain);
• return (unmapped == size) ? 0 : -EINVAL;

+}

+static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,

• struct sg_table *sgt, size_t len, int prot)
  

+{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
• struct scatterlist *sg;
• size_t mapped = 0;
• u64 addr = iova;
• unsigned int i;
• for_each_sg(sgt->sgl, sg, sgt->nents, i) {

• size_t size = sg->length;
  

• phys_addr_t phys = sg_phys(sg);
  

• /* Map the block one page at a time */
  

• while (size) {
  

• 	if (ops->map(ops, addr, phys, 4096, prot, GFP_KERNEL)) {
  

• 		msm_iommu_pagetable_unmap(mmu, iova, mapped);
  

• 		return -EINVAL;
  

• 	}
  

• 	phys += 4096;
  

• 	addr += 4096;
  

• 	size -= 4096;
  

• 	mapped += 4096;
  

• }
  

• }
• return 0;

+}

+static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) +{

• struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
• struct msm_iommu *iommu = to_msm_iommu(pagetable->parent);
• struct adreno_smmu_priv *adreno_smmu =

• dev_get_drvdata(pagetable->parent->dev);
  

• /*

• * If this is the last attached pagetable for the parent,
  

• * disable TTBR0 in the arm-smmu driver
  

• */
  

• if (atomic_dec_return(&iommu->pagetables) == 0)

• adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL);
  

• free_io_pgtable_ops(pagetable->pgtbl_ops);
• kfree(pagetable);

+}

+int msm_iommu_pagetable_params(struct msm_mmu *mmu,

• phys_addr_t *ttbr, int *asid)
  

+{

• struct msm_iommu_pagetable *pagetable;
• if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)

• return -EINVAL;
  

• pagetable = to_pagetable(mmu);
• if (ttbr)

• *ttbr = pagetable->ttbr;
  

• if (asid)

• *asid = pagetable->asid;
  

• return 0;

+}

+static const struct msm_mmu_funcs pagetable_funcs = {

• .map = msm_iommu_pagetable_map,
  

• .unmap = msm_iommu_pagetable_unmap,
  

• .destroy = msm_iommu_pagetable_destroy,
  

+};

+static void msm_iommu_tlb_flush_all(void *cookie) +{ +}

+static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,

• size_t granule, void *cookie)
  

+{ +}

+static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,

• unsigned long iova, size_t granule, void *cookie)
  

+{ +}

+static const struct iommu_flush_ops null_tlb_ops = {

• .tlb_flush_all = msm_iommu_tlb_flush_all,
• .tlb_flush_walk = msm_iommu_tlb_flush_walk,
• .tlb_flush_leaf = msm_iommu_tlb_flush_walk,
• .tlb_add_page = msm_iommu_tlb_add_page,

+};

+struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) +{

• struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev);
• struct msm_iommu *iommu = to_msm_iommu(parent);
• struct msm_iommu_pagetable *pagetable;
• const struct io_pgtable_cfg *ttbr1_cfg = NULL;
• struct io_pgtable_cfg ttbr0_cfg;
• int ret;
• /* Get the pagetable configuration from the domain */
• if (adreno_smmu->cookie)

• ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
  

• if (!ttbr1_cfg)

• return ERR_PTR(-ENODEV);
  

• pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
• if (!pagetable)

• return ERR_PTR(-ENOMEM);
  

• msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs,

• MSM_MMU_IOMMU_PAGETABLE);
  

• /* Clone the TTBR1 cfg as starting point for TTBR0 cfg: */
• ttbr0_cfg = *ttbr1_cfg;
• /* The incoming cfg will have the TTBR1 quirk enabled */
• ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1;
• ttbr0_cfg.tlb = &null_tlb_ops;
• pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1,

• &ttbr0_cfg, iommu->domain);
  

• if (!pagetable->pgtbl_ops) {

• kfree(pagetable);
  

• return ERR_PTR(-ENOMEM);
  

• }
• /*

• * If this is the first pagetable that we've allocated, send it back to
  

• * the arm-smmu driver as a trigger to set up TTBR0
  

• */
  

• if (atomic_inc_return(&iommu->pagetables) == 1) {

• ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
  

• if (ret) {
  

• 	free_io_pgtable_ops(pagetable->pgtbl_ops);
  

• 	kfree(pagetable);
  

• 	return ERR_PTR(ret);
  

• }
  

• }
• /* Needed later for TLB flush */
• pagetable->parent = parent;
• pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr;
• /*

• * TODO we would like each set of page tables to have a unique ASID
  

• * to optimize TLB invalidation.  But iommu_flush_tlb_all() will
  

• * end up flushing the ASID used for TTBR1 pagetables, which is not
  

• * what we want.  So for now just use the same ASID as TTBR1.
  

• */
  

• pagetable->asid = 0;
• return &pagetable->base;

+}

static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { @@ -85,9 +280,11 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) return ERR_PTR(-ENOMEM);

iommu->domain = domain;

• msm_mmu_init(&iommu->base, dev, &funcs);

• msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); iommu_set_fault_handler(domain, msm_fault_handler, iommu);

• atomic_set(&iommu->pagetables, 0);

• ret = iommu_attach_device(iommu->domain, dev); if (ret) { kfree(iommu);

diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 3a534ee59bf6..61ade89d9e48 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -17,18 +17,26 @@ struct msm_mmu_funcs { void (*destroy)(struct msm_mmu *mmu); };

+enum msm_mmu_type {

• MSM_MMU_GPUMMU,
• MSM_MMU_IOMMU,
• MSM_MMU_IOMMU_PAGETABLE,

+};

struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev; int (*handler)(void *arg, unsigned long iova, int flags); void *arg;

• enum msm_mmu_type type;

};

static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,

• const struct msm_mmu_funcs *funcs)
  

• const struct msm_mmu_funcs *funcs, enum msm_mmu_type type)
  

{ mmu->dev = dev; mmu->funcs = funcs;

• mmu->type = type;

}

struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); @@ -41,7 +49,13 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, mmu->handler = handler; }

+struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent);

void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, dma_addr_t *tran_error);

+int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,

• int *asid);
  

#endif /* __MSM_MMU_H__ */

2.26.2

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces.

The default will return a pointer to the global address space.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/msm_drv.c | 13 +++++++------ drivers/gpu/drm/msm/msm_drv.h | 5 +++++ drivers/gpu/drm/msm/msm_gem_vma.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 5 +++++ 5 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 01845a3b8d52..8e70d220bba8 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx);

• ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;

• ctx->aspace = msm_gpu_create_private_address_space(priv->gpu); file->driver_priv = ctx;

  return 0;

@@ -780,18 +780,19 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, }

static int msm_ioctl_gem_info_iova(struct drm_device *dev,

• struct drm_gem_object *obj, uint64_t *iova)
  

• struct drm_file *file, struct drm_gem_object *obj,
  

• uint64_t *iova)
  

{

• struct msm_drm_private *priv = dev->dev_private;

• struct msm_file_private *ctx = file->driver_priv;

• if (!priv->gpu)

• if (!ctx->aspace) return -EINVAL;

  /*

  • Don't pin the memory here - just get an address so that userspace can
  • be productive

  */

• return msm_gem_get_iova(obj, priv->gpu->aspace, iova);

• return msm_gem_get_iova(obj, ctx->aspace, iova);

}

static int msm_ioctl_gem_info(struct drm_device *dev, void *data, @@ -830,7 +831,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data, args->value = msm_gem_mmap_offset(obj); break; case MSM_INFO_GET_IOVA:

• ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
  

• ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
  

  break; case MSM_INFO_SET_NAME: /* length check should leave room for terminating null: */

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 4561bfb5e745..2ca9c3c03845 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -249,6 +249,10 @@ int msm_gem_map_vma(struct msm_gem_address_space *aspace, void msm_gem_close_vma(struct msm_gem_address_space *aspace, struct msm_gem_vma *vma);

+struct msm_gem_address_space * +msm_gem_address_space_get(struct msm_gem_address_space *aspace);

void msm_gem_address_space_put(struct msm_gem_address_space *aspace);

struct msm_gem_address_space * @@ -434,6 +438,7 @@ static inline void __msm_file_private_destroy(struct kref *kref) struct msm_file_private *ctx = container_of(kref, struct msm_file_private, ref);

• msm_gem_address_space_put(ctx->aspace); kfree(ctx);

}

diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c index 5f6a11211b64..29cc1305cf37 100644 --- a/drivers/gpu/drm/msm/msm_gem_vma.c +++ b/drivers/gpu/drm/msm/msm_gem_vma.c @@ -27,6 +27,15 @@ void msm_gem_address_space_put(struct msm_gem_address_space *aspace) kref_put(&aspace->kref, msm_gem_address_space_destroy); }

+struct msm_gem_address_space * +msm_gem_address_space_get(struct msm_gem_address_space *aspace) +{

• if (!IS_ERR_OR_NULL(aspace))

• kref_get(&aspace->kref);
  

• return aspace;

+}

/* Actually unmap memory for the vma */ void msm_gem_purge_vma(struct msm_gem_address_space *aspace, struct msm_gem_vma *vma) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index e1a3cbe25a0c..951850804d77 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -823,6 +823,28 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) return 0; }

+/* Return a new address space for a msm_drm_private instance */ +struct msm_gem_address_space * +msm_gpu_create_private_address_space(struct msm_gpu *gpu) +{

• struct msm_gem_address_space *aspace = NULL;
• if (!gpu)

• return NULL;
  

• /*

• * If the target doesn't support private address spaces then return
  

• * the global one
  

• */
  

• if (gpu->funcs->create_private_address_space)

• aspace = gpu->funcs->create_private_address_space(gpu);
  

• if (IS_ERR_OR_NULL(aspace))

• aspace = msm_gem_address_space_get(gpu->aspace);
  

• return aspace;

+}

int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f96ac0d9049..4052a18e18c2 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -65,6 +65,8 @@ struct msm_gpu_funcs { void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); struct msm_gem_address_space *(*create_address_space) (struct msm_gpu *gpu, struct platform_device *pdev);

• struct msm_gem_address_space *(*create_private_address_space)

• (struct msm_gpu *gpu);
  

};

struct msm_gpu { @@ -295,6 +297,9 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config);

+struct msm_gem_address_space * +msm_gpu_create_private_address_space(struct msm_gpu *gpu);

void msm_gpu_cleanup(struct msm_gpu *gpu);

struct msm_gpu *adreno_load_gpu(struct drm_device *dev);

2.26.2

On 8/14/2020 8:11 AM, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Add support for using per-instance pagetables if all the dependencies are available.

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 3 files changed, 72 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5eabb0109577..9653ac9b3cb8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -81,6 +81,56 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_RING(ring, upper_32_bits(iova)); }

+static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,

• struct msm_ringbuffer *ring, struct msm_file_private *ctx)
  

+{

• phys_addr_t ttbr;
• u32 asid;
• u64 memptr = rbmemptr(ring, ttbr0);
• if (ctx == a6xx_gpu->cur_ctx)

• return;
  

• if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))

• return;
  

• /* Execute the table update */
• OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
• /*

• * For now ignore the asid since the smmu driver uses a TLBIASID to
  

• * flush the TLB when we use iommu_flush_tlb_all() and the smmu driver
  

• * isn't aware that the asid changed.  Instead, keep the default asid
  

• * (0, same as the context bank) to make sure the TLB is properly
  

• * flushed.
  

• */
  

• OUT_RING(ring,

• CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
  

• CP_SMMU_TABLE_UPDATE_1_ASID(0));
  

• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
• /*

• * Write the new TTBR0 to the memstore. This is good for debugging.
  

• */
  

• OUT_PKT7(ring, CP_MEM_WRITE, 4);
• OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
• OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
• OUT_RING(ring, lower_32_bits(ttbr));
• OUT_RING(ring, (0 << 16) | upper_32_bits(ttbr));

why (0 << 16) is required here?

• /*

• * And finally, trigger a uche flush to be sure there isn't anything
  

• * lingering in that part of the GPU
  

• */
  

• OUT_PKT7(ring, CP_EVENT_WRITE, 1);
• OUT_RING(ring, 0x31);

This may be unnecessary, but no harm in keeping it. SMMU_TABLE_UPDATE is supposed to do a UCHE flush.

-Akhil

• a6xx_gpu->cur_ctx = ctx;

+}

• static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;

@@ -90,6 +140,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = submit->ring; unsigned int i;

• a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
• get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start));

@@ -696,6 +748,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0];

• a6xx_gpu->cur_ctx = NULL;
• /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);

@@ -1008,6 +1062,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; }

+static struct msm_gem_address_space * +a6xx_create_private_address_space(struct msm_gpu *gpu) +{

• struct msm_gem_address_space *aspace = NULL;
• struct msm_mmu *mmu;
• mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
• if (!IS_ERR(mmu))

• aspace = msm_gem_address_space_create(mmu,
  

• 	"gpu", 0x100000000ULL, 0x1ffffffffULL);
  

• return aspace;

+}

• static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param,

@@ -1031,6 +1100,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = adreno_iommu_create_address_space,

• .create_private_address_space = a6xx_create_private_address_space,
  

  }, .get_timestamp = a6xx_get_timestamp, };

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 03ba60d5b07f..da22d7549d9b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -19,6 +19,7 @@ struct a6xx_gpu { uint64_t sqe_iova;

struct msm_ringbuffer *cur_ring;

• struct msm_file_private *cur_ctx;

  struct a6xx_gmu gmu; };

diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 7764373d0ed2..0987d6bf848c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t fence;

volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];

• volatile u64 ttbr0; };

  struct msm_ringbuffer {

On Mon, Aug 17, 2020 at 09:10:46PM +0530, Akhil P Oommen wrote:

On 8/14/2020 8:11 AM, Rob Clark wrote:

...

From: Jordan Crouse jcrouse@codeaurora.org

Add support for using per-instance pagetables if all the dependencies are available.

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 3 files changed, 72 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5eabb0109577..9653ac9b3cb8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -81,6 +81,56 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_RING(ring, upper_32_bits(iova)); } +static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,

• struct msm_ringbuffer *ring, struct msm_file_private *ctx)
  

+{

• phys_addr_t ttbr;
• u32 asid;
• u64 memptr = rbmemptr(ring, ttbr0);
• if (ctx == a6xx_gpu->cur_ctx)

• return;
  

• if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))

• return;
  

• /* Execute the table update */
• OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
• /*

• * For now ignore the asid since the smmu driver uses a TLBIASID to
  

• * flush the TLB when we use iommu_flush_tlb_all() and the smmu driver
  

• * isn't aware that the asid changed.  Instead, keep the default asid
  

• * (0, same as the context bank) to make sure the TLB is properly
  

• * flushed.
  

• */
  

• OUT_RING(ring,

• CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
  

• CP_SMMU_TABLE_UPDATE_1_ASID(0));
  

• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
• /*

• * Write the new TTBR0 to the memstore. This is good for debugging.
  

• */
  

• OUT_PKT7(ring, CP_MEM_WRITE, 4);
• OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
• OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
• OUT_RING(ring, lower_32_bits(ttbr));
• OUT_RING(ring, (0 << 16) | upper_32_bits(ttbr));

why (0 << 16) is required here?

Because that is the ASID we are using and we would want the debug TTBR0 to match the hardware as closely as possible.

...

• /*

• * And finally, trigger a uche flush to be sure there isn't anything
  

• * lingering in that part of the GPU
  

• */
  

• OUT_PKT7(ring, CP_EVENT_WRITE, 1);
• OUT_RING(ring, 0x31);

This may be unnecessary, but no harm in keeping it. SMMU_TABLE_UPDATE is supposed to do a UCHE flush.

Correct but I think it is wise to try to match the downstream sequence as much as possible.

Jordan

-Akhil

...

• a6xx_gpu->cur_ctx = ctx;

+}

static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; @@ -90,6 +140,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = submit->ring; unsigned int i;

• a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
• get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start));

@@ -696,6 +748,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0];

• a6xx_gpu->cur_ctx = NULL;
• /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);

@@ -1008,6 +1062,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; } +static struct msm_gem_address_space * +a6xx_create_private_address_space(struct msm_gpu *gpu) +{

• struct msm_gem_address_space *aspace = NULL;
• struct msm_mmu *mmu;
• mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
• if (!IS_ERR(mmu))

• aspace = msm_gem_address_space_create(mmu,
  

• 	"gpu", 0x100000000ULL, 0x1ffffffffULL);
  

• return aspace;

+}

static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -1031,6 +1100,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = adreno_iommu_create_address_space,

• .create_private_address_space = a6xx_create_private_address_space,
  

  }, .get_timestamp = a6xx_get_timestamp,

}; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 03ba60d5b07f..da22d7549d9b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -19,6 +19,7 @@ struct a6xx_gpu { uint64_t sqe_iova; struct msm_ringbuffer *cur_ring;

• struct msm_file_private *cur_ctx; struct a6xx_gmu gmu;

}; diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 7764373d0ed2..0987d6bf848c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t fence; volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];

• volatile u64 ttbr0;

}; struct msm_ringbuffer {

On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

From: Rob Clark robdclark@chromium.org

In $debugfs/gem we already show any vma(s) associated with an object. Also show process names if the vma's address space is a per-process address space.

Reviewed-by: Bjorn Andersson bjorn.andersson@linaro.org

Signed-off-by: Rob Clark robdclark@chromium.org

drivers/gpu/drm/msm/msm_drv.c | 2 +- drivers/gpu/drm/msm/msm_gem.c | 25 +++++++++++++++++++++---- drivers/gpu/drm/msm/msm_gem.h | 5 +++++ drivers/gpu/drm/msm/msm_gem_vma.c | 1 + drivers/gpu/drm/msm/msm_gpu.c | 8 +++++--- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 6 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 8e70d220bba8..8d5c4f98c332 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -597,7 +597,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) kref_init(&ctx->ref); msm_submitqueue_init(dev, ctx);

• ctx->aspace = msm_gpu_create_private_address_space(priv->gpu);

• ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); file->driver_priv = ctx;

  return 0;

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 3cb7aeb93fd3..76a6c5271e57 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -842,11 +842,28 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m)

seq_puts(m, "      vmas:");

• list_for_each_entry(vma, &msm_obj->vmas, list)
  

• 	seq_printf(m, " [%s: %08llx,%s,inuse=%d]",
  

• 		vma->aspace != NULL ? vma->aspace->name : NULL,
  

• 		vma->iova, vma->mapped ? "mapped" : "unmapped",
  

• list_for_each_entry(vma, &msm_obj->vmas, list) {
  

• 	const char *name, *comm;
  

• 	if (vma->aspace) {
  

• 		struct msm_gem_address_space *aspace = vma->aspace;
  

• 		struct task_struct *task =
  

• 			get_pid_task(aspace->pid, PIDTYPE_PID);
  

• 		if (task) {
  

• 			comm = kstrdup(task->comm, GFP_KERNEL);
  

• 		} else {
  

• 			comm = NULL;
  

• 		}
  

• 		name = aspace->name;
  

• 	} else {
  

• 		name = comm = NULL;
  

• 	}
  

• 	seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s,inuse=%d]",
  

• 		name, comm ? ":" : "", comm ? comm : "",
  

• 		vma->aspace, vma->iova,
  

• 		vma->mapped ? "mapped" : "unmapped",
  	vma->inuse);
  

• 	kfree(comm);
  

• }
  
  

  seq_puts(m, "\n"); }

diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 9c573c4269cb..7b1c7a5f8eef 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -24,6 +24,11 @@ struct msm_gem_address_space { spinlock_t lock; /* Protects drm_mm node allocation/removal */ struct msm_mmu *mmu; struct kref kref;

• /* For address spaces associated with a specific process, this

• * will be non-NULL:
  

• */
  

• struct pid *pid;

};

struct msm_gem_vma { diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c index 29cc1305cf37..80a8a266d68f 100644 --- a/drivers/gpu/drm/msm/msm_gem_vma.c +++ b/drivers/gpu/drm/msm/msm_gem_vma.c @@ -17,6 +17,7 @@ msm_gem_address_space_destroy(struct kref *kref) drm_mm_takedown(&aspace->mm); if (aspace->mmu) aspace->mmu->funcs->destroy(aspace->mmu);

• put_pid(aspace->pid); kfree(aspace);

}

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 951850804d77..ac8961187a73 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -825,10 +825,9 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)

/* Return a new address space for a msm_drm_private instance */ struct msm_gem_address_space * -msm_gpu_create_private_address_space(struct msm_gpu *gpu) +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) { struct msm_gem_address_space *aspace = NULL;

• if (!gpu) return NULL;

@@ -836,8 +835,11 @@ msm_gpu_create_private_address_space(struct msm_gpu *gpu) * If the target doesn't support private address spaces then return * the global one */

• if (gpu->funcs->create_private_address_space)

• if (gpu->funcs->create_private_address_space) { aspace = gpu->funcs->create_private_address_space(gpu);

• if (!IS_ERR(aspace))
  

• 	aspace->pid = get_pid(task_pid(task));
  

• }

  if (IS_ERR_OR_NULL(aspace)) aspace = msm_gem_address_space_get(gpu->aspace);

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 4052a18e18c2..59f26bd0fe42 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -298,7 +298,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, const char *name, struct msm_gpu_config *config);

struct msm_gem_address_space * -msm_gpu_create_private_address_space(struct msm_gpu *gpu); +msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);

void msm_gpu_cleanup(struct msm_gpu *gpu);

-- 2.26.2