This patchset is based on Boris's "drm: Add support for bus-format negotiation" RFC at [1] patchset to implement : - basic bus-format negotiation for DW-HDMI - advanced HDMI2.0 YUV420 bus-format negotiation for DW-HDMI
And the counterpart implementation in the Amlogic Meson VPU dw-hdmi glue : - basic bus-format negotiation to select YUV444 bus-format as DW-HDMI input - YUV420 support when HDMI2.0 YUV420 modeset
This is a follow-up from the previous attempts : - "drm/meson: Add support for HDMI2.0 YUV420 4k60" at [2] - "drm/meson: Add support for HDMI2.0 4k60" at [3]
[1] https://patchwork.freedesktop.org/patch/msgid/20190808151150.16336-1-boris.b... [2] https://patchwork.freedesktop.org/patch/msgid/20190520133753.23871-1-narmstr... [3] https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-1-git-send-em...
Neil Armstrong (11): fixup! drm/bridge: Add the necessary bits to support bus format negotiation drm/meson: venc: make drm_display_mode const drm/meson: meson_dw_hdmi: switch to drm_bridge_funcs drm/bridge: synopsys: dw-hdmi: add basic bridge_atomic_check drm/bridge: synopsys: dw-hdmi: use negociated bus formats drm/meson: dw-hdmi: stop enforcing input_bus_format drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a drm/bridge: synopsys: dw-hdmi: add 420 mode format negociation drm/meson: venc: add support for YUV420 setup drm/meson: vclk: add support for YUV420 setup drm/meson: Add YUV420 output support
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 97 +++++++++++++++- drivers/gpu/drm/drm_bridge.c | 6 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 135 +++++++++++++++++----- drivers/gpu/drm/meson/meson_vclk.c | 93 +++++++++++---- drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc.c | 8 +- drivers/gpu/drm/meson/meson_venc.h | 13 ++- drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- include/drm/bridge/dw_hdmi.h | 1 + 9 files changed, 295 insertions(+), 68 deletions(-)
- } else if (b->num_supported_fmts > 1 && b->supported_fmts) {
*selected_bus_fmt = b->supported_fmts[0];return 0;
Here, `!a->num_supported_fmts &&` is missing otherwise this code will select b->supported_fmts[0] whatever the supported formats of a.
- } else if (a->num_supported_fmts > 1 && a->supported_fmts) {
*selected_bus_fmt = a->supported_fmts[0];return 0;
Here, `!b->num_supported_fmts &&` is missing otherwise this code will select a->supported_fmts[0] whatever the supported formats of b.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/drm_bridge.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 5f0925467292..82fe7728fcd1 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -615,10 +615,12 @@ int drm_find_best_bus_format(const struct drm_bus_caps *a, if (!a->num_supported_fmts && !b->num_supported_fmts) { *selected_bus_fmt = 0; return 0; - } else if (b->num_supported_fmts > 1 && b->supported_fmts) { + } else if (!a->num_supported_fmts && + b->num_supported_fmts > 1 && b->supported_fmts) { *selected_bus_fmt = b->supported_fmts[0]; return 0; - } else if (a->num_supported_fmts > 1 && a->supported_fmts) { + } else if (!b->num_supported_fmts && + a->num_supported_fmts > 1 && a->supported_fmts) { *selected_bus_fmt = a->supported_fmts[0]; return 0; } else if (!a->num_supported_fmts || !a->supported_fmts ||
Before switching to bridge funcs, make sure drm_display_mode is passed as const to the venc functions.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_venc.c | 2 +- drivers/gpu/drm/meson/meson_venc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 3d4791798ae0..c8e9840ad450 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -946,7 +946,7 @@ bool meson_venc_hdmi_venc_repeat(int vic) EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { union meson_hdmi_venc_mode *vmode = NULL; union meson_hdmi_venc_mode vmode_dmt; diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 576768bdd08d..1abdcbdf51c0 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -60,7 +60,7 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, - struct drm_display_mode *mode); + const struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv);
void meson_venc_enable_vsync(struct meson_drm *priv);
On Tue, 20 Aug 2019 10:41:00 +0200 Neil Armstrong narmstrong@baylibre.com wrote:
Before switching to bridge funcs, make sure drm_display_mode is passed as const to the venc functions.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com
Reviewed-by: Boris Brezillon boris.brezillon@collabora.com
drivers/gpu/drm/meson/meson_venc.c | 2 +- drivers/gpu/drm/meson/meson_venc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 3d4791798ae0..c8e9840ad450 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -946,7 +946,7 @@ bool meson_venc_hdmi_venc_repeat(int vic) EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
struct drm_display_mode *mode)
const struct drm_display_mode *mode){ union meson_hdmi_venc_mode *vmode = NULL; union meson_hdmi_venc_mode vmode_dmt; diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 576768bdd08d..1abdcbdf51c0 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -60,7 +60,7 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
struct drm_display_mode *mode);
const struct drm_display_mode *mode);unsigned int meson_venci_get_field(struct meson_drm *priv);
void meson_venc_enable_vsync(struct meson_drm *priv);
Switch the dw-hdmi driver to drm_bridge_funcs, and add the default supported YUV444 bus format to the encoder output_bus_caps.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 37 +++++++++++++++++---------- 1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 9f0b08eaf003..9a99d3920610 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -368,7 +368,7 @@ static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi) }
static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); @@ -670,15 +670,17 @@ static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = { .destroy = meson_venc_hdmi_encoder_destroy, };
-static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder, +static int meson_venc_hdmi_encoder_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { return 0; }
-static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder) +static void meson_venc_hdmi_encoder_disable(struct drm_bridge *bridge) { + struct drm_encoder *encoder = bridge_to_encoder(bridge); struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv;
@@ -691,8 +693,9 @@ static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder) writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); }
-static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder) +static void meson_venc_hdmi_encoder_enable(struct drm_bridge *bridge) { + struct drm_encoder *encoder = bridge_to_encoder(bridge); struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv;
@@ -704,10 +707,11 @@ static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder) writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); }
-static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) +static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) { + struct drm_encoder *encoder = bridge_to_encoder(bridge); struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); @@ -724,11 +728,10 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder, writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); }
-static const struct drm_encoder_helper_funcs - meson_venc_hdmi_encoder_helper_funcs = { - .atomic_check = meson_venc_hdmi_encoder_atomic_check, - .disable = meson_venc_hdmi_encoder_disable, +static const struct drm_bridge_funcs meson_venc_hdmi_encoder_bridge_funcs = { .enable = meson_venc_hdmi_encoder_enable, + .disable = meson_venc_hdmi_encoder_disable, + .atomic_check = meson_venc_hdmi_encoder_atomic_check, .mode_set = meson_venc_hdmi_encoder_mode_set, };
@@ -800,6 +803,10 @@ static bool meson_hdmi_connector_is_available(struct device *dev) return false; }
+static const u32 meson_dw_hdmi_out_bus_fmts[] = { + MEDIA_BUS_FMT_YUV8_1X24, +}; + static int meson_dw_hdmi_bind(struct device *dev, struct device *master, void *data) { @@ -810,6 +817,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, struct meson_drm *priv = drm->dev_private; struct dw_hdmi_plat_data *dw_plat_data; struct drm_encoder *encoder; + struct drm_bus_caps *bus_caps; struct resource *res; int irq; int ret; @@ -837,6 +845,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, meson_dw_hdmi->data = match; dw_plat_data = &meson_dw_hdmi->dw_plat_data; encoder = &meson_dw_hdmi->encoder; + bus_caps = &encoder->bridge.output_bus_caps;
meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { @@ -910,8 +919,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
/* Encoder */
- drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs); - + encoder->bridge.funcs = &meson_venc_hdmi_encoder_bridge_funcs; ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, DRM_MODE_ENCODER_TMDS, "meson_hdmi"); if (ret) { @@ -919,6 +927,9 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, return ret; }
+ bus_caps->supported_fmts = meson_dw_hdmi_out_bus_fmts; + bus_caps->num_supported_fmts = ARRAY_SIZE(meson_dw_hdmi_out_bus_fmts); + encoder->possible_crtcs = BIT(0);
DRM_DEBUG_DRIVER("encoder initialized\n");
Add all the supported input and output formats to the bridge input_bus_caps and output_bus_caps, and add a very simple atomic check implementation to negociate output and input bus formats.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 53 +++++++++++++++++++++++ 1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index b4901b174a90..121c2167ee20 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -91,6 +91,24 @@ static const u16 csc_coeff_rgb_in_eitu709[3][4] = { { 0x6756, 0x78ab, 0x2000, 0x0200 } };
+static const u32 dw_hdmi_bus_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_RGB101010_1X30, + MEDIA_BUS_FMT_RGB121212_1X36, + MEDIA_BUS_FMT_RGB161616_1X48, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUV10_1X30, + MEDIA_BUS_FMT_YUV12_1X36, + MEDIA_BUS_FMT_YUV16_1X48, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_UYVY10_1X20, + MEDIA_BUS_FMT_UYVY12_1X24, + MEDIA_BUS_FMT_UYYVYY8_0_5X24, + MEDIA_BUS_FMT_UYYVYY10_0_5X30, + MEDIA_BUS_FMT_UYYVYY12_0_5X36, + MEDIA_BUS_FMT_UYYVYY16_0_5X48, +}; + struct hdmi_vmode { bool mdataenablepolarity;
@@ -2190,6 +2208,33 @@ static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = .get_modes = dw_hdmi_connector_get_modes, };
+static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct dw_hdmi *hdmi = bridge->driver_private; + int ret; + + ret = drm_atomic_bridge_choose_output_bus_cfg(bridge_state, crtc_state, + conn_state); + if (ret) + return ret; + + dev_dbg(hdmi->dev, "selected output format %x\n", + bridge_state->output_bus_cfg.fmt); + + ret = drm_atomic_bridge_choose_input_bus_cfg(bridge_state, crtc_state, + conn_state); + if (ret) + return ret; + + dev_dbg(hdmi->dev, "selected input format %x\n", + bridge_state->input_bus_cfg.fmt); + + return 0; +} + static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) { struct dw_hdmi *hdmi = bridge->driver_private; @@ -2267,6 +2312,7 @@ static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { .attach = dw_hdmi_bridge_attach, + .atomic_check = dw_hdmi_bridge_atomic_check, .enable = dw_hdmi_bridge_enable, .disable = dw_hdmi_bridge_disable, .mode_set = dw_hdmi_bridge_mode_set, @@ -2733,6 +2779,13 @@ __dw_hdmi_probe(struct platform_device *pdev,
hdmi->bridge.driver_private = hdmi; hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; + hdmi->bridge.input_bus_caps.supported_fmts = dw_hdmi_bus_fmts; + hdmi->bridge.input_bus_caps.num_supported_fmts = + ARRAY_SIZE(dw_hdmi_bus_fmts); + hdmi->bridge.output_bus_caps.supported_fmts = dw_hdmi_bus_fmts; + hdmi->bridge.output_bus_caps.num_supported_fmts = + ARRAY_SIZE(dw_hdmi_bus_fmts); + #ifdef CONFIG_OF hdmi->bridge.of_node = pdev->dev.of_node; #endif
Use the negociated bus formats from the atomic check function if the input and output formats are non NULL, otherwise fallback to the plat_data->input_bus_format or the default MEDIA_BUS_FMT_RGB888_1X24 bus format.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 121c2167ee20..316823abdd00 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1968,11 +1968,10 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
- /* TOFIX: Get input format from plat data or fallback to RGB888 */ if (hdmi->plat_data->input_bus_format) hdmi->hdmi_data.enc_in_bus_format = hdmi->plat_data->input_bus_format; - else + else if (!hdmi->hdmi_data.enc_in_bus_format) hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
/* TOFIX: Get input encoding from plat data or fallback to none */ @@ -1982,8 +1981,8 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) else hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
- /* TOFIX: Default to RGB888 output format */ - hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + if (!hdmi->hdmi_data.enc_out_bus_format) + hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
hdmi->hdmi_data.pix_repet_factor = 0; hdmi->hdmi_data.hdcp_enable = 0; @@ -2224,6 +2223,8 @@ static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, dev_dbg(hdmi->dev, "selected output format %x\n", bridge_state->output_bus_cfg.fmt);
+ hdmi->hdmi_data.enc_out_bus_format = bridge_state->output_bus_cfg.fmt; + ret = drm_atomic_bridge_choose_input_bus_cfg(bridge_state, crtc_state, conn_state); if (ret) @@ -2232,6 +2233,8 @@ static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, dev_dbg(hdmi->dev, "selected input format %x\n", bridge_state->input_bus_cfg.fmt);
+ hdmi->hdmi_data.enc_in_bus_format = bridge_state->input_bus_cfg.fmt; + return 0; }
To allow using formats from negociation, stop enforcing input_bus_format in the private dw-plat-data struct.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 9a99d3920610..fb09592eba3e 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -975,7 +975,6 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; dw_plat_data->phy_name = "meson_dw_hdmi_phy"; dw_plat_data->phy_data = meson_dw_hdmi; - dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
platform_set_drvdata(pdev, meson_dw_hdmi);
Now the DW-HDMI Controller supports the HDMI2.0 modes, enable support for these modes in the connector if the platform supports them. We limit these modes to DW-HDMI IP version >= 0x200a which are designed to support HDMI2.0 display modes.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++ include/drm/bridge/dw_hdmi.h | 1 + 2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 316823abdd00..cb560b231d74 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2793,6 +2793,12 @@ __dw_hdmi_probe(struct platform_device *pdev, hdmi->bridge.of_node = pdev->dev.of_node; #endif
+ if (hdmi->version >= 0x200a) + hdmi->connector.ycbcr_420_allowed = + hdmi->plat_data->ycbcr_420_allowed; + else + hdmi->connector.ycbcr_420_allowed = false; + memset(&pdevinfo, 0, sizeof(pdevinfo)); pdevinfo.parent = dev; pdevinfo.id = PLATFORM_DEVID_AUTO; diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index c402364aec0d..04e63ed29417 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -126,6 +126,7 @@ struct dw_hdmi_plat_data { const struct drm_display_mode *mode); unsigned long input_bus_format; unsigned long input_bus_encoding; + bool ycbcr_420_allowed;
/* Vendor PHY support */ const struct dw_hdmi_phy_ops *phy_ops;
Add special negociation case for 420 HDMI2.0 format.
In this case the DW-HDMI CSC cannot handle 420 data, and must be in passthrought, thus input_bus_cfg must be output_bus_cfg.
Add support for handling a specific 8/10/12/16 variant in the connector bus_formats if specified.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 ++++++++++++++++++----- 1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index cb560b231d74..b96119c6fad2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2213,23 +2213,50 @@ static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, struct drm_connector_state *conn_state) { struct dw_hdmi *hdmi = bridge->driver_private; + struct drm_connector *conn = conn_state->connector; + struct drm_display_info *info = &conn->display_info; + struct drm_display_mode *mode = &crtc_state->mode; + bool is_hdmi2_sink = info->hdmi.scdc.supported; int ret;
- ret = drm_atomic_bridge_choose_output_bus_cfg(bridge_state, crtc_state, - conn_state); - if (ret) - return ret; + /* + * If the current mode enforces 4:2:0, force the output but format + * or use the connector bus formats if a non 8bit 4:2:0 format + * is provided. + */ + if (drm_mode_is_420_only(info, mode) || + (!is_hdmi2_sink && drm_mode_is_420_also(info, mode))) { + if (info->num_bus_formats && info->bus_formats && + hdmi_bus_fmt_is_yuv420(info->bus_formats[0])) + bridge_state->output_bus_cfg.fmt = info->bus_formats[0]; + else + bridge_state->output_bus_cfg.fmt = + MEDIA_BUS_FMT_UYYVYY8_0_5X24; + } else { + ret = drm_atomic_bridge_choose_output_bus_cfg(bridge_state, + crtc_state, + conn_state); + if (ret) + return ret; + } + + if (hdmi_bus_fmt_is_yuv420(bridge_state->output_bus_cfg.fmt)) { + /* The DW-HDMI CSC cannot interpolate and decimate in 4:2:0 */ + bridge_state->input_bus_cfg.fmt = + bridge_state->output_bus_cfg.fmt; + } else { + ret = drm_atomic_bridge_choose_input_bus_cfg(bridge_state, + crtc_state, + conn_state); + if (ret) + return ret; + }
dev_dbg(hdmi->dev, "selected output format %x\n", bridge_state->output_bus_cfg.fmt);
hdmi->hdmi_data.enc_out_bus_format = bridge_state->output_bus_cfg.fmt;
- ret = drm_atomic_bridge_choose_input_bus_cfg(bridge_state, crtc_state, - conn_state); - if (ret) - return ret; - dev_dbg(hdmi->dev, "selected input format %x\n", bridge_state->input_bus_cfg.fmt);
This patch adds encoding support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream.
In addition if pixel stream down-sampling, the Y Cb Cr components must also be mapped differently to align with the HDMI2.0 specifications.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 3 ++- drivers/gpu/drm/meson/meson_venc.c | 6 ++++-- drivers/gpu/drm/meson/meson_venc.h | 11 +++++++++++ 3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index fb09592eba3e..2b278ee75100 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -719,7 +719,8 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge, DRM_DEBUG_DRIVER(""%s" vic %d\n", mode->name, vic);
/* VENC + VENC-DVI Mode setup */ - meson_venc_hdmi_mode_set(priv, vic, mode); + meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, false, + MESON_VENC_MAP_CB_Y_CR);
/* VCLK Set clock */ dw_hdmi_set_vclk(dw_hdmi, mode); diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index c8e9840ad450..ec2723822552 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -946,6 +946,8 @@ bool meson_venc_hdmi_venc_repeat(int vic) EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, const struct drm_display_mode *mode) { union meson_hdmi_venc_mode *vmode = NULL; @@ -1496,8 +1498,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, writel_relaxed((use_enci ? 1 : 2) | (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | - 4 << 5 | - (venc_repeat ? 1 << 8 : 0) | + (ycrcb_map << 5) | + (venc_repeat || yuv420_mode ? 1 << 8 : 0) | (hdmi_repeat ? 1 << 12 : 0), priv->io_base + _REG(VPU_HDMI_SETTING));
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 1abdcbdf51c0..88ded5451c49 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -23,6 +23,15 @@ enum { MESON_VENC_MODE_HDMI, };
+enum { + MESON_VENC_MAP_CR_Y_CB = 0, + MESON_VENC_MAP_Y_CB_CR, + MESON_VENC_MAP_Y_CR_CB, + MESON_VENC_MAP_CB_CR_Y, + MESON_VENC_MAP_CB_Y_CR, + MESON_VENC_MAP_CR_CB_Y, +}; + struct meson_cvbs_enci_mode { unsigned int mode_tag; unsigned int hso_begin; /* HSO begin position */ @@ -60,6 +69,8 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode); void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, + unsigned int ycrcb_map, + bool yuv420_mode, const struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv);
This patch adds clocking support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream.
This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ratio with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock.
This patch adds the TMDS PHY clock value in all the video clock setup in order to better support these specific uses cases and switch to the Common Clock framework for clocks handling in the future.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 24 ++++--- drivers/gpu/drm/meson/meson_vclk.c | 93 +++++++++++++++++++------ drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- 4 files changed, 93 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 2b278ee75100..3ce7a63fa994 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -372,15 +372,19 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, { struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq;
vclk_freq = mode->clock;
+ /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + if (!vic) { - meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq, - vclk_freq, vclk_freq, false); + meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq, + vclk_freq, vclk_freq, vclk_freq, false); return; }
@@ -398,11 +402,11 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2;
- DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n", - vclk_freq, venc_freq, hdmi_freq, + DRM_DEBUG_DRIVER("vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n", + phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci);
- meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq, + meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); }
@@ -611,6 +615,7 @@ dw_hdmi_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) { struct meson_drm *priv = connector->dev->dev_private; + unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; unsigned int hdmi_freq; @@ -637,6 +642,9 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
vclk_freq = mode->clock;
+ /* TMDS clock is pixel_clock * 10 */ + phy_freq = vclk_freq * 10; + /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2; @@ -653,10 +661,10 @@ dw_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /= 2;
- dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__, - vclk_freq, venc_freq, hdmi_freq); + dev_dbg(connector->dev->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n", + __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq);
- return meson_vclk_vic_supported_freq(vclk_freq); + return meson_vclk_vic_supported_freq(phy_freq, vclk_freq); }
/* Encoder */ diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index 8abff51f937d..aedbf2ded97c 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -353,12 +353,17 @@ enum { /* 2970 /1 /1 /1 /5 /2 => /1 /1 */ MESON_VCLK_HDMI_297000, /* 5940 /1 /1 /2 /5 /1 => /1 /1 */ - MESON_VCLK_HDMI_594000 + MESON_VCLK_HDMI_594000, +/* 2970 /1 /1 /1 /5 /1 => /1 /2 */ + MESON_VCLK_HDMI_594000_YUV420, };
struct meson_vclk_params { + unsigned int pll_freq; + unsigned int phy_freq; + unsigned int vclk_freq; + unsigned int venc_freq; unsigned int pixel_freq; - unsigned int pll_base_freq; unsigned int pll_od1; unsigned int pll_od2; unsigned int pll_od3; @@ -366,8 +371,11 @@ struct meson_vclk_params { unsigned int vclk_div; } params[] = { [MESON_VCLK_HDMI_ENCI_54000] = { + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, .pixel_freq = 54000, - .pll_base_freq = 4320000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -375,8 +383,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_54000] = { - .pixel_freq = 54000, - .pll_base_freq = 4320000, + .pll_freq = 4320000, + .phy_freq = 270000, + .vclk_freq = 54000, + .venc_freq = 54000, + .pixel_freq = 27000, .pll_od1 = 4, .pll_od2 = 4, .pll_od3 = 1, @@ -384,8 +395,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_DDR_148500] = { - .pixel_freq = 148500, - .pll_base_freq = 2970000, + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 148500, + .venc_freq = 148500, + .pixel_freq = 74250, .pll_od1 = 4, .pll_od2 = 1, .pll_od3 = 1, @@ -393,8 +407,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_74250] = { + .pll_freq = 2970000, + .phy_freq = 742500, + .vclk_freq = 74250, + .venc_freq = 74250, .pixel_freq = 74250, - .pll_base_freq = 2970000, .pll_od1 = 2, .pll_od2 = 2, .pll_od3 = 2, @@ -402,8 +419,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_148500] = { + .pll_freq = 2970000, + .phy_freq = 1485000, + .vclk_freq = 148500, + .venc_freq = 148500, .pixel_freq = 148500, - .pll_base_freq = 2970000, .pll_od1 = 1, .pll_od2 = 2, .pll_od3 = 2, @@ -411,8 +431,11 @@ struct meson_vclk_params { .vclk_div = 1, }, [MESON_VCLK_HDMI_297000] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 297000, + .vclk_freq = 297000, .pixel_freq = 297000, - .pll_base_freq = 5940000, .pll_od1 = 2, .pll_od2 = 1, .pll_od3 = 1, @@ -420,14 +443,29 @@ struct meson_vclk_params { .vclk_div = 2, }, [MESON_VCLK_HDMI_594000] = { + .pll_freq = 5940000, + .phy_freq = 5940000, + .venc_freq = 594000, + .vclk_freq = 594000, .pixel_freq = 594000, - .pll_base_freq = 5940000, .pll_od1 = 1, .pll_od2 = 1, .pll_od3 = 2, .vid_pll_div = VID_PLL_DIV_5, .vclk_div = 1, }, + [MESON_VCLK_HDMI_594000_YUV420] = { + .pll_freq = 5940000, + .phy_freq = 2970000, + .venc_freq = 594000, + .vclk_freq = 594000, + .pixel_freq = 297000, + .pll_od1 = 2, + .pll_od2 = 1, + .pll_od3 = 1, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 1, + }, { /* sentinel */ }, };
@@ -694,6 +732,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, unsigned int od, m, frac, od1, od2, od3;
if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) { + /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */ od3 = 1; if (od < 4) { od1 = 2; @@ -716,21 +755,28 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, }
enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq) +meson_vclk_vic_supported_freq(unsigned int phy_freq, + unsigned int vclk_freq) { int i;
- DRM_DEBUG_DRIVER("freq = %d\n", freq); + DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n", + phy_freq, vclk_freq);
for (i = 0 ; params[i].pixel_freq ; ++i) { DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", i, params[i].pixel_freq, FREQ_1000_1001(params[i].pixel_freq)); + DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n", + i, params[i].phy_freq, + FREQ_1000_1001(params[i].phy_freq/10)*10); /* Match strict frequency */ - if (freq == params[i].pixel_freq) + if (phy_freq == params[i].phy_freq && + vclk_freq == params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (freq == FREQ_1000_1001(params[i].pixel_freq)) + if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) && + vclk_freq == FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; }
@@ -958,8 +1004,9 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, }
void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci) + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci) { bool vic_alternate_clock = false; unsigned int freq; @@ -978,7 +1025,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, * - venc_div = 1 * - encp encoder */ - meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0, + meson_vclk_set(priv, phy_freq, 0, 0, 0, VID_PLL_DIV_5, 2, 1, 1, false, false); return; } @@ -1000,9 +1047,11 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, }
for (freq = 0 ; params[freq].pixel_freq ; ++freq) { - if (vclk_freq == params[freq].pixel_freq || - vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) { - if (vclk_freq != params[freq].pixel_freq) + if ((phy_freq == params[freq].phy_freq || + phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) && + (vclk_freq == params[freq].vclk_freq || + vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) { + if (vclk_freq != params[freq].vclk_freq) vic_alternate_clock = true; else vic_alternate_clock = false; @@ -1031,7 +1080,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, return; }
- meson_vclk_set(priv, params[freq].pll_base_freq, + meson_vclk_set(priv, params[freq].pll_freq, params[freq].pll_od1, params[freq].pll_od2, params[freq].pll_od3, params[freq].vid_pll_div, params[freq].vclk_div, hdmi_tx_div, venc_div, diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h index b62125540aef..aed0ab2efa71 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -25,10 +25,11 @@ enum { enum drm_mode_status meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); enum drm_mode_status -meson_vclk_vic_supported_freq(unsigned int freq); +meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq);
void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int vclk_freq, unsigned int venc_freq, - unsigned int dac_freq, bool hdmi_use_enci); + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, + bool hdmi_use_enci);
#endif /* __MESON_VCLK_H */ diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c index 45a467f10b9b..7fe574adb8dd 100644 --- a/drivers/gpu/drm/meson/meson_venc_cvbs.c +++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c @@ -205,7 +205,8 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, /* Setup 27MHz vclk2 for ENCI and VDAC */ meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS, MESON_VCLK_CVBS, - MESON_VCLK_CVBS, true); + MESON_VCLK_CVBS, MESON_VCLK_CVBS, + true); break; } }
This patch adds support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.
The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. In addition if pixel stream down-sampling, the Y Cb Cr components must also be mapped differently to align with the HDMI2.0 specifications.
This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ration with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock.
This patch enables the bridge bus format negociation, and handles the YUV420 case if selected by the negociation.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 74 +++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 3ce7a63fa994..f7a9c1205937 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -148,6 +148,7 @@ struct meson_dw_hdmi { struct regulator *hdmi_supply; u32 irq_stat; struct dw_hdmi *hdmi; + unsigned long output_bus_fmt; }; #define encoder_to_meson_dw_hdmi(x) \ container_of(x, struct meson_dw_hdmi, encoder) @@ -297,6 +298,10 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, struct meson_drm *priv = dw_hdmi->priv; unsigned int pixel_clock = mode->clock;
+ /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + pixel_clock /= 2; + if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { if (pixel_clock >= 371250) { @@ -379,6 +384,10 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi,
vclk_freq = mode->clock;
+ /* For 420, pixel clock is half unlike venc clock */ + if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + vclk_freq /= 2; + /* TMDS clock is pixel_clock * 10 */ phy_freq = vclk_freq * 10;
@@ -388,13 +397,16 @@ static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi, return; }
+ /* 480i/576i needs global pixel doubling */ if (mode->flags & DRM_MODE_FLAG_DBLCLK) vclk_freq *= 2;
venc_freq = vclk_freq; hdmi_freq = vclk_freq;
- if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) venc_freq *= 2;
vclk_freq = max(venc_freq, hdmi_freq); @@ -439,8 +451,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, /* Enable normal output to PHY */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
- /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ - if (mode->clock > 340000) { + /* TMDS pattern setup */ + if (mode->clock > 340000 && + dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_YUV8_1X24) { dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, @@ -615,6 +628,7 @@ dw_hdmi_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) { struct meson_drm *priv = connector->dev->dev_private; + bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; unsigned int phy_freq; unsigned int vclk_freq; unsigned int venc_freq; @@ -624,9 +638,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
- /* If sink max TMDS clock, we reject the mode */ + /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ if (connector->display_info.max_tmds_clock && - mode->clock > connector->display_info.max_tmds_clock) + mode->clock > connector->display_info.max_tmds_clock && + !drm_mode_is_420_only(&connector->display_info, mode) && + !drm_mode_is_420_also(&connector->display_info, mode)) return MODE_BAD;
/* Check against non-VIC supported modes */ @@ -642,6 +658,12 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
vclk_freq = mode->clock;
+ /* For 420, pixel clock is half unlike venc clock */ + if (drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) + vclk_freq /= 2; + /* TMDS clock is pixel_clock * 10 */ phy_freq = vclk_freq * 10;
@@ -652,8 +674,11 @@ dw_hdmi_mode_valid(struct drm_connector *connector, venc_freq = vclk_freq; hdmi_freq = vclk_freq;
- /* VENC double pixels for 1080i and 720p modes */ - if (meson_venc_hdmi_venc_repeat(vic)) + /* VENC double pixels for 1080i, 720p and YUV420 modes */ + if (meson_venc_hdmi_venc_repeat(vic) || + drm_mode_is_420_only(&connector->display_info, mode) || + (!is_hdmi2_sink && + drm_mode_is_420_also(&connector->display_info, mode))) venc_freq *= 2;
vclk_freq = max(venc_freq, hdmi_freq); @@ -683,6 +708,20 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct drm_encoder *encoder = bridge_to_encoder(bridge); + struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); + int ret; + + ret = drm_atomic_bridge_choose_output_bus_cfg(bridge_state, + crtc_state, + conn_state); + if (ret) + return ret; + + dw_hdmi->output_bus_fmt = bridge_state->output_bus_cfg.fmt; + + DRM_DEBUG_DRIVER("output_bus_fmt %lx\n", dw_hdmi->output_bus_fmt); + return 0; }
@@ -723,18 +762,29 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge, struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv; int vic = drm_match_cea_mode(mode); + unsigned int ycrcb_map = MESON_VENC_MAP_CB_Y_CR; + bool yuv420_mode = false;
DRM_DEBUG_DRIVER(""%s" vic %d\n", mode->name, vic);
+ if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { + ycrcb_map = MESON_VENC_MAP_CR_Y_CB; + yuv420_mode = true; + } + /* VENC + VENC-DVI Mode setup */ - meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, false, - MESON_VENC_MAP_CB_Y_CR); + meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
/* VCLK Set clock */ dw_hdmi_set_vclk(dw_hdmi, mode);
- /* Setup YUV444 to HDMI-TX, no 10bit diphering */ - writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) + /* Setup YUV420 to HDMI-TX, no 10bit diphering */ + writel_relaxed(2 | (2 << 2), + priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); + else + /* Setup YUV444 to HDMI-TX, no 10bit diphering */ + writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); }
static const struct drm_bridge_funcs meson_venc_hdmi_encoder_bridge_funcs = { @@ -814,6 +864,7 @@ static bool meson_hdmi_connector_is_available(struct device *dev)
static const u32 meson_dw_hdmi_out_bus_fmts[] = { MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_UYYVYY8_0_5X24, };
static int meson_dw_hdmi_bind(struct device *dev, struct device *master, @@ -985,6 +1036,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, dw_plat_data->phy_name = "meson_dw_hdmi_phy"; dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; + dw_plat_data->ycbcr_420_allowed = true;
platform_set_drvdata(pdev, meson_dw_hdmi);
On Tue, 20 Aug 2019 10:40:58 +0200 Neil Armstrong narmstrong@baylibre.com wrote:
This patchset is based on Boris's "drm: Add support for bus-format negotiation" RFC at [1]
Small clarification. Neil's work in based on a slightly different version of my RFC [4] (I plan to post a v2 very soon).
patchset to implement :
- basic bus-format negotiation for DW-HDMI
- advanced HDMI2.0 YUV420 bus-format negotiation for DW-HDMI
And the counterpart implementation in the Amlogic Meson VPU dw-hdmi glue :
- basic bus-format negotiation to select YUV444 bus-format as DW-HDMI input
- YUV420 support when HDMI2.0 YUV420 modeset
This is a follow-up from the previous attempts :
- "drm/meson: Add support for HDMI2.0 YUV420 4k60" at [2]
- "drm/meson: Add support for HDMI2.0 4k60" at [3]
[1] https://patchwork.freedesktop.org/patch/msgid/20190808151150.16336-1-boris.b... [2] https://patchwork.freedesktop.org/patch/msgid/20190520133753.23871-1-narmstr... [3] https://patchwork.freedesktop.org/patch/msgid/1549022873-40549-1-git-send-em...
[4]https://github.com/bbrezillon/linux-0day/commits/drm-bridge-busfmt-2
Neil Armstrong (11): fixup! drm/bridge: Add the necessary bits to support bus format negotiation drm/meson: venc: make drm_display_mode const drm/meson: meson_dw_hdmi: switch to drm_bridge_funcs drm/bridge: synopsys: dw-hdmi: add basic bridge_atomic_check drm/bridge: synopsys: dw-hdmi: use negociated bus formats drm/meson: dw-hdmi: stop enforcing input_bus_format drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a drm/bridge: synopsys: dw-hdmi: add 420 mode format negociation drm/meson: venc: add support for YUV420 setup drm/meson: vclk: add support for YUV420 setup drm/meson: Add YUV420 output support
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 97 +++++++++++++++- drivers/gpu/drm/drm_bridge.c | 6 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 135 +++++++++++++++++----- drivers/gpu/drm/meson/meson_vclk.c | 93 +++++++++++---- drivers/gpu/drm/meson/meson_vclk.h | 7 +- drivers/gpu/drm/meson/meson_venc.c | 8 +- drivers/gpu/drm/meson/meson_venc.h | 13 ++- drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- include/drm/bridge/dw_hdmi.h | 1 + 9 files changed, 295 insertions(+), 68 deletions(-)
dri-devel@lists.freedesktop.org
-
Boris Brezillon -
Neil Armstrong