On Wed, Jul 02, 2014 at 06:29:23PM +0200, Paolo Bonzini wrote:

Il 02/07/2014 17:27, Michael S. Tsirkin ha scritto:

...

At some level, maybe Paolo is right. Ignore existing drivers and ask intel developers to update their drivers to do something sane on hypervisors, even if they do ugly things on real hardware.

A simple proposal since what I wrote earlier though apparently wasn't very clear:

Detect Xen subsystem vendor id on vga card. If there, avoid poking at chipset. Instead

• use subsystem device # for card type

You mean for PCH type (aka PCH device id).

...

• use second half of BAR0 of device
• instead of access to pci host

hypervisors will simply take BAR0 and double it in size, make second part map to what would be the pci host.

Nice. Detecting the backdoor via the subsystem vendor id is clever.

I'm not sure if it's possible to just double the size of BAR0 or not, but my laptop has:

Region 0: Memory at d0000000 (64-bit, non-prefetchable) [size=4M] Region 2: Memory at c0000000 (64-bit, prefetchable) [size=256M] Region 4: I/O ports at 5000 [size=64]

and I hope we can reserve a few KB for hypervisors within those 4M, or 8 bytes for an address/data pair (like cf8/cfc) within BAR4's 64 bytes (or grow BAR4 to 128 bytes, or something like that).

Xen can still add the hacky machine type if they want for existing hosts, but this would be a nice way forward.

It would be good to understand first why i915 in the first place needs to setup the bridge MBAR if it has not been set. As in, why is this region needed? Is it needed to flush the pipeline (as in you need to write there?) or ..

Perhaps it is not needed anymore with the current hardware and what can be done is put a stake in the ground saying that only genX or later will be supported.

The commit ids allude to power managament and the earlier commits did poke there - but I don't see it on the latest tree.

Paolo

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