Display Stream Compression (DSC) compresses the display stream in host which is later decoded by panel. This series enables this for Qualcomm msm driver. This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then support in encoder. We also add support in DSI and introduce required topology changes.
In order for panel to set the DSC parameters we add dsc in drm_panel and set it from the msm driver.
We still have dsc as a globabl entity. I think while doing DP + DSC we should be able to update it, right now comprehending the requirements are bit difficult.
Complete changes which enable this for Pixel3 along with panel driver (not part of this series) and DT changes can be found at: git.linaro.org/people/vinod.koul/kernel.git pixel/dsc_v3
Comments welcome!
Changes since v2: - Fix comments by Dimitry except the dsc being global. - Move RM patch later for dependency on topology now - Add patch for mode valid callback for dsi_mgr - Add missing structure documentation patch - Fix errors in mode_3d changes - Rebase on v5.16-rc1 and test
Changes since v1: - Fix various issues spotted by kbuildbot - Rebase to v5.15-rc3 - Remove unused fields and duplicate defines - Enable DSC blocks only when DSC is enabled - remove sdm845 feature mask, use 0 - Check for DSC in hw_ctl
Changes since RFC: - Drop the DT binding patch as we derive the configuration from panel - Drop the drm api patch as we no longer need it (use pps drm api) - Fix comments raised by Dimitry - Add dsc parameters calculation from downstream
Vinod Koul (13): drm/msm/dsi: add support for dsc data drm/msm/disp/dpu1: Add support for DSC drm/msm/disp/dpu1: Add support for DSC in pingpong block drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog drm/msm/disp/dpu1: Don't use DSC with mode_3d drm/msm/disp/dpu1: Add DSC support in hw_ctl drm/msm/disp/dpu1: Add support for DSC in encoder drm/msm: Add missing structure documentation drm/msm/disp/dpu1: Add support for DSC in topology drm/msm/disp/dpu1: Add DSC support in RM drm/msm/dsi: add mode valid callback for dsi_mgr drm/msm/dsi: Add support for DSC configuration drm/msm/dsi: Pass DSC params to drm_panel
drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 158 +++++++++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 + .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 +++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 + .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 + drivers/gpu/drm/msm/dsi/dsi_host.c | 285 +++++++++++++++++- drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 + drivers/gpu/drm/msm/msm_drv.h | 23 ++ include/drm/drm_panel.h | 7 + 22 files changed, 970 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
Display Stream Compression (DSC) parameters need to be calculated. Add helpers and struct msm_display_dsc_config in msm_drv for this msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 20 +++++ 2 files changed, 152 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index f69a125f9559..30c1e299aa52 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -31,6 +31,8 @@
#define DSI_RESET_TOGGLE_DELAY_MS 20
+static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc); + static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) { u32 ver; @@ -157,6 +159,7 @@ struct msm_dsi_host { struct regmap *sfpb;
struct drm_display_mode *mode; + struct msm_display_dsc_config *dsc;
/* connected device info */ struct device_node *device_node; @@ -1710,6 +1713,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; }
+static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e +}; + +/* only 8bpc, 8bpp added */ +static char min_qp[DSC_NUM_BUF_RANGES] = { + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 +}; + +static char max_qp[DSC_NUM_BUF_RANGES] = { + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 +}; + +static char bpg_offset[DSC_NUM_BUF_RANGES] = { + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 +}; + +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc) +{ + int mux_words_size; + int groups_per_line, groups_total; + int min_rate_buffer_size; + int hrd_delay; + int pre_num_extra_mux_bits, num_extra_mux_bits; + int slice_bits; + int target_bpp_x16; + int data; + int final_value, final_scale; + int i; + + dsc->drm->rc_model_size = 8192; + dsc->drm->first_line_bpg_offset = 12; + dsc->drm->rc_edge_factor = 6; + dsc->drm->rc_tgt_offset_high = 3; + dsc->drm->rc_tgt_offset_low = 3; + dsc->drm->simple_422 = 0; + dsc->drm->convert_rgb = 1; + dsc->drm->vbr_enable = 0; + + /* handle only bpp = bpc = 8 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i]; + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i]; + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i]; + } + + dsc->drm->initial_offset = 6144; /* Not bpp 12 */ + if (dsc->drm->bits_per_pixel != 8) + dsc->drm->initial_offset = 2048; /* bpp = 12 */ + + mux_words_size = 48; /* bpc == 8/10 */ + if (dsc->drm->bits_per_component == 12) + mux_words_size = 64; + + dsc->drm->initial_xmit_delay = 512; + dsc->drm->initial_scale_value = 32; + dsc->drm->first_line_bpg_offset = 12; + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1; + + /* bpc 8 */ + dsc->drm->flatness_min_qp = 3; + dsc->drm->flatness_max_qp = 12; + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8); + dsc->drm->rc_quant_incr_limit0 = 11; + dsc->drm->rc_quant_incr_limit1 = 11; + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of + * params are calculated + */ + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3); + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3); + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8; + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8) + dsc->drm->slice_chunk_size++; + + /* rbs-min */ + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset + + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel + + groups_per_line * dsc->drm->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel); + + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay; + + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size / + (dsc->drm->rc_model_size - dsc->drm->initial_offset); + + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height; + + groups_total = groups_per_line * dsc->drm->slice_height; + + data = dsc->drm->first_line_bpg_offset * 2048; + + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1)); + + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2); + + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size - + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size)); + + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits); + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total); + + /* bpp * 16 + 0.5 */ + data = dsc->drm->bits_per_pixel * 16; + data *= 2; + data++; + data /= 2; + target_bpp_x16 = data; + + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16; + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits; + dsc->drm->final_offset = final_value; + + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value); + + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset); + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data; + + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8); + + return 0; +} + static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { struct device *dev = &msm_host->pdev->dev; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 69952b239384..de7cb65bfc52 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -30,6 +30,7 @@ #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_fb_helper.h> +#include <drm/drm_dsc.h> #include <drm/msm_drm.h> #include <drm/drm_gem.h>
@@ -134,6 +135,22 @@ struct msm_drm_thread { struct kthread_worker *worker; };
+/* DSC config */ +struct msm_display_dsc_config { + struct drm_dsc_config *drm; + + u32 initial_lines; + u32 pkt_per_line; + u32 bytes_in_slice; + u32 bytes_per_pkt; + u32 eol_byte_num; + u32 pclk_per_line; + u32 slice_last_group_size; + u32 det_thresh_flatness; + + unsigned int dsc_mask; +}; + struct msm_drm_private {
struct drm_device *dev; @@ -228,6 +245,9 @@ struct msm_drm_private { /* Properties */ struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
+ /* DSC configuration */ + struct msm_display_dsc_config *dsc; + /* VRAM carveout, used when no IOMMU: */ struct { unsigned long size;
On 16/11/2021 09:22, Vinod Koul wrote:
Here you have a bitmask, but it is never used in this way (you never read actual values from it). So I'd suggest to drop it.
Let's make it `stuct msm_display_dsc_config * dsc[2]` at least. This way DSI0 and DSI1 will know if DSC should be used for the respective host. Otherwise DSC can get enabled for DP encoder if there an attached DSC DSI panel.
Hi Vinod
On 11/15/2021 10:22 PM, Vinod Koul wrote:
since its been a while on this, before moving ahead with a FIXME comment, I wanted to know if you had a chance to check what is the discrepancy between this and drm_dsc_compute_rc_parameters().
The LOC saved can be quite a bit if we move to drm_dsc_compute_rc_parameters(). Last time we synced, I think only one parameter was mismatching. The code-churn to avoid one mismatch seems a lot. If there are more conflicting parameters than one or two, we can go ahead with this custom calculation with your FIXME.
I agree with Dmitry, that we need a closer binding of dsc_config with which display its getting associated with. Having it in the private object is too generic.
https://patchwork.freedesktop.org/patch/463255/?series=90413&rev=4
How about moving this to struct dpu_encoder_virt. That way, it will be associated with the correct encoder.
Yes, I dont see the usage for dsc_mask too.
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add support by adding hw blocks for DSC
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/Makefile | 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++ 5 files changed, 314 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 40577f8856d8..7d7058f1f5c1 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -59,6 +59,7 @@ msm-y := \ disp/dpu1/dpu_formats.o \ disp/dpu1/dpu_hw_catalog.o \ disp/dpu1/dpu_hw_ctl.o \ + disp/dpu1/dpu_hw_dsc.o \ disp/dpu1/dpu_hw_interrupts.o \ disp/dpu1/dpu_hw_intf.o \ disp/dpu1/dpu_hw_lm.o \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4ade44bbd37e..65f43fadcda0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -553,6 +553,16 @@ struct dpu_merge_3d_cfg { const struct dpu_merge_3d_sub_blks *sblk; };
+/** + * struct dpu_dsc_cfg - information of DSC blocks + * @id enum identifying this block + * @base register offset of this block + * @features bit mask identifying sub-blocks/features + */ +struct dpu_dsc_cfg { + DPU_HW_BLK_INFO; +}; + /** * struct dpu_intf_cfg - information of timing engine blocks * @id enum identifying this block @@ -749,6 +759,9 @@ struct dpu_mdss_cfg { u32 merge_3d_count; const struct dpu_merge_3d_cfg *merge_3d;
+ u32 dsc_count; + struct dpu_dsc_cfg *dsc; + u32 intf_count; const struct dpu_intf_cfg *intf;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c new file mode 100644 index 000000000000..449d6f1dad28 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, Linaro Limited + */ + +#include "dpu_kms.h" +#include "dpu_hw_catalog.h" +#include "dpu_hwio.h" +#include "dpu_hw_mdss.h" +#include "dpu_hw_dsc.h" + +#define DSC_COMMON_MODE 0x000 +#define DSC_ENC 0X004 +#define DSC_PICTURE 0x008 +#define DSC_SLICE 0x00C +#define DSC_CHUNK_SIZE 0x010 +#define DSC_DELAY 0x014 +#define DSC_SCALE_INITIAL 0x018 +#define DSC_SCALE_DEC_INTERVAL 0x01C +#define DSC_SCALE_INC_INTERVAL 0x020 +#define DSC_FIRST_LINE_BPG_OFFSET 0x024 +#define DSC_BPG_OFFSET 0x028 +#define DSC_DSC_OFFSET 0x02C +#define DSC_FLATNESS 0x030 +#define DSC_RC_MODEL_SIZE 0x034 +#define DSC_RC 0x038 +#define DSC_RC_BUF_THRESH 0x03C +#define DSC_RANGE_MIN_QP 0x074 +#define DSC_RANGE_MAX_QP 0x0B0 +#define DSC_RANGE_BPG_OFFSET 0x0EC + +static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) +{ + struct dpu_hw_blk_reg_map *c = &dsc->hw; + + DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); +} + +static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, + struct msm_display_dsc_config *dsc, u32 mode) +{ + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; + u32 data, lsb, bpp; + u32 initial_lines = dsc->initial_lines; + bool is_cmd_mode = !(mode & DSC_MODE_VIDEO); + + DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); + + if (is_cmd_mode) + initial_lines += 1; + + data = (initial_lines << 20); + data |= ((dsc->slice_last_group_size - 1) << 18); + /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ + data |= dsc->drm->bits_per_pixel << 12; + lsb = dsc->drm->bits_per_pixel % 4; + bpp = dsc->drm->bits_per_pixel / 4; + bpp *= 4; + bpp <<= 4; + bpp |= lsb; + + data |= bpp << 8; + data |= (dsc->drm->block_pred_enable << 7); + data |= (dsc->drm->line_buf_depth << 3); + data |= (dsc->drm->simple_422 << 2); + data |= (dsc->drm->convert_rgb << 1); + data |= dsc->drm->bits_per_component; + + DPU_REG_WRITE(c, DSC_ENC, data); + + data = dsc->drm->pic_width << 16; + data |= dsc->drm->pic_height; + DPU_REG_WRITE(c, DSC_PICTURE, data); + + data = dsc->drm->slice_width << 16; + data |= dsc->drm->slice_height; + DPU_REG_WRITE(c, DSC_SLICE, data); + + data = dsc->drm->slice_chunk_size << 16; + DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); + + data = dsc->drm->initial_dec_delay << 16; + data |= dsc->drm->initial_xmit_delay; + DPU_REG_WRITE(c, DSC_DELAY, data); + + data = dsc->drm->initial_scale_value; + DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); + + data = dsc->drm->scale_decrement_interval; + DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); + + data = dsc->drm->scale_increment_interval; + DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); + + data = dsc->drm->first_line_bpg_offset; + DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data); + + data = dsc->drm->nfl_bpg_offset << 16; + data |= dsc->drm->slice_bpg_offset; + DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); + + data = dsc->drm->initial_offset << 16; + data |= dsc->drm->final_offset; + DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); + + data = dsc->det_thresh_flatness << 10; + data |= dsc->drm->flatness_max_qp << 5; + data |= dsc->drm->flatness_min_qp; + DPU_REG_WRITE(c, DSC_FLATNESS, data); + + data = dsc->drm->rc_model_size; + DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data); + + data = dsc->drm->rc_tgt_offset_low << 18; + data |= dsc->drm->rc_tgt_offset_high << 14; + data |= dsc->drm->rc_quant_incr_limit1 << 9; + data |= dsc->drm->rc_quant_incr_limit0 << 4; + data |= dsc->drm->rc_edge_factor; + DPU_REG_WRITE(c, DSC_RC, data); +} + +static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, + struct msm_display_dsc_config *dsc) +{ + struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params; + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; + u32 off; + int i; + + off = DSC_RC_BUF_THRESH; + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) { + DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]); + off += 4; + } + + off = DSC_RANGE_MIN_QP; + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + DPU_REG_WRITE(c, off, rc[i].range_min_qp); + off += 4; + } + + off = DSC_RANGE_MAX_QP; + for (i = 0; i < 15; i++) { + DPU_REG_WRITE(c, off, rc[i].range_max_qp); + off += 4; + } + + off = DSC_RANGE_BPG_OFFSET; + for (i = 0; i < 15; i++) { + DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); + off += 4; + } +} + +static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, + struct dpu_mdss_cfg *m, + void __iomem *addr, + struct dpu_hw_blk_reg_map *b) +{ + int i; + + for (i = 0; i < m->dsc_count; i++) { + if (dsc == m->dsc[i].id) { + b->base_off = addr; + b->blk_off = m->dsc[i].base; + b->length = m->dsc[i].len; + b->hwversion = m->hwversion; + b->log_mask = DPU_DBG_MASK_DSC; + return &m->dsc[i]; + } + } + + return NULL; +} + +static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, + unsigned long cap) +{ + ops->dsc_disable = dpu_hw_dsc_disable; + ops->dsc_config = dpu_hw_dsc_config; + ops->dsc_config_thresh = dpu_hw_dsc_config_thresh; +}; + +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, + struct dpu_mdss_cfg *m) +{ + struct dpu_hw_dsc *c; + struct dpu_dsc_cfg *cfg; + + c = kzalloc(sizeof(*c), GFP_KERNEL); + if (!c) + return ERR_PTR(-ENOMEM); + + cfg = _dsc_offset(idx, m, addr, &c->hw); + if (IS_ERR_OR_NULL(cfg)) { + kfree(c); + return ERR_PTR(-EINVAL); + } + + c->idx = idx; + c->caps = cfg; + _setup_dsc_ops(&c->ops, c->caps->features); + + return c; +} + +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc) +{ + kfree(dsc); +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h new file mode 100644 index 000000000000..648c9e4d8749 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2020-2021, Linaro Limited */ + +#ifndef _DPU_HW_DSC_H +#define _DPU_HW_DSC_H + +#include <drm/drm_dsc.h> + +#define DSC_MODE_SPLIT_PANEL BIT(0) +#define DSC_MODE_MULTIPLEX BIT(1) +#define DSC_MODE_VIDEO BIT(2) + +struct dpu_hw_dsc; + +/** + * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions + * Assumption is these functions will be called after clocks are enabled + */ +struct dpu_hw_dsc_ops { + /** + * dsc_disable - disable dsc + * @hw_dsc: Pointer to dsc context + */ + void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc); + + /** + * dsc_config - configures dsc encoder + * @hw_dsc: Pointer to dsc context + * @dsc: panel dsc parameters + * @mode: dsc topology mode to be set + */ + void (*dsc_config)(struct dpu_hw_dsc *hw_dsc, + struct msm_display_dsc_config *dsc, u32 mode); + + /** + * dsc_config_thresh - programs panel thresholds + * @hw_dsc: Pointer to dsc context + * @dsc: panel dsc parameters + */ + void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc, + struct msm_display_dsc_config *dsc); +}; + +struct dpu_hw_dsc { + struct dpu_hw_blk base; + struct dpu_hw_blk_reg_map hw; + + /* dsc */ + enum dpu_dsc idx; + const struct dpu_dsc_cfg *caps; + + /* ops */ + struct dpu_hw_dsc_ops ops; +}; + +/** + * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx. + * @idx: DSC index for which driver object is required + * @addr: Mapped register io address of MDP + * @m: Pointer to mdss catalog data + * Returns: Error code or allocated dpu_hw_dsc context + */ +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, + struct dpu_mdss_cfg *m); + +/** + * dpu_hw_dsc_destroy - destroys dsc driver context + * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init + */ +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc); + +static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw) +{ + return container_of(hw, struct dpu_hw_dsc, base); +} + +#endif /* _DPU_HW_DSC_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index bb9ceadeb0bb..b0ce8cb97d22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -97,6 +97,7 @@ enum dpu_hw_blk_type { DPU_HW_BLK_WB, DPU_HW_BLK_DSPP, DPU_HW_BLK_MERGE_3D, + DPU_HW_BLK_DSC, DPU_HW_BLK_MAX, };
@@ -176,6 +177,17 @@ enum dpu_ctl { CTL_MAX };
+enum dpu_dsc { + DSC_NONE = 0, + DSC_0, + DSC_1, + DSC_2, + DSC_3, + DSC_4, + DSC_5, + DSC_MAX +}; + enum dpu_pingpong { PINGPONG_0 = 1, PINGPONG_1, @@ -437,5 +449,6 @@ struct dpu_mdss_color { #define DPU_DBG_MASK_VBIF (1 << 8) #define DPU_DBG_MASK_ROT (1 << 9) #define DPU_DBG_MASK_DSPP (1 << 10) +#define DPU_DBG_MASK_DSC (1 << 11)
#endif /* _DPU_HW_MDSS_H */
On 16/11/2021 09:22, Vinod Koul wrote:
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
In SDM845, DSC can be enabled by writing to pingpong block registers, so add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar abhinavk@codeaurora.org Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul vkoul@kernel.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++ 2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 55766c97c4c8..47c6ab6caf95 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -28,6 +28,9 @@ #define PP_FBC_MODE 0x034 #define PP_FBC_BUDGET_CTL 0x038 #define PP_FBC_LOSSY_MODE 0x03C +#define PP_DSC_MODE 0x0a0 +#define PP_DCE_DATA_IN_SWAP 0x0ac +#define PP_DCE_DATA_OUT_SWAP 0x0c8
#define PP_DITHER_EN 0x000 #define PP_DITHER_BITDEPTH 0x004 @@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) return line; }
+static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *c = &pp->hw; + + DPU_REG_WRITE(c, PP_DSC_MODE, 1); + return 0; +} + +static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *c = &pp->hw; + + DPU_REG_WRITE(c, PP_DSC_MODE, 0); +} + +static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp) +{ + struct dpu_hw_blk_reg_map *pp_c = &pp->hw; + int data; + + data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP); + data |= BIT(18); /* endian flip */ + DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data); + return 0; +} + static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, unsigned long features) { @@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; c->ops.get_line_count = dpu_hw_pp_get_line_count; + c->ops.setup_dsc = dpu_hw_pp_setup_dsc; + c->ops.enable_dsc = dpu_hw_pp_dsc_enable; + c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
if (test_bit(DPU_PINGPONG_DITHER, &features)) c->ops.setup_dither = dpu_hw_pp_setup_dither; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 89d08a715c16..12758468d9ca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops { */ void (*setup_dither)(struct dpu_hw_pingpong *pp, struct dpu_hw_dither_cfg *cfg); + /** + * Enable DSC + */ + int (*enable_dsc)(struct dpu_hw_pingpong *pp); + + /** + * Disable DSC + */ + void (*disable_dsc)(struct dpu_hw_pingpong *pp); + + /** + * Setup DSC + */ + int (*setup_dsc)(struct dpu_hw_pingpong *pp); };
struct dpu_hw_merge_3d;
On 2021-11-16 11:52:46, Vinod Koul wrote:
In SDM845, DSC can be enabled by writing to pingpong block registers, so add support for DSC in hw_pp
Nit: I don't think the ", so add support for DSC in XXX" part in this and other commit messages add anything. You've already stated that in the title, the commit body is just extra justification (and can perhaps be filled with extra details about the patch contents instead).
This enum does not seem used here, is it used in another patch?
It looks like most other callbacks in dpu1 use an `enable` function with a boolean, instead of having a separate disable function. That should simplify the implementation down to a single ternary-if, too. Would that be desired to use here?
- Marijn
On 18/02/2022 00:54, Marijn Suijten wrote:
Just my 2c. I personally hate the unified functions with the boolean argument. One of the reasons being the return value. Typically you do not expect that the disable function can fail (or return an error). But the unified function provides an error (to be handled) even in the disable case.
Last, but not least, overall the kernel API is biased towards separate enable and disable calls.
On 2022-02-18 01:12:02, Dmitry Baryshkov wrote:
Fair enough, we should replace the other functions then. Or perhaps drop the return argument entirely, it's always zero for enable_dsc anyway. I doubt we'll ever add additional checks here? If we do, things can be split again.
- Marijn
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul vkoul@kernel.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce6f32a919e5..c773bbe57b6b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -821,6 +821,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), }; + +/************************************************************* + * DSC sub blocks config + *************************************************************/ +#define DSC_BLK(_name, _id, _base) \ + {\ + .name = _name, .id = _id, \ + .base = _base, .len = 0x140, \ + .features = 0, \ + } + +static struct dpu_dsc_cfg sdm845_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000), + DSC_BLK("dsc_1", DSC_1, 0x80400), + DSC_BLK("dsc_2", DSC_2, 0x80800), + DSC_BLK("dsc_3", DSC_3, 0x80c00), +}; + /************************************************************* * INTF sub blocks config *************************************************************/ @@ -1124,6 +1142,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .mixer = sdm845_lm, .pingpong_count = ARRAY_SIZE(sdm845_pp), .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm845_dsc), + .dsc = sdm845_dsc, .intf_count = ARRAY_SIZE(sdm845_intf), .intf = sdm845_intf, .vbif_count = ARRAY_SIZE(sdm845_vbif),
We cannot enable mode_3d when we are using the DSC. So pass configuration to detect DSC is enabled and not enable mode_3d when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 4 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index e7270eb6b84b..efb85d595598 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( return BLEND_3D_NONE; }
+static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc = phys_enc->parent; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + + if (priv->dsc) + return priv->dsc->dsc_mask; + + return 0; +} + /** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 34a6940d12c5..f3f00f4d0193 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); + ctl->ops.setup_intf_cfg(ctl, &intf_cfg); }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb983e..36831457a91b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
intf_cfg |= (cfg->intf & 0xF) << 4;
- if (cfg->mode_3d) { + /* In DSC we can't set merge, so check for dsc too */ + if (cfg->mode_3d && !cfg->dsc) { intf_cfg |= BIT(19); intf_cfg |= (cfg->mode_3d - 0x1) << 20; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..9847c9c46d6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid * @stream_sel: Stream selection for multi-stream interfaces + * @dsc: DSC BIT masks */ struct dpu_hw_intf_cfg { enum dpu_intf intf; @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; int stream_sel; + unsigned int dsc; };
/**
On 16/11/2021 09:22, Vinod Koul wrote:
I'd prefer if we disable mode_3d here, rather than ignoring it in the dpu_hw_ctl_intf_cfg()
I think here'd better have WARN_ON(cfg->mode_3d && cfg->dsc) or similar dev_warn().
On Wed, 24 Nov 2021 at 18:40, Dmitry Baryshkov dmitry.baryshkov@linaro.org wrote:
Here you are returning the mask, so it should not be bool.
Please ignore this comment, dsc mask already exists.
Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 36831457a91b..66b0c44118d8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff
@@ -120,7 +123,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { - if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -498,6 +500,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 mode_sel = 0;
+ if (cfg->dsc) + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc); + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17);
@@ -509,6 +514,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->dsc) { + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + } }
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
On 16/11/2021 09:22, Vinod Koul wrote:
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
We need to configure the encoder for DSC configuration and calculate DSC parameters for the given timing so this patch adds that support by adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 140 +++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e7ee4cfb8461..f2ff8a504918 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -21,6 +21,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_ctl.h" #include "dpu_hw_dspp.h" +#include "dpu_hw_dsc.h" #include "dpu_formats.h" #include "dpu_encoder_phys.h" #include "dpu_crtc.h" @@ -136,6 +137,7 @@ enum dpu_enc_rc_states { * @cur_slave: As above but for the slave encoder. * @hw_pp: Handle to the pingpong blocks used for the display. No. * pingpong blocks can be different than num_phys_encs. + * @hw_dsc: Handle to the DSC blocks used for the display. * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped * for partial update right-only cases, such as pingpong * split where virtual pingpong does not generate IRQs @@ -182,6 +184,7 @@ struct dpu_encoder_virt { struct dpu_encoder_phys *cur_master; struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
bool intfs_swapped;
@@ -972,7 +975,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; - int num_lm, num_ctl, num_pp; + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; + int num_lm, num_ctl, num_pp, num_dsc; int i, j;
if (!drm_enc) { @@ -1030,6 +1034,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL;
+ if (priv->dsc) { + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_DSC, + hw_dsc, ARRAY_SIZE(hw_dsc)); + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL; + } + cstate = to_dpu_crtc_state(drm_crtc->state);
for (i = 0; i < num_lm; i++) { @@ -1772,10 +1784,132 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) nsecs_to_jiffies(ktime_to_ns(wakeup_time))); }
+static void +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width) +{ + int slice_count, slice_per_intf; + int bytes_in_slice, total_bytes_per_intf; + + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) { + DPU_ERROR("Invalid DSC/slices\n"); + return; + } + + slice_count = dsc->drm->slice_count; + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width); + + /* + * If slice_count is greater than slice_per_intf then default to 1. + * This can happen during partial update. + */ + if (slice_count > slice_per_intf) + slice_count = 1; + + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * + dsc->drm->bits_per_pixel, 8); + total_bytes_per_intf = bytes_in_slice * slice_per_intf; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); + dsc->bytes_in_slice = bytes_in_slice; + dsc->bytes_per_pkt = bytes_in_slice * slice_count; + dsc->pkt_per_line = slice_per_intf / slice_count; +} + +static void +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc, + u32 enc_ip_width) +{ + int ssm_delay, total_pixels, soft_slice_per_enc; + + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width; + + /* + * minimum number of initial line pixels is a sum of: + * 1. sub-stream multiplexer delay (83 groups for 8bpc, + * 91 for 10 bpc) * 3 + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 + * 3. the initial xmit delay + * 4. total pipeline delay through the "lock step" of encoder (47) + * 5. 6 additional pixels as the output of the rate buffer is + * 48 bits wide + */ + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92); + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47; + if (soft_slice_per_enc > 1) + total_pixels += (ssm_delay * 3); + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width); +} + +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc, + struct dpu_hw_pingpong *hw_pp, + struct msm_display_dsc_config *dsc, + u32 common_mode) +{ + if (hw_dsc->ops.dsc_config) + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode); + + if (hw_dsc->ops.dsc_config_thresh) + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); + + if (hw_pp->ops.setup_dsc) + hw_pp->ops.setup_dsc(hw_pp); + + if (hw_pp->ops.enable_dsc) + hw_pp->ops.enable_dsc(hw_pp); +} + +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, + struct msm_display_dsc_config *dsc) +{ + /* coding only for 2LM, 2enc, 1 dsc config */ + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; + int this_frame_slices; + int intf_ip_w, enc_ip_w; + int dsc_common_mode; + int pic_width; + int i; + + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { + hw_pp[i] = dpu_enc->hw_pp[i]; + hw_dsc[i] = dpu_enc->hw_dsc[i]; + + if (!hw_pp[i] || !hw_dsc[i]) { + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); + return; + } + } + + dsc_common_mode = 0; + pic_width = dsc->drm->pic_width; + + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; + if (enc_master->intf_mode == INTF_MODE_VIDEO) + dsc_common_mode |= DSC_MODE_VIDEO; + + this_frame_slices = pic_width / dsc->drm->slice_width; + intf_ip_w = this_frame_slices * dsc->drm->slice_width; + + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w); + + /* + * dsc merge case: when using 2 encoders for the same stream, + * no. of slices need to be same on both the encoders. + */ + enc_ip_w = intf_ip_w / 2; + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); + + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode); +} + void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; struct dpu_encoder_phys *phys; + struct msm_drm_private *priv; bool needs_hw_reset = false; unsigned int i;
@@ -1803,6 +1937,10 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); } } + + priv = drm_enc->dev->dev_private; + if (priv->dsc) + dpu_encoder_prep_dsc(dpu_enc, priv->dsc); }
void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
Somehow documentation for dspp was missed, so add that
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/msm_drv.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index de7cb65bfc52..c4a588ad226e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -102,6 +102,7 @@ enum msm_event_wait { * @num_lm: number of layer mixers used * @num_enc: number of compression encoder blocks used * @num_intf: number of interfaces the panel is mounted on + * @num_dspp: number of dspp blocks used */ struct msm_display_topology { u32 num_lm;
For DSC to work we typically need a 2,2,1 configuration. This should suffice for resolutions up to 4k. For more resolutions like 8k this won't work.
Also, it is better to use 2 LMs and DSC instances as half width results in lesser power consumption as compared to single LM, DSC at full width.
The panel has been tested only with 2,2,1 configuration, so for now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar abhinavk@codeaurora.org Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.h | 2 ++ 2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f2ff8a504918..12f58de88ac7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -533,6 +533,8 @@ static struct msm_display_topology dpu_encoder_get_topology( struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; + struct drm_encoder *drm_enc; + struct msm_drm_private *priv; int i, intf_count = 0;
for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) @@ -567,8 +569,24 @@ static struct msm_display_topology dpu_encoder_get_topology( topology.num_enc = 0; topology.num_intf = intf_count;
+ drm_enc = &dpu_enc->base; + priv = drm_enc->dev->dev_private; + if (priv && priv->dsc) { + /* In case of Display Stream Compression DSC, we would use + * 2 encoders, 2 line mixers and 1 interface + * this is power optimal and can drive up to (including) 4k + * screens + */ + topology.num_enc = 2; + topology.num_dsc = 2; + topology.num_intf = 1; + topology.num_lm = 2; + priv->dsc->dsc_mask = BIT(0) | BIT(1); + } + return topology; } + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index c4a588ad226e..d6b25d77700e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -103,12 +103,14 @@ enum msm_event_wait { * @num_enc: number of compression encoder blocks used * @num_intf: number of interfaces the panel is mounted on * @num_dspp: number of dspp blocks used + * @num_dsc: number of Display Stream Compression (DSC) blocks used */ struct msm_display_topology { u32 num_lm; u32 num_enc; u32 num_intf; u32 num_dspp; + u32 num_dsc; };
/**
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 +++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + 3 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 775bcbda860f..fd6672efb096 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -146,6 +146,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; };
struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9c83d6e427a..c9d0fc765aaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -11,6 +11,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_dsc.h" #include "dpu_encoder.h" #include "dpu_trace.h"
@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_intf_destroy(hw); } } + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) { + struct dpu_hw_dsc *hw; + + if (rm->dsc_blks[i]) { + hw = to_dpu_hw_dsc(rm->dsc_blks[i]); + dpu_hw_dsc_destroy(hw); + } + }
return 0; } @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; }
+ for (i = 0; i < cat->dsc_count; i++) { + struct dpu_hw_dsc *hw; + const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; + + hw = dpu_hw_dsc_init(dsc->id, mmio, cat); + if (IS_ERR_OR_NULL(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed dsc object creation: err %d\n", rc); + goto fail; + } + rm->dsc_blks[dsc->id - DSC_0] = &hw->base; + } + return 0;
fail: @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf( }
global_state->intf_to_enc_id[idx] = enc_id; + return 0; }
@@ -500,6 +523,38 @@ static int _dpu_rm_reserve_intf_related_hw( return ret; }
+static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_encoder *enc, + const struct msm_display_topology *top) +{ + struct msm_drm_private *priv; + int num_dsc = top->num_dsc; + int i; + + priv = enc->dev->dev_private; + + if (!priv) + return -EIO; + + /* check if DSC is supported */ + if (!priv->dsc) + return 0; + + /* check if DSC required are allocated or not */ + for (i = 0; i < num_dsc; i++) { + if (global_state->dsc_to_enc_id[i]) { + DPU_ERROR("DSC %d is already allocated\n", i); + return -EIO; + } + } + + for (i = 0; i < num_dsc; i++) + global_state->dsc_to_enc_id[i] = enc->base.id; + + return 0; +} + static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, @@ -526,6 +581,10 @@ static int _dpu_rm_make_reservation( if (ret) return ret;
+ ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + if (ret) + return ret; + return ret; }
@@ -567,6 +626,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->intf_to_enc_id, ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id); + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); }
int dpu_rm_reserve( @@ -640,6 +701,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->dspp_to_enc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; + case DPU_HW_BLK_DSC: + hw_blks = rm->dsc_blks; + hw_to_enc_id = global_state->dsc_to_enc_id; + max_blks = ARRAY_SIZE(rm->dsc_blks); + break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..278d2a510b80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -30,6 +30,7 @@ struct dpu_rm { struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
uint32_t lm_max_width; };
Add a mode valid callback for dsi_mgr for checking mode being valid in case of DSC. For DSC the height and width needs to be multiple of slice, so we check that here
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/dsi/dsi.h | 2 ++ drivers/gpu/drm/msm/dsi/dsi_host.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ++++++++++++ 3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 569c8ff062ba..e7affab2fc1e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -115,6 +115,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, + const struct drm_display_mode *mode); struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 30c1e299aa52..31d385d8d834 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2588,6 +2588,32 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, return 0; }
+enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, + const struct drm_display_mode *mode) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + struct msm_display_dsc_config *dsc = msm_host->dsc; + int pic_width = mode->hdisplay; + int pic_height = mode->vdisplay; + + if (!msm_host->dsc) + return MODE_OK; + + if (pic_width % dsc->drm->slice_width) { + pr_err("DSI: pic_width %d has to be multiple of slice %d\n", + pic_width, dsc->drm->slice_width); + return MODE_H_ILLEGAL; + } + + if (pic_height % dsc->drm->slice_height) { + pr_err("DSI: pic_height %d has to be multiple of slice %d\n", + pic_height, dsc->drm->slice_height); + return MODE_V_ILLEGAL; + } + + return MODE_OK; +} + struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) { return of_drm_find_panel(to_msm_dsi_host(host)->device_node); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 20c4d650fd80..0ad8a53aaa0e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -579,6 +579,17 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge, msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode); }
+static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + int id = dsi_mgr_bridge_get_id(bridge); + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct mipi_dsi_host *host = msm_dsi->host; + + return msm_dsi_host_check_dsc(host, mode); +} + static const struct drm_connector_funcs dsi_mgr_connector_funcs = { .detect = dsi_mgr_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, @@ -600,6 +611,7 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = { .disable = dsi_mgr_bridge_disable, .post_disable = dsi_mgr_bridge_post_disable, .mode_set = dsi_mgr_bridge_mode_set, + .mode_valid = dsi_mgr_bridge_mode_valid, };
/* initialize connector when we're connected to a drm_panel */
On 16/11/2021 09:22, Vinod Koul wrote:
Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org
When DSC is enabled, we need to configure DSI registers accordingly and configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and timing information and configure these registers.
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++ drivers/gpu/drm/msm/dsi/dsi_host.c | 113 ++++++++++++++++++++++++++++- 2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 49b551ad1bff..c1c85df58c4b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c + +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8 + +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac + #endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 31d385d8d834..2c14c36f0b3d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); }
+static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc, + int pic_width, int pic_height) +{ + if (!dsc || !pic_width || !pic_height) { + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height); + return -EINVAL; + } + + dsc->drm->pic_width = pic_width; + dsc->drm->pic_height = pic_height; + + return 0; +} + static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { struct drm_display_mode *mode = msm_host->mode; @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) hdisplay /= 2; }
+ if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + + /* update dsc params with timing params */ + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay); + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height); + + /* we do the calculations for dsc parameters here so that + * panel can use these parameters + */ + dsi_populate_dsc_params(dsc); + + /* Divide the display by 3 but keep back/font porch and + * pulse width same + */ + h_total -= hdisplay; + hdisplay /= 3; + h_total += hdisplay; + ha_end = ha_start + hdisplay; + } + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { + if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + u32 reg, intf_width, slice_per_intf; + u32 total_bytes_per_intf; + + /* first calculate dsc parameters and then program + * compress mode registers + */ + intf_width = hdisplay; + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width); + + dsc->drm->slice_count = 1; + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8); + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count; + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; + + reg = dsc->bytes_per_pkt << 16; + reg |= (0x0b << 8); /* dtype of compressed image */ + + /* pkt_per_line: + * 0 == 1 pkt + * 1 == 2 pkt + * 2 == 4 pkt + * 3 pkt is not supported + * above translates to ffs() - 1 + */ + reg |= (ffs(dsc->pkt_per_line) - 1) << 6; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + reg |= dsc->eol_byte_num << 4; + reg |= 1; + + dsi_write(msm_host, + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); + } + dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ + if (msm_host->dsc) { + struct msm_display_dsc_config *dsc = msm_host->dsc; + u32 reg, reg_ctrl, reg_ctrl2; + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf; + + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); + + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width); + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * + dsc->drm->bits_per_pixel, 8); + dsc->drm->slice_chunk_size = bytes_in_slice; + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; + + reg = 0x39 << 8; + reg |= ffs(dsc->pkt_per_line) << 6; + + dsc->eol_byte_num = total_bytes_per_intf % 3; + reg |= dsc->eol_byte_num << 4; + reg |= 1; + + reg_ctrl |= reg; + reg_ctrl2 |= bytes_in_slice; + + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); + } + /* image data and 1 byte write_memory_start cmd */ - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + if (!msm_host->dsc) + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + else + wc = mode->hdisplay / 2 + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | @@ -2051,9 +2158,13 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; + struct msm_drm_private *priv; int ret;
msm_host->dev = dev; + priv = dev->dev_private; + priv->dsc = msm_host->dsc; + ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); if (ret) { pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
Hi Vinod,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next] [also build test WARNING on v5.16-rc1 next-20211118] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vinod-Koul/drm-msm-Add-Display-Stre... base: git://anongit.freedesktop.org/drm/drm drm-next config: arm64-randconfig-r036-20211118 (attached as .config) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm64 cross compiling tool for clang build # apt-get install binutils-aarch64-linux-gnu # https://github.com/0day-ci/linux/commit/0d90631d88b4295b0612892e62110dd3b11c... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Vinod-Koul/drm-msm-Add-Display-Stream-Compression-Support/20211116-142602 git checkout 0d90631d88b4295b0612892e62110dd3b11c9d78 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=arm64
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot lkp@intel.com
All warnings (new ones prefixed by >>):
drivers/gpu/drm/msm/dsi/dsi_host.c:1039:13: warning: variable 'reg_ctrl' set but not used [-Wunused-but-set-variable]
u32 reg, reg_ctrl, reg_ctrl2; ^ 1 warning generated.
vim +/reg_ctrl +1039 drivers/gpu/drm/msm/dsi/dsi_host.c
924 925 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 926 { 927 struct drm_display_mode *mode = msm_host->mode; 928 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 929 u32 h_total = mode->htotal; 930 u32 v_total = mode->vtotal; 931 u32 hs_end = mode->hsync_end - mode->hsync_start; 932 u32 vs_end = mode->vsync_end - mode->vsync_start; 933 u32 ha_start = h_total - mode->hsync_start; 934 u32 ha_end = ha_start + mode->hdisplay; 935 u32 va_start = v_total - mode->vsync_start; 936 u32 va_end = va_start + mode->vdisplay; 937 u32 hdisplay = mode->hdisplay; 938 u32 wc; 939 940 DBG(""); 941 942 /* 943 * For bonded DSI mode, the current DRM mode has 944 * the complete width of the panel. Since, the complete 945 * panel is driven by two DSI controllers, the horizontal 946 * timings have to be split between the two dsi controllers. 947 * Adjust the DSI host timing values accordingly. 948 */ 949 if (is_bonded_dsi) { 950 h_total /= 2; 951 hs_end /= 2; 952 ha_start /= 2; 953 ha_end /= 2; 954 hdisplay /= 2; 955 } 956 957 if (msm_host->dsc) { 958 struct msm_display_dsc_config *dsc = msm_host->dsc; 959 960 /* update dsc params with timing params */ 961 dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay); 962 DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height); 963 964 /* we do the calculations for dsc parameters here so that 965 * panel can use these parameters 966 */ 967 dsi_populate_dsc_params(dsc); 968 969 /* Divide the display by 3 but keep back/font porch and 970 * pulse width same 971 */ 972 h_total -= hdisplay; 973 hdisplay /= 3; 974 h_total += hdisplay; 975 ha_end = ha_start + hdisplay; 976 } 977 978 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 979 if (msm_host->dsc) { 980 struct msm_display_dsc_config *dsc = msm_host->dsc; 981 u32 reg, intf_width, slice_per_intf; 982 u32 total_bytes_per_intf; 983 984 /* first calculate dsc parameters and then program 985 * compress mode registers 986 */ 987 intf_width = hdisplay; 988 slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width); 989 990 dsc->drm->slice_count = 1; 991 dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8); 992 total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; 993 994 dsc->eol_byte_num = total_bytes_per_intf % 3; 995 dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3); 996 dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count; 997 dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; 998 999 reg = dsc->bytes_per_pkt << 16; 1000 reg |= (0x0b << 8); /* dtype of compressed image */ 1001 1002 /* pkt_per_line: 1003 * 0 == 1 pkt 1004 * 1 == 2 pkt 1005 * 2 == 4 pkt 1006 * 3 pkt is not supported 1007 * above translates to ffs() - 1 1008 */ 1009 reg |= (ffs(dsc->pkt_per_line) - 1) << 6; 1010 1011 dsc->eol_byte_num = total_bytes_per_intf % 3; 1012 reg |= dsc->eol_byte_num << 4; 1013 reg |= 1; 1014 1015 dsi_write(msm_host, 1016 REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 1017 } 1018 1019 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1020 DSI_ACTIVE_H_START(ha_start) | 1021 DSI_ACTIVE_H_END(ha_end)); 1022 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1023 DSI_ACTIVE_V_START(va_start) | 1024 DSI_ACTIVE_V_END(va_end)); 1025 dsi_write(msm_host, REG_DSI_TOTAL, 1026 DSI_TOTAL_H_TOTAL(h_total - 1) | 1027 DSI_TOTAL_V_TOTAL(v_total - 1)); 1028 1029 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1030 DSI_ACTIVE_HSYNC_START(hs_start) | 1031 DSI_ACTIVE_HSYNC_END(hs_end)); 1032 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1033 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1034 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1035 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1036 } else { /* command mode */ 1037 if (msm_host->dsc) { 1038 struct msm_display_dsc_config *dsc = msm_host->dsc;
1039 u32 reg, reg_ctrl, reg_ctrl2;
1040 u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf; 1041 1042 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 1043 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 1044 1045 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width); 1046 bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 1047 dsc->drm->bits_per_pixel, 8); 1048 dsc->drm->slice_chunk_size = bytes_in_slice; 1049 total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf; 1050 dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count; 1051 1052 reg = 0x39 << 8; 1053 reg |= ffs(dsc->pkt_per_line) << 6; 1054 1055 dsc->eol_byte_num = total_bytes_per_intf % 3; 1056 reg |= dsc->eol_byte_num << 4; 1057 reg |= 1; 1058 1059 reg_ctrl |= reg; 1060 reg_ctrl2 |= bytes_in_slice; 1061 1062 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg); 1063 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 1064 } 1065 1066 /* image data and 1 byte write_memory_start cmd */ 1067 if (!msm_host->dsc) 1068 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 1069 else 1070 wc = mode->hdisplay / 2 + 1; 1071 1072 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1073 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1074 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1075 msm_host->channel) | 1076 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1077 MIPI_DSI_DCS_LONG_WRITE)); 1078 1079 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1080 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1081 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1082 } 1083 } 1084
--- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 16/11/2021 09:22, Vinod Koul wrote:
I have been thinking about this piece. I highly dislike the priv->dsc field for multiple reasons.
Please correct me if I'm wrong, we use it for several reasons: - to check if DSC is requested at all - to store the dsc_mask
The DSC mask should be calculated basing on dpu_encoder_virt->hw_dsc[] values, so it can be removed from msm_display_dsc_config.
To check whether DSC is enabled, I'd suggest the following:
- Add use_dsc flag to struct msm_display_info. This way it would be generic to all possible encoders which can use DSC.
- Add struct msm_dsi_has_dsc_panel() function. It checks whether msm_host has ->dsc data. Feel free to change the name of the function to better suit your style.
- Call msm_dsi_has_dsc_panel() from _dpu_kms_initialize_dsi(). If DSC is requested, set info->use_dsc.
- In dpu_encoder_setup store use_dsc in struct dpu_encoder_virt() and use it later instead of checking priv->dsc.
WDYT?
On 24/11/2021 19:21, Dmitry Baryshkov wrote:
I forgot about the patch 2, which actually uses priv->dsc data. The overall idea would be the same, get data pointer from msm_dsi and pass it through the msm_display_info.
Hi Vinod,
On 2021-11-16 11:52:55, Vinod Koul wrote:
I presume you are aware that these files are autogenerated, but there does not seem to be any link to patches adding these registers to the XML files in either envytools to mesa, nor could I find any merge/pull requests on the matter. Would you mind posting those? Before doing so though, consider the comment below about register mapping.
This function - adopted from downstream - does not seem to perform a whole lot, especially without the modulo checks against the slice size. Perhaps it can be inlined?
This seems to be pretty non-standard and perhaps unnecessary debug code, with a stray dash in there. Is is needed here, and if so how about using %dx%d\n to format width and height?
A more general nit on the comments in this patch series: it is appreciated if comments explain the rationale rather than - or in addition to - merely paraphrasing the code that follows.
If I am not mistaken this is the same value as dsc->drm->slice_width, since a multiple of 8 is inherently "a multiple of 8" and hence needs no rounding when divided by 8 again.
Also note that the cmdmode variant below uses bits_per_pixel here; is that discrepancy intended?
This was already calculated and assigned just a couple lines above.
Note that the XML register file exists to map out the layout of these registers, including bit offset, size, and (enum) constant values. It is appreciated if you can replace all these magical shifts and magic flags/bits with the appropriate enum constants and constructor functions, after mapping them out in the XML file.
Shouldn't old values be masked out first, before writing new bits or values below? The video-mode variant doesn't read back old register values.
Same comment about moving magic constants and shifts into the XML file.
Doesn't the calculation need -1 here just like video mode?
Thanks!
- Marijn
Hi Marijn,
On 11-12-21, 01:03, Marijn Suijten wrote:
Most of the code here is :)
This was split from downstream code to check and update dimension. We can inline this, or should we leave that to compiler. I am not a very big fan of inlining...
I can update that, sure...
Yes it might be the case here, but in this case I wanted to explicitly point out hat we need to divide display by 3...
Yes this doesnt look right, I will update
Also note that the cmdmode variant below uses bits_per_pixel here; is that discrepancy intended?
Nope both should use bits_per_pixel..
Yup, dropped now.
Yeah I am trying to get those details, if I manage to get it, will update for sure as Dmitry already pointed in MESA PR.
This follows downstream where the registers are read, modified and written back
yes if we get details of bits
yes will update now
Hi Vinod,
Thanks for taking time to go through this review, please find some clarifications below.
On 2022-02-17 16:44:04, Vinod Koul wrote:
It doesn't seem beneficial to code readability to have this function, which is only called just once and also has the same struct members read in a `DBG()` directly, abstracted away to a function. Not really concerned about generated code/performance FWIW.
Also note that the caller isn't checking the `-EINVAL` result...
That is, the result code here should be checked (or function inlined).
The main point here is justifying _why_ there's a division by 3 for the active portion of the signal, I presume that's the compression ratio (having not read into the DSC compression standard yet at all)?
That'd be lovely. In any case, even if you can't get the meaning for all these bits, offsets and constants, it's still desired to at least add them to the XML as "unknown" or something (including offset in the name). Then perhaps the details can be filled in over time while keeping the driver free of magic constants. See for example how some of the Adreno register XML descriptions set this up.
For example, without those details we can already state that `eol_byte_num` has an offset of 4 in the MODE_CTL register, and probably a size of 2 bits since its value is always modulo 3. Likewise pkt_per_line can be turned into an `<enum>` and so on for the other segments that build up this register. Let me know in the mesa MR if you need assistance/suggestions for mapping out the registers in XML.
Are you sure about this? The register values are never cleared, meaning that only bits get added through the `|=` below but never unset - unless downstream clears these registers elsewhere before ending up in (their equivalent of) dsi_timing_setup.
As mentioned above, even without those details this constant can be represented in the XML, as belonging to offset `8` of the register.
Thanks. I forgot to mention: there seem to be a lot of similarities between the video and commandmode computations, can those possibly be factored out of the if-else to save on duplication and accidental mismatches like these?
- Marijn
On 17-02-22, 16:11, Marijn Suijten wrote:
I have made this void inline.
This function return void, so no point in checking
I have updated this comment
I have modified video mode to write and not read now. For command mode all bits are set to some value so no need to mask old values for that
Thanks, this was a good suggestion and am happy to report that I have incorporated this and indeed code looks better
On 2022-03-22 22:46:50, Vinod Koul wrote:
Perhaps there is a misunderstanding here: with inlining I am referring to the process of transplanting the _function body_ to the only call-site, not adding the `inline` keyword nor changing this to `void`.
The checks that make this function return `-EINVAL` seem valid, so the caller should check it instead of removing the return?
It isn't returning `void` in the current patch series that my email is reviewing, hence explicitly mentioning here that it may have been overlooked.
Please only convert this to `void` if you are sure that the clause that originally made `dsi_dsc_update_pic_dim()` return `-EINVAL` on invalid input is unreachable (if, for example, you moved this check to another location, say here in `dsi_timing_setup`).
Alas, it's pretty tricky to reason and pose assumptions about code that I cannot see; we should probably continue this discussion in the next patch revision depending on how it looks :)
Thank you for applying this and the other comments, glad to hear the code is shaping up and looking forward to the next revision!
- Marijn
When DSC is enabled, we need to pass the DSC parameters to panel driver as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul vkoul@kernel.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 16 +++++++++++++++- include/drm/drm_panel.h | 7 +++++++ 2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 2c14c36f0b3d..3d5773fcf496 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2159,11 +2159,25 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; struct msm_drm_private *priv; + struct drm_panel *panel; int ret;
msm_host->dev = dev; + panel = msm_dsi_host_get_panel(&msm_host->base); priv = dev->dev_private; - priv->dsc = msm_host->dsc; + + if (panel && panel->dsc) { + struct msm_display_dsc_config *dsc = priv->dsc; + + if (!dsc) { + dsc = kzalloc(sizeof(*dsc), GFP_KERNEL); + if (!dsc) + return -ENOMEM; + dsc->drm = panel->dsc; + priv->dsc = dsc; + msm_host->dsc = dsc; + } + }
ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); if (ret) { diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index 4602f833eb51..eb8ae9bf32ed 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -171,6 +171,13 @@ struct drm_panel { * Panel entry in registry. */ struct list_head list; + + /** + * @dsc: + * + * Panel DSC pps payload to be sent + */ + struct drm_dsc_config *dsc; };
void drm_panel_init(struct drm_panel *panel, struct device *dev,
On 16/11/2021 09:22, Vinod Koul wrote:
devm_kzalloc()?
Or even simpler: embed msm_display_dsc_config into struct msm_dsi_host and use it only if dsc->drm is set (IOW the panel provided DSC data)?
On 16/11/2021 09:22, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver as well, so add a dsc parameter in panel and set it when DSC is enabled
Nit: I think patch description is a bit inaccurate, since we pass DSC parameters from panel to DSI host rather than other way around.
dri-devel@lists.freedesktop.org
-
Abhinav Kumar -
Dmitry Baryshkov -
kernel test robot -
Marijn Suijten -
Vinod Koul