When loading/unloading several time the driver on r600 we end up with the GPU in broken state and loading fail to initialize acceleration. Reset the GPU at load time so acceleration keep working over load/unload.

v2 Move status print after reset in asic_reset to avoid cluttering log with this at module load time.

Signed-off-by: Jerome Glisse jglisse@redhat.com --- drivers/gpu/drm/radeon/r600.c | 37 +++++++++++++++++++++++-------------- 1 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 1537079..b932f48 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1163,13 +1163,6 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); u32 tmp;

- dev_info(rdev->dev, "GPU softreset \n"); - dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", - RREG32(R_008010_GRBM_STATUS)); - dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", - RREG32(R_008014_GRBM_STATUS2)); - dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", - RREG32(R_000E50_SRBM_STATUS)); rv515_mc_stop(rdev, &save); if (r600_mc_wait_for_idle(rdev)) { dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); @@ -1207,12 +1200,6 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) WREG32(R_008020_GRBM_SOFT_RESET, 0); /* Wait a little for things to settle down */ mdelay(1); - dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", - RREG32(R_008010_GRBM_STATUS)); - dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", - RREG32(R_008014_GRBM_STATUS2)); - dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", - RREG32(R_000E50_SRBM_STATUS)); rv515_mc_resume(rdev, &save); return 0; } @@ -1245,7 +1232,23 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)

int r600_asic_reset(struct radeon_device *rdev) { - return r600_gpu_soft_reset(rdev); + int r; + + dev_info(rdev->dev, "GPU softreset \n"); + dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", + RREG32(R_008010_GRBM_STATUS)); + dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", + RREG32(R_008014_GRBM_STATUS2)); + dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", + RREG32(R_000E50_SRBM_STATUS)); + r = r600_gpu_soft_reset(rdev); + dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", + RREG32(R_008010_GRBM_STATUS)); + dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", + RREG32(R_008014_GRBM_STATUS2)); + dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", + RREG32(R_000E50_SRBM_STATUS)); + return r; }

static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, @@ -2460,6 +2463,12 @@ int r600_init(struct radeon_device *rdev) DRM_INFO("GPU not posted. posting now...\n"); atom_asic_init(rdev->mode_info.atom_context); } + + /* GPU is sometimes in broken state (especialy after loading/unloading + * the driver several time. Reset the GPU. + */ + r600_gpu_soft_reset(rdev); + /* Initialize scratch registers */ r600_scratch_init(rdev); /* Initialize surface registers */