Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com --- include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf + #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com --- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index acb5094..04b253f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val; + uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE | - EDP_SU_TRACK_ENABLE | - EDP_FRAMES_BEFORE_SU_ENTRY; + EDP_SU_TRACK_ENABLE; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, + &sink_latency)) { + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT; + } else { + val |= EDP_FRAMES_BEFORE_SU_ENTRY; + }
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index acb5094..04b253f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val;
uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE |
EDP_SU_TRACK_ENABLE |EDP_FRAMES_BEFORE_SU_ENTRY;
EDP_SU_TRACK_ENABLE;- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
&sink_latency)) {
== 1
sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;} else {
val |= EDP_FRAMES_BEFORE_SU_ENTRY;}
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
-- 1.9.1
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Sep 20, 2017, at 7:33 AM, Nagaraju, Vathsala vathsala.nagaraju@intel.com wrote:
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index acb5094..04b253f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val;
uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE |
EDP_SU_TRACK_ENABLE |EDP_FRAMES_BEFORE_SU_ENTRY;
Please also remove the definition of this su_entry since it was not following the new standards anyway... Probably good to replace with function macro style for better use below...
EDP_SU_TRACK_ENABLE;- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
&sink_latency)) {sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
... so you could use val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency +1);
} else {
val |= EDP_FRAMES_BEFORE_SU_ENTRY;}
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
-- 1.9.1
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
v2 : - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) - add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 82f36dd..89c5249 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) (mask) << 16 | (value); }) #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
/* Engine ID */
@@ -4047,7 +4048,6 @@ enum { #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) #define EDP_PSR2_IDLE_MASK 0xf -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0a17d1f..e505fa6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val; + uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE | - EDP_SU_TRACK_ENABLE | - EDP_FRAMES_BEFORE_SU_ENTRY; + EDP_SU_TRACK_ENABLE; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, + &sink_latency) == 1) { + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; + } else { + sink_latency = 0; + } + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 82f36dd..89c5249 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) (mask) << 16 | (value); }) #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
not here
/* Engine ID */
@@ -4047,7 +4048,6 @@ enum { #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) #define EDP_PSR2_IDLE_MASK 0xf -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
move here
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0a17d1f..e505fa6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val;
uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE |
EDP_SU_TRACK_ENABLE |EDP_FRAMES_BEFORE_SU_ENTRY;
EDP_SU_TRACK_ENABLE;- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
&sink_latency) == 1) {sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
with those changes
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
} else {
sink_latency = 0;}
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
-- 1.9.1
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
Merged both patches to dinq. Thanks for the patches.
I'm anxiously waiting the PSR2 related workaroud(s)! ;)
Thanks, Rodrigo.
drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 82f36dd..89c5249 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) (mask) << 16 | (value); }) #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
/* Engine ID */
@@ -4047,7 +4048,6 @@ enum { #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) #define EDP_PSR2_IDLE_MASK 0xf -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0a17d1f..e505fa6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val;
uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE |
EDP_SU_TRACK_ENABLE |EDP_FRAMES_BEFORE_SU_ENTRY;
EDP_SU_TRACK_ENABLE;if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
&sink_latency) == 1) {sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;} else {
sink_latency = 0;}
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
-- 1.9.1
On Thu, 28 Sep 2017, Rodrigo Vivi rodrigo.vivi@intel.com wrote:
Merged both patches to dinq. Thanks for the patches.
While patch 1 was a simple addition of a few DP macros, we need to get ack from Dave or (preferrably non-Intel) drm-misc maintainers before queuing non-i915 patches through drm-intel.
Dave, Sean, ack after the fact...?
The patch is [1].
BR, Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/1506419953-32605-1-git-send-ema...
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
where did you get that? eDP 1.4 teels 2009h is a debug register.
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Maybe the patch should then make this clear, by annotating it with /* eDP 1.4b */ That's missing, which isn't all that great really, since it makes specs hunts like yours necessary.
Please fix up before applying. -Daniel
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter daniel@ffwll.ch wrote:
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Maybe the patch should then make this clear, by annotating it with /* eDP 1.4b */ That's missing, which isn't all that great really, since it makes specs hunts like yours necessary.
It's actually in eDP 1.4 spec, table 5-6 page 86
Please fix up before applying. -Daniel
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
-- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat < puthik@chromium.org> wrote:
On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter daniel@ffwll.ch wrote:
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Maybe the patch should then make this clear, by annotating it with /* eDP 1.4b */ That's missing, which isn't all that great really, since it makes specs hunts like yours necessary.
It's actually in eDP 1.4 spec, table 5-6 page 86
Copy and paste the wrong one. 0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR Status Field page 124
Please fix up before applying. -Daniel
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
-- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
On Tue, Sep 26, 2017 at 1:37 PM, Puthikorn Voravootivat puthik@chromium.org wrote:
On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat puthik@chromium.org wrote:
On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter daniel@ffwll.ch wrote:
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
Add defines for dpcd register 2009 (synchronization latency in sink).
Cc: Rodrigo Vivi rodrigo.vivi@intel.com CC: Puthikorn Voravootivat puthik@chromium.org Signed-off-by: Vathsala Nagaraju vathsala.nagaraju@intel.com
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Maybe the patch should then make this clear, by annotating it with /* eDP 1.4b */ That's missing, which isn't all that great really, since it makes specs hunts like yours necessary.
It's actually in eDP 1.4 spec, table 5-6 page 86
Copy and paste the wrong one. 0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR Status Field page 124
you are absolutely right! eDP 1.4 has it. even the eDP 1.4a had... I definitely had a strange version here... All updated locally here.
For the patch I will update when merging. No need to send a newer version. I intend to merge patches tomorrow if no one has any other comment or concern on those.
Please fix up before applying. -Daniel
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 11c39f1..846004e6 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -735,6 +735,9 @@ # define DP_PSR_SINK_INTERNAL_ERROR 7 # define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009 +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
-- 1.9.1
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-- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
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Daniel Vetter -
Jani Nikula -
Puthikorn Voravootivat -
Rodrigo Vivi -
Rodrigo Vivi -
vathsala nagaraju -
Ville Syrjälä -
Vivi, Rodrigo