HDMI 2.0 spec defines a method to reduce the RF footprint while operating at higher pixel clocks, which is called Scrambling. Scrambling can be controlled over a new set of I2C registers which are accessible over existing DDC I2C lines, called SCDC register set.
This patch series contains 6 patches: - First two patches add generic drm helper functions to read and write into SCDC registers. These patches are written by Thierry, in a patch series published here: https://patchwork.kernel.org/patch/9459051/ Minor changes were done to map the patches into this series.
- Next two patches add functions for scrambling detection and scrambling control.
- Next two patches use this infrastructure in DRM layer from I915 driver, to enable scrambling on a GLK deivce which sports a native HDMI 2.0 controller.
V2: - addressed review comments from Thierry, Ville and Dhinakaran - added signed-off-by:self in first two patches(Jani N)
V3: - addressed review comments from Jose and Jani
V4: - addressed review comments from Maarten on patch 5, rebase all other patches
V5: - addressed review comments from Ville/Ander on patch 1, 4, 5 rebase all other patches
Shashank Sharma (4): drm/edid: detect SCDC support in HF-VSDB drm/edid: detect SCDC support in HF-VSDB drm/i915: enable scrambling drm/i915: allow HDMI 2.0 clock rates
Thierry Reding (2): drm: Add SCDC helpers drm/edid: check for HF-VSDB block
Documentation/gpu/drm-kms-helpers.rst | 12 ++ drivers/gpu/drm/Makefile | 3 +- drivers/gpu/drm/drm_edid.c | 60 +++++++++ drivers/gpu/drm/drm_scdc_helper.c | 234 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_ddi.c | 29 +++++ drivers/gpu/drm/i915/intel_drv.h | 14 ++ drivers/gpu/drm/i915/intel_hdmi.c | 100 +++++++++++++++ include/drm/drm_connector.h | 52 ++++++++ include/drm/drm_edid.h | 6 +- include/drm/drm_scdc_helper.h | 159 +++++++++++++++++++++++ include/linux/hdmi.h | 1 + 12 files changed, 672 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/drm_scdc_helper.c create mode 100644 include/drm/drm_scdc_helper.h
From: Thierry Reding treding@nvidia.com
SCDC is a mechanism defined in the HDMI 2.0 specification that allows the source and sink devices to communicate.
This commit introduces helpers to access the SCDC and provides the symbolic names for the various registers defined in the specification.
V2: Rebase. V3: Added R-B from Jose. V4: Rebase V5: Addressed review comments from Ville - Handle the I2c return values in a better way (dp_dual_mode) - Make the macros for SCDC Major/Minor more readable, by adding a 'GET' in the macro names
Signed-off-by: Thierry Reding treding@nvidia.com Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Jose Abreu joabreu@synopsys.com --- Documentation/gpu/drm-kms-helpers.rst | 12 ++++ drivers/gpu/drm/Makefile | 3 +- drivers/gpu/drm/drm_scdc_helper.c | 123 +++++++++++++++++++++++++++++++ include/drm/drm_scdc_helper.h | 132 ++++++++++++++++++++++++++++++++++ 4 files changed, 269 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/drm_scdc_helper.c create mode 100644 include/drm/drm_scdc_helper.h
diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index 03040aa..7592756 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -217,6 +217,18 @@ EDID Helper Functions Reference .. kernel-doc:: drivers/gpu/drm/drm_edid.c :export:
+SCDC Helper Functions Reference +=============================== + +.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c + :doc: scdc helpers + +.. kernel-doc:: include/drm/drm_scdc_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c + :export: + Rectangle Utilities Reference =============================
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 3ee9579..da5b08c 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -31,7 +31,8 @@ drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ drm_kms_helper_common.o drm_dp_dual_mode_helper.o \ - drm_simple_kms_helper.o drm_modeset_helper.o + drm_simple_kms_helper.o drm_modeset_helper.o \ + drm_scdc_helper.o
drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c new file mode 100644 index 0000000..c2dd33f --- /dev/null +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2015 NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include <linux/slab.h> + +#include <drm/drm_scdc_helper.h> + +/** + * DOC: scdc helpers + * + * Status and Control Data Channel (SCDC) is a mechanism introduced by the + * HDMI 2.0 specification. It is a point-to-point protocol that allows the + * HDMI source and HDMI sink to exchange data. The same I2C interface that + * is used to access EDID serves as the transport mechanism for SCDC. + */ + +#define SCDC_I2C_SLAVE_ADDRESS 0x54 + +/** + * drm_scdc_read - read a block of data from SCDC + * @adapter: I2C controller + * @offset: start offset of block to read + * @buffer: return location for the block to read + * @size: size of the block to read + * + * Reads a block of data from SCDC, starting at a given offset. + * + * Returns: + * 0 on success, negative error code on failure. + */ +ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer, + size_t size) +{ + int ret; + struct i2c_msg msgs[2] = { + { + .addr = SCDC_I2C_SLAVE_ADDRESS, + .flags = 0, + .len = 1, + .buf = &offset, + }, { + .addr = SCDC_I2C_SLAVE_ADDRESS, + .flags = I2C_M_RD, + .len = size, + .buf = buffer, + } + }; + + ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) + return ret; + if (ret != ARRAY_SIZE(msgs)) + return -EPROTO; + + return 0; +} +EXPORT_SYMBOL(drm_scdc_read); + +/** + * drm_scdc_write - write a block of data to SCDC + * @adapter: I2C controller + * @offset: start offset of block to write + * @buffer: block of data to write + * @size: size of the block to write + * + * Writes a block of data to SCDC, starting at a given offset. + * + * Returns: + * 0 on success, negative error code on failure. + */ +ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, + const void *buffer, size_t size) +{ + struct i2c_msg msg = { + .addr = SCDC_I2C_SLAVE_ADDRESS, + .flags = 0, + .len = 1 + size, + .buf = NULL, + }; + void *data; + int err; + + data = kmalloc(1 + size, GFP_TEMPORARY); + if (!data) + return -ENOMEM; + + msg.buf = data; + + memcpy(data, &offset, sizeof(offset)); + memcpy(data + 1, buffer, size); + + err = i2c_transfer(adapter, &msg, 1); + + kfree(data); + + if (err < 0) + return err; + if (err != 1) + return -EPROTO; + + return 0; +} +EXPORT_SYMBOL(drm_scdc_write); diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h new file mode 100644 index 0000000..9c52deb --- /dev/null +++ b/include/drm/drm_scdc_helper.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015 NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DRM_SCDC_HELPER_H +#define DRM_SCDC_HELPER_H + +#include <linux/i2c.h> +#include <linux/types.h> + +#define SCDC_SINK_VERSION 0x01 + +#define SCDC_SOURCE_VERSION 0x02 + +#define SCDC_UPDATE_0 0x10 +#define SCDC_READ_REQUEST_TEST (1 << 2) +#define SCDC_CED_UPDATE (1 << 1) +#define SCDC_STATUS_UPDATE (1 << 0) + +#define SCDC_UPDATE_1 0x11 + +#define SCDC_TMDS_CONFIG 0x20 +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1) +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1) +#define SCDC_SCRAMBLING_ENABLE (1 << 0) + +#define SCDC_SCRAMBLER_STATUS 0x21 +#define SCDC_SCRAMBLING_STATUS (1 << 0) + +#define SCDC_CONFIG_0 0x30 +#define SCDC_READ_REQUEST_ENABLE (1 << 0) + +#define SCDC_STATUS_FLAGS_0 0x40 +#define SCDC_CH2_LOCK (1 < 3) +#define SCDC_CH1_LOCK (1 < 2) +#define SCDC_CH0_LOCK (1 < 1) +#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK) +#define SCDC_CLOCK_DETECT (1 << 0) + +#define SCDC_STATUS_FLAGS_1 0x41 + +#define SCDC_ERR_DET_0_L 0x50 +#define SCDC_ERR_DET_0_H 0x51 +#define SCDC_ERR_DET_1_L 0x52 +#define SCDC_ERR_DET_1_H 0x53 +#define SCDC_ERR_DET_2_L 0x54 +#define SCDC_ERR_DET_2_H 0x55 +#define SCDC_CHANNEL_VALID (1 << 7) + +#define SCDC_ERR_DET_CHECKSUM 0x56 + +#define SCDC_TEST_CONFIG_0 0xc0 +#define SCDC_TEST_READ_REQUEST (1 << 7) +#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f) + +#define SCDC_MANUFACTURER_IEEE_OUI 0xd0 +#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3 + +#define SCDC_DEVICE_ID 0xd3 +#define SCDC_DEVICE_ID_SIZE 8 + +#define SCDC_DEVICE_HARDWARE_REVISION 0xdb +#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf) +#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf) + +#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc +#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd + +#define SCDC_MANUFACTURER_SPECIFIC 0xde +#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34 + +ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer, + size_t size); +ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, + const void *buffer, size_t size); + +/** + * drm_scdc_readb - read a single byte from SCDC + * @adapter: I2C adapter + * @offset: offset of register to read + * @value: return location for the register value + * + * Reads a single byte from SCDC. This is a convenience wrapper around the + * drm_scdc_read() function. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset, + u8 *value) +{ + return drm_scdc_read(adapter, offset, value, sizeof(*value)); +} + +/** + * drm_scdc_writeb - write a single byte to SCDC + * @adapter: I2C adapter + * @offset: offset of register to read + * @value: return location for the register value + * + * Writes a single byte to SCDC. This is a convenience wrapper around the + * drm_scdc_write() function. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, + u8 value) +{ + return drm_scdc_write(adapter, offset, &value, sizeof(value)); +} + +#endif
From: Thierry Reding treding@nvidia.com
This patch implements a small function that finds if a given CEA db is hdmi-forum vendor specific data block or not.
V2: Rebase. V3: Added R-B from Jose. V4: Rebase V5: Rebase
Signed-off-by: Thierry Reding treding@nvidia.com Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Jose Abreu joabreu@synopsys.com --- drivers/gpu/drm/drm_edid.c | 15 +++++++++++++++ include/linux/hdmi.h | 1 + 2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index e1743ab..055b511 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3248,6 +3248,21 @@ static bool cea_db_is_hdmi_vsdb(const u8 *db) return hdmi_id == HDMI_IEEE_OUI; }
+static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) +{ + unsigned int oui; + + if (cea_db_tag(db) != VENDOR_BLOCK) + return false; + + if (cea_db_payload_len(db) < 7) + return false; + + oui = db[3] << 16 | db[2] << 8 | db[1]; + + return oui == HDMI_FORUM_IEEE_OUI; +} + #define for_each_cea_db(cea, i, start, end) \ for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index edbb4fc..d271ff2 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -35,6 +35,7 @@ enum hdmi_infoframe_type { };
#define HDMI_IEEE_OUI 0x000c03 +#define HDMI_FORUM_IEEE_OUI 0xc45dd8 #define HDMI_INFOFRAME_HEADER_SIZE 4 #define HDMI_AVI_INFOFRAME_SIZE 13 #define HDMI_SPD_INFOFRAME_SIZE 25
This patch does following: - Adds a new structure (drm_hdmi_info) in drm_display_info. This structure will be used to save and indicate if sink supports advanced HDMI 2.0 features - Adds another structure drm_scdc within drm_hdmi_info, to reflect scdc support and capabilities in connected HDMI 2.0 sink. - Checks the HF-VSDB block for presence of SCDC, and marks it in scdc structure - If SCDC is present, checks if sink is capable of generating SCDC read request, and marks it in scdc structure.
V2: Addressed review comments Thierry: - Fix typos in commit message and make abbreviation consistent across the commit message. - Change structure object name from hdmi_info -> hdmi - Fix typos and abbreviations in description of structure drm_hdmi_info end the description with a full stop. - Create a structure drm_scdc, and keep all information related to SCDC register set (supported, read request supported) etc in it.
Ville: - Change rr -> read_request - Call drm_detect_scrambling function drm_parse_hf_vsdb so that all of HF-VSDB parsing can be kept in same function, in incremental patches.
V3: Rebase. V4: Rebase. V5: Rebase.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Thierry Reding treding@nvidia.com --- drivers/gpu/drm/drm_edid.c | 14 ++++++++++++++ include/drm/drm_connector.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 055b511..0881108 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3814,6 +3814,18 @@ enum hdmi_quantization_range } EXPORT_SYMBOL(drm_default_rgb_quant_range);
+static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, + const u8 *hf_vsdb) +{ + struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; + + if (hf_vsdb[6] & 0x80) { + hdmi->scdc.supported = true; + if (hf_vsdb[6] & 0x40) + hdmi->scdc.read_request = true; + } +} + static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, const u8 *hdmi) { @@ -3928,6 +3940,8 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
if (cea_db_is_hdmi_vsdb(db)) drm_parse_hdmi_vsdb_video(connector, db); + if (cea_db_is_hdmi_forum_vsdb(db)) + drm_parse_hdmi_forum_vsdb(connector, db); } }
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index e5e1edd..6d5304e 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -87,6 +87,34 @@ enum subpixel_order { SubPixelVerticalRGB, SubPixelVerticalBGR, SubPixelNone, + +}; + +/* + * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink + * + * Provides SCDC register support and capabilities related information on a + * HDMI 2.0 sink. In case of a HDMI 1.4 sink, all parameter must be 0. + */ +struct drm_scdc { + /** + * @supported: status control & data channel present. + */ + bool supported; + /** + * @read_request: sink is capable of generating scdc read request. + */ + bool read_request; +}; + +/** + * struct drm_hdmi_info - runtime information about the connected HDMI sink + * + * Describes if a given display supports advanced HDMI 2.0 features. + * This information is available in CEA-861-F extension blocks (like HF-VSDB). + */ +struct drm_hdmi_info { + struct drm_scdc scdc; };
/** @@ -188,6 +216,11 @@ struct drm_display_info { * @cea_rev: CEA revision of the HDMI sink. */ u8 cea_rev; + + /** + * @hdmi: advance features of a HDMI sink. + */ + struct drm_hdmi_info hdmi; };
int drm_display_info_set_bus_formats(struct drm_display_info *info,
This patch does following: - Adds a new structure (drm_hdmi_info) in drm_display_info. This structure will be used to save and indicate if sink supports advanced HDMI 2.0 features - Adds another structure drm_scdc within drm_hdmi_info, to reflect scdc support and capabilities in connected HDMI 2.0 sink. - Checks the HF-VSDB block for presence of SCDC, and marks it in scdc structure - If SCDC is present, checks if sink is capable of generating SCDC read request, and marks it in scdc structure.
V2: Addressed review comments Thierry: - Fix typos in commit message and make abbreviation consistent across the commit message. - Change structure object name from hdmi_info -> hdmi - Fix typos and abbreviations in description of structure drm_hdmi_info end the description with a full stop. - Create a structure drm_scdc, and keep all information related to SCDC register set (supported, read request supported) etc in it.
Ville: - Change rr -> read_request - Call drm_detect_scrambling function drm_parse_hf_vsdb so that all of HF-VSDB parsing can be kept in same function, in incremental patches.
V3: Rebase. V4: Rebase. V5: Rebase.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Thierry Reding treding@nvidia.com --- drivers/gpu/drm/drm_edid.c | 33 +++++++++++- drivers/gpu/drm/drm_scdc_helper.c | 111 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 19 +++++++ include/drm/drm_edid.h | 6 ++- include/drm/drm_scdc_helper.h | 27 ++++++++++ 5 files changed, 194 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 0881108..e84c5ab 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -37,6 +37,7 @@ #include <drm/drm_edid.h> #include <drm/drm_encoder.h> #include <drm/drm_displayid.h> +#include <drm/drm_scdc_helper.h>
#include "drm_crtc_internal.h"
@@ -3817,13 +3818,43 @@ enum hdmi_quantization_range static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, const u8 *hf_vsdb) { - struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; + struct drm_display_info *display = &connector->display_info; + struct drm_hdmi_info *hdmi = &display->hdmi;
if (hf_vsdb[6] & 0x80) { hdmi->scdc.supported = true; if (hf_vsdb[6] & 0x40) hdmi->scdc.read_request = true; } + + /* + * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. + * And as per the spec, three factors confirm this: + * * Availability of a HF-VSDB block in EDID (check) + * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) + * * SCDC support available (let's check) + * Lets check it out. + */ + + if (hf_vsdb[5]) { + /* max clock is 5000 KHz times block value */ + u32 max_tmds_clock = hf_vsdb[5] * 5000; + struct drm_scdc *scdc = &hdmi->scdc; + + if (max_tmds_clock > 340000) { + display->max_tmds_clock = max_tmds_clock; + DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", + display->max_tmds_clock); + } + + if (scdc->supported) { + scdc->scrambling.supported = true; + + /* Few sinks support scrambling for cloks < 340M */ + if ((hf_vsdb[6] & 0x8)) + scdc->scrambling.low_rates = true; + } + } }
static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index c2dd33f..180a7cd 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -22,8 +22,10 @@ */
#include <linux/slab.h> +#include <linux/delay.h>
#include <drm/drm_scdc_helper.h> +#include <drm/drmP.h>
/** * DOC: scdc helpers @@ -121,3 +123,112 @@ ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, return 0; } EXPORT_SYMBOL(drm_scdc_write); + +/** + * drm_scdc_check_scrambling_status - what is status of scrambling? + * @adapter: I2C adapter for DDC channel + * + * Reads the scrambler status over SCDC, and checks the + * scrambling status. + * + * Returns: + * True if the scrambling is enabled, false otherwise. + */ + +bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter) +{ + u8 status; + int ret; + + ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status); + if (ret < 0) { + DRM_ERROR("Failed to read scrambling status, error %d\n", ret); + return false; + } + + return status & SCDC_SCRAMBLING_STATUS; +} +EXPORT_SYMBOL(drm_scdc_get_scrambling_status); + +/** + * drm_scdc_set_scrambling - enable scrambling + * @adapter: I2C adapter for DDC channel + * @enable: bool to indicate if scrambling is to be enabled/disabled + * + * Writes the TMDS config register over SCDC channel, and: + * enables scrambling when enable = 1 + * disables scrambling when enable = 0 + * + * Returns: + * True if scrambling is set/reset successfully, false otherwise. + */ + +bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable) +{ + u8 config; + int ret; + + ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); + if (ret < 0) { + DRM_ERROR("Failed to read tmds config, err=%d\n", ret); + return false; + } + + if (enable) + config |= SCDC_SCRAMBLING_ENABLE; + else + config &= ~SCDC_SCRAMBLING_ENABLE; + + ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); + if (ret < 0) { + DRM_ERROR("Failed to enable scrambling, error %d\n", ret); + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_scdc_set_scrambling); + +/** + * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio + * @adapter: I2C adapter for DDC channel + * @set: ret or reset the high clock ratio + * + * Writes to the TMDS config register over SCDC channel, and: + * sets TMDS clock ratio to 1/40 when set = 1 + * sets TMDS clock ratio to 1/10 when set = 0 + * + * Returns: + * True if write is successful, false otherwise. + */ +bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set) +{ + u8 config; + int ret; + + ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); + if (ret < 0) { + DRM_ERROR("Failed to read tmds config, err=%d\n", ret); + return false; + } + + if (set) + config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; + else + config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; + + ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); + if (ret < 0) { + DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret); + return false; + } + + /* + * The spec says that a source should wait minimum 1ms and maximum + * 100ms after writing the TMDS config for clock ratio. Lets allow a + * wait of upto 2ms here. + */ + usleep_range(1000, 2000); + return true; +} +EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 6d5304e..78618308 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -90,6 +90,20 @@ enum subpixel_order {
};
+/** + * struct drm_scrambling: sink's scrambling support. + */ +struct drm_scrambling { + /** + * @supported: scrambling supported for rates > 340 Mhz. + */ + bool supported; + /** + * @low_rates: scrambling supported for rates <= 340 Mhz. + */ + bool low_rates; +}; + /* * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink * @@ -105,8 +119,13 @@ struct drm_scdc { * @read_request: sink is capable of generating scdc read request. */ bool read_request; + /** + * @scrambling: sink's scrambling capabilities + */ + struct drm_scrambling scrambling; };
+ /** * struct drm_hdmi_info - runtime information about the connected HDMI sink * diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 3ead84d..f4a91e0 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -476,5 +476,9 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb); - +bool drm_enable_scrambling(struct drm_connector *connector, + struct i2c_adapter *adapter, bool force); +bool drm_disable_scrambling(struct drm_connector *connector, + struct i2c_adapter *adapter, bool force); +bool drm_check_scrambling_status(struct i2c_adapter *adapter); #endif /* __DRM_EDID_H__ */ diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h index 9c52deb..ab6bcfb 100644 --- a/include/drm/drm_scdc_helper.h +++ b/include/drm/drm_scdc_helper.h @@ -129,4 +129,31 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, return drm_scdc_write(adapter, offset, &value, sizeof(value)); }
+/** + * drm_scdc_set_scrambling - enable scrambling + * @adapter: I2C adapter for DDC channel + * @enable: bool to indicate if scrambling is to be enabled/disabled + * + * Writes the TMDS config register over SCDC channel, and: + * enables scrambling when enable = 1 + * disables scrambling when enable = 0 + * + * Returns: + * True if scrambling is set/reset successfully, false otherwise. + */ +bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable); + +/** + * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio + * @adapter: I2C adapter for DDC channel + * @set: ret or reset the high clock ratio + * + * Writes to the TMDS config register over SCDC channel, and: + * sets TMDS clock ratio to 1/40 when set = 1 + * sets TMDS clock ratio to 1/10 when set = 0 + * + * Returns: + * True if write is successful, false otherwise. + */ +bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set); #endif
On Tue, Feb 28, 2017 at 02:09:08PM +0530, Shashank Sharma wrote:
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info. This structure will be used to save and indicate if sink supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it in scdc structure
- If SCDC is present, checks if sink is capable of generating SCDC read request, and marks it in scdc structure.
V2: Addressed review comments Thierry:
- Fix typos in commit message and make abbreviation consistent across the commit message.
- Change structure object name from hdmi_info -> hdmi
- Fix typos and abbreviations in description of structure drm_hdmi_info end the description with a full stop.
- Create a structure drm_scdc, and keep all information related to SCDC register set (supported, read request supported) etc in it.
Ville:
- Change rr -> read_request
- Call drm_detect_scrambling function drm_parse_hf_vsdb so that all of HF-VSDB parsing can be kept in same function, in incremental patches.
V3: Rebase. V4: Rebase. V5: Rebase.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Thierry Reding treding@nvidia.com
drivers/gpu/drm/drm_edid.c | 33 +++++++++++- drivers/gpu/drm/drm_scdc_helper.c | 111 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 19 +++++++ include/drm/drm_edid.h | 6 ++- include/drm/drm_scdc_helper.h | 27 ++++++++++ 5 files changed, 194 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 0881108..e84c5ab 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -37,6 +37,7 @@ #include <drm/drm_edid.h> #include <drm/drm_encoder.h> #include <drm/drm_displayid.h> +#include <drm/drm_scdc_helper.h>
#include "drm_crtc_internal.h"
@@ -3817,13 +3818,43 @@ enum hdmi_quantization_range static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, const u8 *hf_vsdb) {
- struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
struct drm_display_info *display = &connector->display_info;
struct drm_hdmi_info *hdmi = &display->hdmi;
if (hf_vsdb[6] & 0x80) { hdmi->scdc.supported = true; if (hf_vsdb[6] & 0x40) hdmi->scdc.read_request = true; }
/*
* All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.* And as per the spec, three factors confirm this:* * Availability of a HF-VSDB block in EDID (check)* * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)* * SCDC support available (let's check)* Lets check it out.*/if (hf_vsdb[5]) {
/* max clock is 5000 KHz times block value */u32 max_tmds_clock = hf_vsdb[5] * 5000;struct drm_scdc *scdc = &hdmi->scdc;if (max_tmds_clock > 340000) {display->max_tmds_clock = max_tmds_clock;DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",display->max_tmds_clock);}if (scdc->supported) {scdc->scrambling.supported = true;/* Few sinks support scrambling for cloks < 340M */if ((hf_vsdb[6] & 0x8))scdc->scrambling.low_rates = true;}}
}
static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index c2dd33f..180a7cd 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -22,8 +22,10 @@ */
#include <linux/slab.h> +#include <linux/delay.h>
#include <drm/drm_scdc_helper.h> +#include <drm/drmP.h>
/**
- DOC: scdc helpers
@@ -121,3 +123,112 @@ ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, return 0; } EXPORT_SYMBOL(drm_scdc_write);
+/**
- drm_scdc_check_scrambling_status - what is status of scrambling?
- @adapter: I2C adapter for DDC channel
- Reads the scrambler status over SCDC, and checks the
- scrambling status.
- Returns:
- True if the scrambling is enabled, false otherwise.
- */
+bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter) +{
- u8 status;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
- if (ret < 0) {
DRM_ERROR("Failed to read scrambling status, error %d\n", ret);return false;- }
- return status & SCDC_SCRAMBLING_STATUS;
+} +EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
+/**
- drm_scdc_set_scrambling - enable scrambling
- @adapter: I2C adapter for DDC channel
- @enable: bool to indicate if scrambling is to be enabled/disabled
- Writes the TMDS config register over SCDC channel, and:
- enables scrambling when enable = 1
- disables scrambling when enable = 0
- Returns:
- True if scrambling is set/reset successfully, false otherwise.
- */
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable) +{
- u8 config;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
DRM_ERROR("Failed to read tmds config, err=%d\n", ret);return false;- }
- if (enable)
config |= SCDC_SCRAMBLING_ENABLE;- else
config &= ~SCDC_SCRAMBLING_ENABLE;- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
DRM_ERROR("Failed to enable scrambling, error %d\n", ret);return false;- }
- return true;
+} +EXPORT_SYMBOL(drm_scdc_set_scrambling);
+/**
- drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
- @adapter: I2C adapter for DDC channel
- @set: ret or reset the high clock ratio
- Writes to the TMDS config register over SCDC channel, and:
- sets TMDS clock ratio to 1/40 when set = 1
- sets TMDS clock ratio to 1/10 when set = 0
The 1/10 and 1/40 ratios confuse me a little since we never really deal with the bitrate in the driver. Instead we always deal with either pixel clock, character clock or TMDS clock (well prior to this TMDS clock == character clock). So the factor 10 never enters the picture elsewhere. So I would prefer to specify these in those terms as well.
An enum for the ratios might also help in making this a bit less cryptic.
- Returns:
- True if write is successful, false otherwise.
- */
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set) +{
- u8 config;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
DRM_ERROR("Failed to read tmds config, err=%d\n", ret);return false;- }
- if (set)
config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;- else
config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);return false;- }
- /*
* The spec says that a source should wait minimum 1ms and maximum* 100ms after writing the TMDS config for clock ratio. Lets allow a* wait of upto 2ms here.*/- usleep_range(1000, 2000);
- return true;
+} +EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 6d5304e..78618308 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -90,6 +90,20 @@ enum subpixel_order {
};
+/**
- struct drm_scrambling: sink's scrambling support.
- */
+struct drm_scrambling {
- /**
* @supported: scrambling supported for rates > 340 Mhz.*/- bool supported;
- /**
* @low_rates: scrambling supported for rates <= 340 Mhz.*/- bool low_rates;
+};
/*
- struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink
@@ -105,8 +119,13 @@ struct drm_scdc { * @read_request: sink is capable of generating scdc read request. */ bool read_request;
- /**
* @scrambling: sink's scrambling capabilities*/- struct drm_scrambling scrambling;
};
/**
- struct drm_hdmi_info - runtime information about the connected HDMI sink
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 3ead84d..f4a91e0 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -476,5 +476,9 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb);
+bool drm_enable_scrambling(struct drm_connector *connector,
struct i2c_adapter *adapter, bool force);+bool drm_disable_scrambling(struct drm_connector *connector,
struct i2c_adapter *adapter, bool force);+bool drm_check_scrambling_status(struct i2c_adapter *adapter);
Old leftovers?
#endif /* __DRM_EDID_H__ */ diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h index 9c52deb..ab6bcfb 100644 --- a/include/drm/drm_scdc_helper.h +++ b/include/drm/drm_scdc_helper.h @@ -129,4 +129,31 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, return drm_scdc_write(adapter, offset, &value, sizeof(value)); }
+/**
- drm_scdc_set_scrambling - enable scrambling
- @adapter: I2C adapter for DDC channel
- @enable: bool to indicate if scrambling is to be enabled/disabled
- Writes the TMDS config register over SCDC channel, and:
- enables scrambling when enable = 1
- disables scrambling when enable = 0
- Returns:
- True if scrambling is set/reset successfully, false otherwise.
- */
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
+/**
- drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
- @adapter: I2C adapter for DDC channel
- @set: ret or reset the high clock ratio
- Writes to the TMDS config register over SCDC channel, and:
- sets TMDS clock ratio to 1/40 when set = 1
- sets TMDS clock ratio to 1/10 when set = 0
- Returns:
- True if write is successful, false otherwise.
- */
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
#endif
1.9.1
Regards
Shashank
On 3/1/2017 8:28 PM, Ville Syrjälä wrote:
On Tue, Feb 28, 2017 at 02:09:08PM +0530, Shashank Sharma wrote:
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info. This structure will be used to save and indicate if sink supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it in scdc structure
- If SCDC is present, checks if sink is capable of generating SCDC read request, and marks it in scdc structure.
V2: Addressed review comments Thierry:
- Fix typos in commit message and make abbreviation consistent across the commit message.
- Change structure object name from hdmi_info -> hdmi
- Fix typos and abbreviations in description of structure drm_hdmi_info end the description with a full stop.
- Create a structure drm_scdc, and keep all information related to SCDC register set (supported, read request supported) etc in it.
Ville:
- Change rr -> read_request
- Call drm_detect_scrambling function drm_parse_hf_vsdb so that all of HF-VSDB parsing can be kept in same function, in incremental patches.
V3: Rebase. V4: Rebase. V5: Rebase.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Thierry Reding treding@nvidia.com
drivers/gpu/drm/drm_edid.c | 33 +++++++++++- drivers/gpu/drm/drm_scdc_helper.c | 111 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 19 +++++++ include/drm/drm_edid.h | 6 ++- include/drm/drm_scdc_helper.h | 27 ++++++++++ 5 files changed, 194 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 0881108..e84c5ab 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -37,6 +37,7 @@ #include <drm/drm_edid.h> #include <drm/drm_encoder.h> #include <drm/drm_displayid.h> +#include <drm/drm_scdc_helper.h>
#include "drm_crtc_internal.h"
@@ -3817,13 +3818,43 @@ enum hdmi_quantization_range static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, const u8 *hf_vsdb) {
- struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
struct drm_display_info *display = &connector->display_info;
struct drm_hdmi_info *hdmi = &display->hdmi;
if (hf_vsdb[6] & 0x80) { hdmi->scdc.supported = true; if (hf_vsdb[6] & 0x40) hdmi->scdc.read_request = true; }
/*
* All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.* And as per the spec, three factors confirm this:* * Availability of a HF-VSDB block in EDID (check)* * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)* * SCDC support available (let's check)* Lets check it out.*/if (hf_vsdb[5]) {
/* max clock is 5000 KHz times block value */u32 max_tmds_clock = hf_vsdb[5] * 5000;struct drm_scdc *scdc = &hdmi->scdc;if (max_tmds_clock > 340000) {display->max_tmds_clock = max_tmds_clock;DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",display->max_tmds_clock);}if (scdc->supported) {scdc->scrambling.supported = true;/* Few sinks support scrambling for cloks < 340M */if ((hf_vsdb[6] & 0x8))scdc->scrambling.low_rates = true;}} }
static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index c2dd33f..180a7cd 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -22,8 +22,10 @@ */
#include <linux/slab.h> +#include <linux/delay.h>
#include <drm/drm_scdc_helper.h> +#include <drm/drmP.h>
/**
- DOC: scdc helpers
@@ -121,3 +123,112 @@ ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, return 0; } EXPORT_SYMBOL(drm_scdc_write);
+/**
- drm_scdc_check_scrambling_status - what is status of scrambling?
- @adapter: I2C adapter for DDC channel
- Reads the scrambler status over SCDC, and checks the
- scrambling status.
- Returns:
- True if the scrambling is enabled, false otherwise.
- */
+bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter) +{
- u8 status;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
- if (ret < 0) {
DRM_ERROR("Failed to read scrambling status, error %d\n", ret);return false;- }
- return status & SCDC_SCRAMBLING_STATUS;
+} +EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
+/**
- drm_scdc_set_scrambling - enable scrambling
- @adapter: I2C adapter for DDC channel
- @enable: bool to indicate if scrambling is to be enabled/disabled
- Writes the TMDS config register over SCDC channel, and:
- enables scrambling when enable = 1
- disables scrambling when enable = 0
- Returns:
- True if scrambling is set/reset successfully, false otherwise.
- */
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable) +{
- u8 config;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
DRM_ERROR("Failed to read tmds config, err=%d\n", ret);return false;- }
- if (enable)
config |= SCDC_SCRAMBLING_ENABLE;- else
config &= ~SCDC_SCRAMBLING_ENABLE;- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
DRM_ERROR("Failed to enable scrambling, error %d\n", ret);return false;- }
- return true;
+} +EXPORT_SYMBOL(drm_scdc_set_scrambling);
+/**
- drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
- @adapter: I2C adapter for DDC channel
- @set: ret or reset the high clock ratio
- Writes to the TMDS config register over SCDC channel, and:
- sets TMDS clock ratio to 1/40 when set = 1
- sets TMDS clock ratio to 1/10 when set = 0
The 1/10 and 1/40 ratios confuse me a little since we never really deal with the bitrate in the driver. Instead we always deal with either pixel clock, character clock or TMDS clock (well prior to this TMDS clock == character clock). So the factor 10 never enters the picture elsewhere. So I would prefer to specify these in those terms as well.
Ok, I will add comments for pixel clock as well
An enum for the ratios might also help in making this a bit less cryptic.
Humm, not sure how helpful will be an enum, as thats only used in case of pixelclock>340 asso, only two entries 1/40 and 1/10, but let me see if I can do that.
- Returns:
- True if write is successful, false otherwise.
- */
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set) +{
- u8 config;
- int ret;
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
DRM_ERROR("Failed to read tmds config, err=%d\n", ret);return false;- }
- if (set)
config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;- else
config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);return false;- }
- /*
* The spec says that a source should wait minimum 1ms and maximum* 100ms after writing the TMDS config for clock ratio. Lets allow a* wait of upto 2ms here.*/- usleep_range(1000, 2000);
- return true;
+} +EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio); diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 6d5304e..78618308 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -90,6 +90,20 @@ enum subpixel_order {
};
+/**
- struct drm_scrambling: sink's scrambling support.
- */
+struct drm_scrambling {
- /**
* @supported: scrambling supported for rates > 340 Mhz.*/- bool supported;
- /**
* @low_rates: scrambling supported for rates <= 340 Mhz.*/- bool low_rates;
+};
- /*
- struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink
@@ -105,8 +119,13 @@ struct drm_scdc { * @read_request: sink is capable of generating scdc read request. */ bool read_request;
/**
* @scrambling: sink's scrambling capabilities*/struct drm_scrambling scrambling; };
/**
- struct drm_hdmi_info - runtime information about the connected HDMI sink
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 3ead84d..f4a91e0 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -476,5 +476,9 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb);
+bool drm_enable_scrambling(struct drm_connector *connector,
struct i2c_adapter *adapter, bool force);+bool drm_disable_scrambling(struct drm_connector *connector,
struct i2c_adapter *adapter, bool force);+bool drm_check_scrambling_status(struct i2c_adapter *adapter);
Old leftovers?
Oops, my bad.
#endif /* __DRM_EDID_H__ */ diff --git a/include/drm/drm_scdc_helper.h b/include/drm/drm_scdc_helper.h index 9c52deb..ab6bcfb 100644 --- a/include/drm/drm_scdc_helper.h +++ b/include/drm/drm_scdc_helper.h @@ -129,4 +129,31 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset, return drm_scdc_write(adapter, offset, &value, sizeof(value)); }
+/**
- drm_scdc_set_scrambling - enable scrambling
- @adapter: I2C adapter for DDC channel
- @enable: bool to indicate if scrambling is to be enabled/disabled
- Writes the TMDS config register over SCDC channel, and:
- enables scrambling when enable = 1
- disables scrambling when enable = 0
- Returns:
- True if scrambling is set/reset successfully, false otherwise.
- */
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
+/**
- drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
- @adapter: I2C adapter for DDC channel
- @set: ret or reset the high clock ratio
- Writes to the TMDS config register over SCDC channel, and:
- sets TMDS clock ratio to 1/40 when set = 1
- sets TMDS clock ratio to 1/10 when set = 0
- Returns:
- True if write is successful, false otherwise.
- */
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
#endif
1.9.1
Geminilake platform sports a native HDMI 2.0 controller, and is capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required, enables it during the modeset.
V2: Addressed review comments from Ville: - Do not track scrambling status in DRM layer, track somewhere in driver like in intel_crtc_state. - Don't talk to monitor at such a low layer, set monitor scrambling in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani - In comments, function names, use "sink" instead of "monitor", so that the implementation could be close to the language of HDMI spec.
V4: Addressed review comment from Maarten - scrambling -> hdmi_scrambling high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander - Do not modifiy the crtc_state after compute_config. Move all scrambling and tmds_clock_ratio calcutations to compute_config. - While setting scrambling for source/sink, do not check the conditions again, just go by the crtc_state flags. This will simplyfy the condition checks.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 14 ++++++ drivers/gpu/drm/i915/intel_hdmi.c | 98 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce6f096..1759b64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7824,7 +7824,11 @@ enum { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) #define TRANS_DDI_BFI_ENABLE (1<<4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) +#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
/* DisplayPort Transport Control */ #define _DP_TP_CTL_A 0x64040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7c08d7..24bc3a8 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1311,6 +1311,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp |= TRANS_DDI_MODE_SELECT_HDMI; else temp |= TRANS_DDI_MODE_SELECT_DVI; + + if (IS_GEMINILAKE(dev_priv)) + temp = intel_hdmi_handle_source_scrambling( + intel_encoder, + intel_crtc->config, temp); } else if (type == INTEL_OUTPUT_ANALOG) { temp |= TRANS_DDI_MODE_SELECT_FDI; temp |= (intel_crtc->config->fdi_lanes - 1) << 1; @@ -1885,6 +1890,21 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ if (IS_GEMINILAKE(dev_priv)) { + struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); + /* + * GLK sports a native HDMI 2.0 controller. If required + * clock rate is > 340 Mhz && scrambling is supported + * by sink, enable scrambling before enabling the + * HDMI 2.0 port. The sink can choose to disable the + * scrambling if it doesn't detect a scrambled within + * 100 ms. + */ + intel_hdmi_handle_sink_scrambling(intel_encoder, + conn_state->connector, + crtc->config, true); + } + /* In HDMI/DVI mode, the port width, and swing/emphasis values * are ignored so nothing special needs to be done besides * enabling the port. @@ -1912,11 +1932,20 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder, struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base; + struct drm_i915_private *dev_priv = encoder->dev->dev_private; int type = intel_encoder->type;
if (old_crtc_state->has_audio) intel_audio_codec_disable(intel_encoder);
+ if ((type == INTEL_OUTPUT_HDMI) && IS_GEMINILAKE(dev_priv)) { + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + + intel_hdmi_handle_sink_scrambling(intel_encoder, + old_conn_state->connector, + intel_crtc->config, false); + } + if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 907fb00..0e53fcd 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -695,6 +695,12 @@ struct intel_crtc_state {
/* Gamma mode programmed on the pipe */ uint32_t gamma_mode; + + /* HDMI scrambling status (sink) */ + bool hdmi_scrambling; + + /* HDMI High TMDS char rate ratio (sink) */ + bool hdmi_high_tmds_clock_ratio; };
struct vlv_wm_state { @@ -1626,6 +1632,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder, + struct intel_crtc_state *config, + uint32_t hdmi_config); +void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder, + struct drm_connector *connector, + struct intel_crtc_state *config, + bool enable); void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index c2184f7..fdbeefd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -34,6 +34,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_scdc_helper.h> #include "intel_drv.h" #include <drm/i915_drm.h> #include <drm/intel_lpe_audio.h> @@ -1316,6 +1317,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; + struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; int clock_12bpc = clock_8bpc * 3 / 2; int desired_bpp; @@ -1385,6 +1387,16 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
+ if (scdc->scrambling.supported) { + if (scdc->scrambling.low_rates) + pipe_config->hdmi_scrambling = true; + + if (pipe_config->port_clock > 340000) { + pipe_config->hdmi_scrambling = true; + pipe_config->hdmi_high_tmds_clock_ratio = true; + } + } + return true; }
@@ -1794,6 +1806,92 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; }
+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder, + struct drm_connector *connector, + struct intel_crtc_state *config, + bool enable) +{ + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); + struct drm_i915_private *dev_priv = connector->dev->dev_private; + struct drm_scrambling *scrambling = + &connector->display_info.hdmi.scdc.scrambling; + struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, + intel_hdmi->ddc_bus); + bool ret; + + if (!scrambling->supported) + return; + + DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", + intel_encoder->base.name, connector->name); + + if (enable) { + + if (config->hdmi_high_tmds_clock_ratio) { + /* Set TMDS bit clock ratio to 1/40 */ + ret = drm_scdc_set_high_tmds_clock_ratio(adptr, true); + if (!ret) { + DRM_ERROR("Set high TMDS ratio failed\n"); + return; + } + } + + if (config->hdmi_scrambling) { + /* Enable sink scrambling */ + ret = drm_scdc_set_scrambling(adptr, true); + if (!ret) { + DRM_ERROR("Can't enable sink scrambling\n"); + return; + } + } + + DRM_DEBUG_KMS("sink scrambling enabled\n"); + return; + } + + if (config->hdmi_high_tmds_clock_ratio) { + /* Set TMDS bit clock ratio back to 1/10 */ + ret = !(drm_scdc_set_high_tmds_clock_ratio(adptr, false)); + if (ret) + DRM_ERROR("Reset high TMDS ratio failed\n"); + } + + if (config->hdmi_scrambling) { + /* Disable sink scrambling */ + ret = !(drm_scdc_set_scrambling(adptr, false)); + if (ret) + DRM_ERROR("Disable sink scrambling failed\n"); + } + + DRM_DEBUG_KMS("sink scrambling disabled\n"); +} + +uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder, + struct intel_crtc_state *config, uint32_t hdmi_config) +{ + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); + struct drm_connector *connector = &intel_hdmi->attached_connector->base; + + DRM_DEBUG_KMS("Setting scrambling for enc:%s connector:%s\n", + intel_encoder->base.name, connector->name); + + hdmi_config &= ~(TRANS_DDI_HDMI_SCRAMBLING | + TRANS_DDI_HIGH_TMDS_CHAR_RATE | + TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ | + TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE); + + if (config->hdmi_scrambling) + hdmi_config |= (TRANS_DDI_HDMI_SCRAMBLING | + TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ | + TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE); + + if (config->hdmi_high_tmds_clock_ratio) + hdmi_config |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; + + return hdmi_config; +} + static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) {
On Tue, Feb 28, 2017 at 02:09:09PM +0530, Shashank Sharma wrote:
Geminilake platform sports a native HDMI 2.0 controller, and is capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required, enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor", so that the implementation could be close to the language of HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the conditions again, just go by the crtc_state flags. This will simplyfy the condition checks.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com
drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 14 ++++++ drivers/gpu/drm/i915/intel_hdmi.c | 98 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce6f096..1759b64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7824,7 +7824,11 @@ enum { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) #define TRANS_DDI_BFI_ENABLE (1<<4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) +#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
/* DisplayPort Transport Control */ #define _DP_TP_CTL_A 0x64040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7c08d7..24bc3a8 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1311,6 +1311,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp |= TRANS_DDI_MODE_SELECT_HDMI; else temp |= TRANS_DDI_MODE_SELECT_DVI;
if (IS_GEMINILAKE(dev_priv))temp = intel_hdmi_handle_source_scrambling(intel_encoder,intel_crtc->config, temp);@@ -1885,6 +1890,21 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
if (IS_GEMINILAKE(dev_priv)) {struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);/** GLK sports a native HDMI 2.0 controller. If required* clock rate is > 340 Mhz && scrambling is supported* by sink, enable scrambling before enabling the* HDMI 2.0 port. The sink can choose to disable the* scrambling if it doesn't detect a scrambled within* 100 ms.*/intel_hdmi_handle_sink_scrambling(intel_encoder,conn_state->connector,crtc->config, true);}- /* In HDMI/DVI mode, the port width, and swing/emphasis values
- are ignored so nothing special needs to be done besides
- enabling the port.
@@ -1912,11 +1932,20 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder, struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private; int type = intel_encoder->type;
if (old_crtc_state->has_audio) intel_audio_codec_disable(intel_encoder);
if ((type == INTEL_OUTPUT_HDMI) && IS_GEMINILAKE(dev_priv)) {
^ ^
Pointless parens. Also I'm nor sure we want the platform check here. Seems to me that we should be able to just explicitly configure the sink on every platform, iff the sink supports SCDC of course.
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);intel_hdmi_handle_sink_scrambling(intel_encoder,old_conn_state->connector,intel_crtc->config, false);- }
- if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 907fb00..0e53fcd 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -695,6 +695,12 @@ struct intel_crtc_state {
/* Gamma mode programmed on the pipe */ uint32_t gamma_mode;
- /* HDMI scrambling status (sink) */
- bool hdmi_scrambling;
- /* HDMI High TMDS char rate ratio (sink) */
- bool hdmi_high_tmds_clock_ratio;
};
struct vlv_wm_state { @@ -1626,6 +1632,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config,uint32_t hdmi_config);+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable);void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index c2184f7..fdbeefd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -34,6 +34,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_scdc_helper.h> #include "intel_drv.h" #include <drm/i915_drm.h> #include <drm/intel_lpe_audio.h> @@ -1316,6 +1317,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; int clock_12bpc = clock_8bpc * 3 / 2; int desired_bpp;
@@ -1385,6 +1387,16 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported) {
Here we should have a check whether the source support scrambling or not.
if (scdc->scrambling.low_rates)pipe_config->hdmi_scrambling = true;if (pipe_config->port_clock > 340000) {pipe_config->hdmi_scrambling = true;pipe_config->hdmi_high_tmds_clock_ratio = true;}- }
- return true;
}
@@ -1794,6 +1806,92 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; }
+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct drm_scrambling *scrambling =
&connector->display_info.hdmi.scdc.scrambling;- struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
intel_hdmi->ddc_bus);- bool ret;
- if (!scrambling->supported)
return;- DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- if (enable) {
if (config->hdmi_high_tmds_clock_ratio) {/* Set TMDS bit clock ratio to 1/40 */ret = drm_scdc_set_high_tmds_clock_ratio(adptr, true);if (!ret) {DRM_ERROR("Set high TMDS ratio failed\n");return;}}if (config->hdmi_scrambling) {/* Enable sink scrambling */ret = drm_scdc_set_scrambling(adptr, true);if (!ret) {DRM_ERROR("Can't enable sink scrambling\n");return;}}DRM_DEBUG_KMS("sink scrambling enabled\n");return;- }
- if (config->hdmi_high_tmds_clock_ratio) {
/* Set TMDS bit clock ratio back to 1/10 */ret = !(drm_scdc_set_high_tmds_clock_ratio(adptr, false));if (ret)DRM_ERROR("Reset high TMDS ratio failed\n");- }
- if (config->hdmi_scrambling) {
/* Disable sink scrambling */ret = !(drm_scdc_set_scrambling(adptr, false));if (ret)DRM_ERROR("Disable sink scrambling failed\n");- }
Seems a little complicated for what it's doing.
I'd go for something simple like:
foo(bool scrambling, bool clock_ratio) { set_scrambling(scrambling); set_clock_ratio(clock_ratio); }
enable() { foo(crtc_state->hdmi_scrambling, crtc_state->clock_ratio); }
disable() { foo(false, false); }
- DRM_DEBUG_KMS("sink scrambling disabled\n");
+}
+uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config, uint32_t hdmi_config)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_connector *connector = &intel_hdmi->attached_connector->base;
- DRM_DEBUG_KMS("Setting scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- hdmi_config &= ~(TRANS_DDI_HDMI_SCRAMBLING |
TRANS_DDI_HIGH_TMDS_CHAR_RATE |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_scrambling)
hdmi_config |= (TRANS_DDI_HDMI_SCRAMBLING |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_high_tmds_clock_ratio)
hdmi_config |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
IMO just inline these two things into the function that configures this register. Having to jump around between functions is just extra pain we don't need IMO.
There should also be corresponding readout code for this in intel_ddi_get_config(), and matching PIPE_CONF_CHECK stuff in intel_pipe_config_compare().
- return hdmi_config;
+}
static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { -- 1.9.1
Regards
Shashank
On 3/1/2017 8:41 PM, Ville Syrjälä wrote:
On Tue, Feb 28, 2017 at 02:09:09PM +0530, Shashank Sharma wrote:
Geminilake platform sports a native HDMI 2.0 controller, and is capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required, enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor", so that the implementation could be close to the language of HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the conditions again, just go by the crtc_state flags. This will simplyfy the condition checks.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com
drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 14 ++++++ drivers/gpu/drm/i915/intel_hdmi.c | 98 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce6f096..1759b64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7824,7 +7824,11 @@ enum { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) #define TRANS_DDI_BFI_ENABLE (1<<4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) +#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
/* DisplayPort Transport Control */ #define _DP_TP_CTL_A 0x64040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7c08d7..24bc3a8 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1311,6 +1311,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp |= TRANS_DDI_MODE_SELECT_HDMI; else temp |= TRANS_DDI_MODE_SELECT_DVI;
if (IS_GEMINILAKE(dev_priv))temp = intel_hdmi_handle_source_scrambling(intel_encoder,intel_crtc->config, temp);@@ -1885,6 +1890,21 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
if (IS_GEMINILAKE(dev_priv)) {struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);/** GLK sports a native HDMI 2.0 controller. If required* clock rate is > 340 Mhz && scrambling is supported* by sink, enable scrambling before enabling the* HDMI 2.0 port. The sink can choose to disable the* scrambling if it doesn't detect a scrambled within* 100 ms.*/intel_hdmi_handle_sink_scrambling(intel_encoder,conn_state->connector,crtc->config, true);}- /* In HDMI/DVI mode, the port width, and swing/emphasis values
- are ignored so nothing special needs to be done besides
- enabling the port.
@@ -1912,11 +1932,20 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder, struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private; int type = intel_encoder->type;
if (old_crtc_state->has_audio) intel_audio_codec_disable(intel_encoder);
if ((type == INTEL_OUTPUT_HDMI) && IS_GEMINILAKE(dev_priv)) {
^ ^Pointless parens. Also I'm nor sure we want the platform check here. Seems to me that we should be able to just explicitly configure the sink on every platform, iff the sink supports SCDC of course.
This is interesting, what if I connect a HDMI 2.0 sink, which supports scrambling to a GEN8 or non-lspcon GEN 9 device ? Shouldn't we check if the source also allows it ?
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);intel_hdmi_handle_sink_scrambling(intel_encoder,old_conn_state->connector,intel_crtc->config, false);- }
- if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 907fb00..0e53fcd 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -695,6 +695,12 @@ struct intel_crtc_state {
/* Gamma mode programmed on the pipe */ uint32_t gamma_mode;
/* HDMI scrambling status (sink) */
bool hdmi_scrambling;
/* HDMI High TMDS char rate ratio (sink) */
bool hdmi_high_tmds_clock_ratio; };
struct vlv_wm_state {
@@ -1626,6 +1632,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config,uint32_t hdmi_config);+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable);diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index c2184f7..fdbeefd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -34,6 +34,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_scdc_helper.h> #include "intel_drv.h" #include <drm/i915_drm.h> #include <drm/intel_lpe_audio.h> @@ -1316,6 +1317,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; int clock_12bpc = clock_8bpc * 3 / 2; int desired_bpp;
@@ -1385,6 +1387,16 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported) {
Here we should have a check whether the source support scrambling or not.
Ok, makes sense.
if (scdc->scrambling.low_rates)pipe_config->hdmi_scrambling = true;if (pipe_config->port_clock > 340000) {pipe_config->hdmi_scrambling = true;pipe_config->hdmi_high_tmds_clock_ratio = true;}- }
- return true; }
@@ -1794,6 +1806,92 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; }
+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct drm_scrambling *scrambling =
&connector->display_info.hdmi.scdc.scrambling;- struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
intel_hdmi->ddc_bus);- bool ret;
- if (!scrambling->supported)
return;- DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- if (enable) {
if (config->hdmi_high_tmds_clock_ratio) {/* Set TMDS bit clock ratio to 1/40 */ret = drm_scdc_set_high_tmds_clock_ratio(adptr, true);if (!ret) {DRM_ERROR("Set high TMDS ratio failed\n");return;}}if (config->hdmi_scrambling) {/* Enable sink scrambling */ret = drm_scdc_set_scrambling(adptr, true);if (!ret) {DRM_ERROR("Can't enable sink scrambling\n");return;}}DRM_DEBUG_KMS("sink scrambling enabled\n");return;- }
- if (config->hdmi_high_tmds_clock_ratio) {
/* Set TMDS bit clock ratio back to 1/10 */ret = !(drm_scdc_set_high_tmds_clock_ratio(adptr, false));if (ret)DRM_ERROR("Reset high TMDS ratio failed\n");- }
- if (config->hdmi_scrambling) {
/* Disable sink scrambling */ret = !(drm_scdc_set_scrambling(adptr, false));if (ret)DRM_ERROR("Disable sink scrambling failed\n");- }
Seems a little complicated for what it's doing.
I'd go for something simple like:
foo(bool scrambling, bool clock_ratio) { set_scrambling(scrambling); set_clock_ratio(clock_ratio); }
enable() { foo(crtc_state->hdmi_scrambling, crtc_state->clock_ratio); }
disable() { foo(false, false); }
In the first look, I thought intel_hdmi_handle_sink_scrambling is your foo, but later I realized, you dont want an if (enable) cond.... will take care of it.
- DRM_DEBUG_KMS("sink scrambling disabled\n");
+}
+uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config, uint32_t hdmi_config)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_connector *connector = &intel_hdmi->attached_connector->base;
- DRM_DEBUG_KMS("Setting scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- hdmi_config &= ~(TRANS_DDI_HDMI_SCRAMBLING |
TRANS_DDI_HIGH_TMDS_CHAR_RATE |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_scrambling)
hdmi_config |= (TRANS_DDI_HDMI_SCRAMBLING |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_high_tmds_clock_ratio)
hdmi_config |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;IMO just inline these two things into the function that configures this register. Having to jump around between functions is just extra pain we don't need IMO.
Not really, this function is also making sure, that the scrambling bits are cleared, and only enabled which is required. Also, this is making code more readable, segregating scrambling functionalities, and better for debugging too. Lets keep this one if you please allow.
There should also be corresponding readout code for this in intel_ddi_get_config(), and matching PIPE_CONF_CHECK stuff in intel_pipe_config_compare().
Agree, will add that too.
- Shashank
- return hdmi_config;
+}
- static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) {
-- 1.9.1
On Thu, 2017-03-02 at 08:25 +0530, Sharma, Shashank wrote:
Regards
Shashank
On 3/1/2017 8:41 PM, Ville Syrjälä wrote:
On Tue, Feb 28, 2017 at 02:09:09PM +0530, Shashank Sharma wrote:
Geminilake platform sports a native HDMI 2.0 controller, and is capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required, enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor", so that the implementation could be close to the language of HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the conditions again, just go by the crtc_state flags. This will simplyfy the condition checks.
Signed-off-by: Shashank Sharma shashank.sharma@intel.com
drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_ddi.c | 29 ++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 14 ++++++ drivers/gpu/drm/i915/intel_hdmi.c | 98 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce6f096..1759b64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7824,7 +7824,11 @@ enum { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) #define TRANS_DDI_BFI_ENABLE (1<<4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) +#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
/* DisplayPort Transport Control */ #define _DP_TP_CTL_A 0x64040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a7c08d7..24bc3a8 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1311,6 +1311,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp |= TRANS_DDI_MODE_SELECT_HDMI; else temp |= TRANS_DDI_MODE_SELECT_DVI;
if (IS_GEMINILAKE(dev_priv))temp = intel_hdmi_handle_source_scrambling(intel_encoder,intel_crtc->config, temp);@@ -1885,6 +1890,21 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
if (IS_GEMINILAKE(dev_priv)) {struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);/** GLK sports a native HDMI 2.0 controller. If required* clock rate is > 340 Mhz && scrambling is supported* by sink, enable scrambling before enabling the* HDMI 2.0 port. The sink can choose to disable the* scrambling if it doesn't detect a scrambled within* 100 ms.*/intel_hdmi_handle_sink_scrambling(intel_encoder,conn_state->connector,crtc->config, true);}- /* In HDMI/DVI mode, the port width, and swing/emphasis values
- are ignored so nothing special needs to be done besides
- enabling the port.
@@ -1912,11 +1932,20 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder, struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = encoder->dev->dev_private; int type = intel_encoder->type;
if (old_crtc_state->has_audio) intel_audio_codec_disable(intel_encoder);
if ((type == INTEL_OUTPUT_HDMI) && IS_GEMINILAKE(dev_priv)) {
^ ^Pointless parens. Also I'm nor sure we want the platform check here. Seems to me that we should be able to just explicitly configure the sink on every platform, iff the sink supports SCDC of course.
This is interesting, what if I connect a HDMI 2.0 sink, which supports scrambling to a GEN8 or non-lspcon GEN 9 device ? Shouldn't we check if the source also allows it ?
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);intel_hdmi_handle_sink_scrambling(intel_encoder,old_conn_state->connector,intel_crtc->config, false);- }
- if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 907fb00..0e53fcd 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -695,6 +695,12 @@ struct intel_crtc_state {
/* Gamma mode programmed on the pipe */ uint32_t gamma_mode;
/* HDMI scrambling status (sink) */
bool hdmi_scrambling;
/* HDMI High TMDS char rate ratio (sink) */
bool hdmi_high_tmds_clock_ratio; };
struct vlv_wm_state {
@@ -1626,6 +1632,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config,uint32_t hdmi_config);+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable);diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index c2184f7..fdbeefd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -34,6 +34,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_scdc_helper.h> #include "intel_drv.h" #include <drm/i915_drm.h> #include <drm/intel_lpe_audio.h> @@ -1316,6 +1317,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; int clock_12bpc = clock_8bpc * 3 / 2; int desired_bpp;
@@ -1385,6 +1387,16 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported) {
Here we should have a check whether the source support scrambling or not.
Ok, makes sense.
if (scdc->scrambling.low_rates)pipe_config->hdmi_scrambling = true;if (pipe_config->port_clock > 340000) {pipe_config->hdmi_scrambling = true;pipe_config->hdmi_high_tmds_clock_ratio = true;}- }
- return true; }
@@ -1794,6 +1806,92 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; }
+void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
struct drm_connector *connector,struct intel_crtc_state *config,bool enable)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct drm_scrambling *scrambling =
&connector->display_info.hdmi.scdc.scrambling;- struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
intel_hdmi->ddc_bus);- bool ret;
- if (!scrambling->supported)
return;- DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- if (enable) {
if (config->hdmi_high_tmds_clock_ratio) {/* Set TMDS bit clock ratio to 1/40 */ret = drm_scdc_set_high_tmds_clock_ratio(adptr, true);if (!ret) {DRM_ERROR("Set high TMDS ratio failed\n");return;}}if (config->hdmi_scrambling) {/* Enable sink scrambling */ret = drm_scdc_set_scrambling(adptr, true);if (!ret) {DRM_ERROR("Can't enable sink scrambling\n");return;}}DRM_DEBUG_KMS("sink scrambling enabled\n");return;- }
- if (config->hdmi_high_tmds_clock_ratio) {
/* Set TMDS bit clock ratio back to 1/10 */ret = !(drm_scdc_set_high_tmds_clock_ratio(adptr, false));if (ret)DRM_ERROR("Reset high TMDS ratio failed\n");- }
- if (config->hdmi_scrambling) {
/* Disable sink scrambling */ret = !(drm_scdc_set_scrambling(adptr, false));if (ret)DRM_ERROR("Disable sink scrambling failed\n");- }
Seems a little complicated for what it's doing.
I'd go for something simple like:
foo(bool scrambling, bool clock_ratio) { set_scrambling(scrambling); set_clock_ratio(clock_ratio); }
enable() { foo(crtc_state->hdmi_scrambling, crtc_state->clock_ratio); }
disable() { foo(false, false); }
In the first look, I thought intel_hdmi_handle_sink_scrambling is your foo, but later I realized, you dont want an if (enable) cond.... will take care of it.
- DRM_DEBUG_KMS("sink scrambling disabled\n");
+}
+uint32_t +intel_hdmi_handle_source_scrambling(struct intel_encoder *intel_encoder,
struct intel_crtc_state *config, uint32_t hdmi_config)+{
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
- struct drm_connector *connector = &intel_hdmi->attached_connector->base;
- DRM_DEBUG_KMS("Setting scrambling for enc:%s connector:%s\n",
intel_encoder->base.name, connector->name);- hdmi_config &= ~(TRANS_DDI_HDMI_SCRAMBLING |
TRANS_DDI_HIGH_TMDS_CHAR_RATE |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_scrambling)
hdmi_config |= (TRANS_DDI_HDMI_SCRAMBLING |TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ |TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE);- if (config->hdmi_high_tmds_clock_ratio)
hdmi_config |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;IMO just inline these two things into the function that configures this register. Having to jump around between functions is just extra pain we don't need IMO.
Not really, this function is also making sure, that the scrambling bits are cleared,
There is no read-modify-write in intel_ddi_enable_transcoder_func(). Every bit that is not explicitly set is cleared.
and only enabled which is required. Also, this is making code more readable, segregating scrambling functionalities, and better for debugging too. Lets keep this one if you please allow.
I think the extra function makes it harder to read. The function intel_ddi_enable_transcoder_func() only translates the current configuration to the right bits that need to be programmed to TRANS_DDI_FUNC_CTL. That belongs in intel_ddi.c.
To help with debugging, add HDMI scrambling prints to intel_dump_pipe_config(). That's actually more useful than the print in this function since it can also tell us if scrambling was enabled for a configuration read out from hw state.
Ander
There should also be corresponding readout code for this in intel_ddi_get_config(), and matching PIPE_CONF_CHECK stuff in intel_pipe_config_compare().
Agree, will add that too.
- Shashank
- return hdmi_config;
+}
- static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) {
-- 1.9.1
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Geminilake has a native HDMI 2.0 controller, which is capable of driving clocks upto 594Mhz. This patch updates the max tmds clock limit for the same.
V2: rebase V3: rebase V4: added r-b from Ander V5: rebase
Cc: Ander Conselvan De Oliveira ander.conselvan.de.oliveira@intel.com Signed-off-by: Shashank Sharma shashank.sharma@intel.com Reviewed-by: Ander Conselvan De Oliveira ander.conselvan.de.oliveira@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index fdbeefd..d44b9fb 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1209,6 +1209,8 @@ static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) { if (IS_G4X(dev_priv)) return 165000; + else if (IS_GEMINILAKE(dev_priv)) + return 594000; else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) return 300000; else
dri-devel@lists.freedesktop.org
-
Ander Conselvan De Oliveira -
Sharma, Shashank -
Shashank Sharma
-
Ville Syrjälä