New subject: [PATCH] radeon: Fix disabling PCI bus mastering on big endian hosts.

5 Jan 2012

From: Michel Dänzer michel.daenzer@amd.com
It would previously write basically random bits to PCI configuration space...
Not very surprising that the GPU tended to stop responding completely. The
resulting MCE even froze the whole machine sometimes.
Now resetting the GPU after a lockup has at least a fighting chance of
succeeding.
Cc: stable@vger.kernel.org
Signed-off-by: Michel Dänzer michel.daenzer@amd.com
---
 drivers/gpu/drm/radeon/r100.c  |    5 +++--
 drivers/gpu/drm/radeon/rs600.c |    4 ++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 9cf5197..7e94ea5 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2186,6 +2186,7 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 void r100_bm_disable(struct radeon_device *rdev)
 {
    u32 tmp;
+	u16 tmp16;
/* disable bus mastering */
    tmp = RREG32(R_000030_BUS_CNTL);
@@ -2196,8 +2197,8 @@ void r100_bm_disable(struct radeon_device *rdev)
    WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
    tmp = RREG32(RADEON_BUS_CNTL);
    mdelay(1);
-	pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
-	pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
+	pci_read_config_word(rdev->pdev, 0x4, &tmp16);
+	pci_write_config_word(rdev->pdev, 0x4, tmp16 & 0xFFFB);
    mdelay(1);
 }
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index ca6d5b6..803e0d3 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -324,10 +324,10 @@ void rs600_hpd_fini(struct radeon_device *rdev)
void rs600_bm_disable(struct radeon_device *rdev)
 {
-	u32 tmp;
+	u16 tmp;
/* disable bus mastering */
-	pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
+	pci_read_config_word(rdev->pdev, 0x4, &tmp);
    pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
    mdelay(1);
 }
-- 
1.7.7.3


    