The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead.
Note: testing of this series was limited to SDM845 and the 10nm PHY
Major changes in v3: - keep supporting DTs without ref clock for the 28nm and the 28nm 8960 PHYs - added patch to add ref clock to qcom-apq8064.dtsi
Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm
Matthias Kaehlcke (8): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT drm/msm/dsi: 28nm PHY: Get ref clock from the DT drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 10nm PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
.../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 ++++++- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +++++++-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 35 ++++++++++++++----- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 ++++++++++++--- 8 files changed, 87 insertions(+), 26 deletions(-)
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke mka@chromium.org --- Changes in V3: - added note that the ref clock is only required for new DTS files/entries
Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
Quoting Matthias Kaehlcke (2018-11-30 16:52:47)
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Reviewed-by: Stephen Boyd swboyd@chromium.org
Hi,
On Fri, Nov 30, 2018 at 4:53 PM Matthias Kaehlcke mka@chromium.org wrote:
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Changes in V3:
- added note that the ref clock is only required for new DTS files/entries
Changes in v2:
- add the ref clock for all PHYs, not only the 10nm one
- updated commit message
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Douglas Anderson dianders@chromium.org
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified.
Signed-off-by: Matthias Kaehlcke mka@chromium.org --- Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2: - patch added to the series --- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..3af678d3317f6 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,9 +47,9 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 27000000 -#define VCO_MIN_RATE 600000000 -#define VCO_MAX_RATE 1200000000 +#define VCO_REF_CLK_DEFAULT_RATE 27000000 +#define VCO_MIN_RATE 600000000 +#define VCO_MAX_RATE 1200000000
#define DSI_BYTE_PLL_CLK 0 #define DSI_PIXEL_PLL_CLK 1 @@ -75,6 +75,8 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
+ const char *vco_ref_clk_name; + /* custom byte clock divider */ struct clk_bytediv *bytediv;
@@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10; - val = VCO_REF_CLK_RATE / 10; + if (parent_rate) + val = parent_rate / 10; + else + val = VCO_REF_CLK_DEFAULT_RATE / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, @@ -410,7 +415,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char *clk_name, *parent_name, *vco_name; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, + .parent_names = &pll_28nm->vco_ref_clk_name, .num_parents = 1, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, @@ -494,6 +499,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; int ret;
if (!pdev) @@ -506,6 +512,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id + 1;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + return ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + pll_28nm->vco_ref_clk_name = "pxo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified.
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Changes in v3:
- use default name and rate if the ref clock is not specified in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..3af678d3317f6 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,9 +47,9 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 27000000 -#define VCO_MIN_RATE 600000000 -#define VCO_MAX_RATE 1200000000 +#define VCO_REF_CLK_DEFAULT_RATE 27000000 +#define VCO_MIN_RATE 600000000 +#define VCO_MAX_RATE 1200000000
#define DSI_BYTE_PLL_CLK 0 #define DSI_PIXEL_PLL_CLK 1 @@ -75,6 +75,8 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
const char *vco_ref_clk_name;
Can this be passed around during clk registration so we don't have to store it away in the structure?
/* custom byte clock divider */ struct clk_bytediv *bytediv;@@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
val = VCO_REF_CLK_RATE / 10;
if (parent_rate)val = parent_rate / 10;elseval = VCO_REF_CLK_DEFAULT_RATE / 10;
Is the clk not properly hooked up to a parent sometimes so parent_rate is 0? That sounds odd given the fact that it used to be 'pxo' and that has always existed on the system as 27 MHz. So I'd remove this and just use parent_rate all the time.
On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified.
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Changes in v3:
- use default name and rate if the ref clock is not specified in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..3af678d3317f6 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,9 +47,9 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 27000000 -#define VCO_MIN_RATE 600000000 -#define VCO_MAX_RATE 1200000000 +#define VCO_REF_CLK_DEFAULT_RATE 27000000 +#define VCO_MIN_RATE 600000000 +#define VCO_MAX_RATE 1200000000
#define DSI_BYTE_PLL_CLK 0 #define DSI_PIXEL_PLL_CLK 1 @@ -75,6 +75,8 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
const char *vco_ref_clk_name;Can this be passed around during clk registration so we don't have to store it away in the structure?
makes sense, will do
/* custom byte clock divider */ struct clk_bytediv *bytediv;@@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
val = VCO_REF_CLK_RATE / 10;
if (parent_rate)val = parent_rate / 10;elseval = VCO_REF_CLK_DEFAULT_RATE / 10;Is the clk not properly hooked up to a parent sometimes so parent_rate is 0? That sounds odd given the fact that it used to be 'pxo' and that has always existed on the system as 27 MHz. So I'd remove this and just use parent_rate all the time.
I wondered about this, but since I don't have hardware for testing I kept the previous hardcoded rate. If we know for sure that 'pxo' always exists it should indeed be fine to use the parent rate.
Quoting Matthias Kaehlcke (2018-12-04 09:35:49)
On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
/* custom byte clock divider */ struct clk_bytediv *bytediv;@@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
val = VCO_REF_CLK_RATE / 10;
if (parent_rate)val = parent_rate / 10;elseval = VCO_REF_CLK_DEFAULT_RATE / 10;Is the clk not properly hooked up to a parent sometimes so parent_rate is 0? That sounds odd given the fact that it used to be 'pxo' and that has always existed on the system as 27 MHz. So I'd remove this and just use parent_rate all the time.
I wondered about this, but since I don't have hardware for testing I kept the previous hardcoded rate. If we know for sure that 'pxo' always exists it should indeed be fine to use the parent rate.
Yes we know for sure. The 'pxo' board clk is there on apq8064 dtsi file which seems to be the only place this is used. The pxo_board clk is sent through a 'pxo' clk that's created in drivers/clk/qcom/common.c qcom_cc_register_board_clk().
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified.
Signed-off-by: Matthias Kaehlcke mka@chromium.org --- Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to unsigned long - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 35 ++++++++++++++++------ 1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 26e3a01a99c2b..4a84c69ca0b2b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -40,7 +40,7 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 19200000 +#define VCO_REF_CLK_DEFAULT_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000
@@ -81,6 +81,7 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
+ const char *vco_ref_clk_name; int vco_delay;
/* private clocks: */ @@ -139,6 +140,8 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; + unsigned long ref_clk_rate = parent_rate ? + parent_rate : VCO_REF_CLK_DEFAULT_RATE; unsigned long div_fbx1000, gen_vco_clk; u32 refclk_cfg, frac_n_mode, frac_n_value; u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; @@ -166,17 +169,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE; + rem = rate % ref_clk_rate; if (rem) { refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; frac_n_mode = 1; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + div_fbx1000 = rate / (ref_clk_rate / 500); + gen_vco_clk = div_fbx1000 * (ref_clk_rate / 500); } else { refclk_cfg = 0x0; frac_n_mode = 0; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + div_fbx1000 = rate / (ref_clk_rate / 1000); + gen_vco_clk = div_fbx1000 * (ref_clk_rate / 1000); }
DBG("refclk_cfg = %d", refclk_cfg); @@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; - u32 ref_clk = VCO_REF_CLK_RATE; + u32 ref_clk = parent_rate ? + parent_rate : VCO_REF_CLK_DEFAULT_RATE; unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate); @@ -273,7 +277,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, /* Check to see if the ref clk doubler is enabled */ doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - ref_clk += (doubler * VCO_REF_CLK_RATE); + ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */ sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); @@ -518,7 +522,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &pll_28nm->vco_ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -593,6 +597,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; int ret;
if (!pdev) @@ -605,6 +610,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + pll_28nm->vco_ref_clk_name = "xo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
Quoting Matthias Kaehlcke (2018-11-30 16:52:49)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 26e3a01a99c2b..4a84c69ca0b2b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -81,6 +81,7 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
const char *vco_ref_clk_name; int vco_delay; /* private clocks: */@@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
u32 ref_clk = VCO_REF_CLK_RATE;
u32 ref_clk = parent_rate ?parent_rate : VCO_REF_CLK_DEFAULT_RATE;
Same comments apply here.
unsigned long vco_rate; VERB("parent_rate=%lu", parent_rate);
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson dianders@chromium.org' tag
Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c index 71fe60e5f01f1..032bf3e8614bd 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c @@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 1300000000UL #define VCO_MAX_RATE 2600000000UL
@@ -139,6 +138,7 @@ struct dsi_pll_14nm { /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock;
+ struct clk *vco_ref_clk; u64 vco_current_rate; u64 vco_ref_clk_rate;
@@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, parent_rate);
pll_14nm->vco_current_rate = rate; - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) { char clk_name[32], parent[32], vco_name[32]; + const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk); struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll_14nm->id = id; pll_14nm_list[id] = pll_14nm;
+ pll_14nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(pll_14nm->vco_ref_clk)) { + ret = PTR_ERR(pll_14nm->vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n");
Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that use the 10nm PHY
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson dianders@chromium.org' tag
Changes in v2: - remove anonymous array in clk_init_data assignment - log error code if devm_clk_get() fails - don't log devm_clk_get() failures for -EPROBE_DEFER - updated commit message --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 4c03f0b7343ed..2d23372acd20d 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -91,6 +91,7 @@ struct dsi_pll_10nm { void __iomem *phy_cmn_mmio; void __iomem *mmio;
+ struct clk *vco_ref_clk; u64 vco_ref_clk_rate; u64 vco_current_rate;
@@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) { char clk_name[32], parent[32], vco_name[32]; char parent2[32], parent3[32], parent4[32]; + const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk); struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll_10nm->id = id; pll_10nm_list[id] = pll_10nm;
+ pll_10nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(pll_10nm->vco_ref_clk)) { + ret = PTR_ERR(pll_10nm->vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n");
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- Changes in v3: - added 'Reviewed-by: Douglas Anderson dianders@chromium.org' tag
Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>;
- clocks = <&gcc GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; }; };
Quoting Matthias Kaehlcke (2018-11-30 16:52:52)
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org
Reviewed-by: Stephen Boyd swboyd@chromium.org
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org --- based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file" (https://patchwork.kernel.org/patch/10666253/)
Changes in v3: - added 'Reviewed-by: Douglas Anderson dianders@chromium.org' tag
Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5728b4cfae269..cdb5a9bb23e69 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1372,8 +1372,9 @@ #clock-cells = <1>; #phy-cells = <0>;
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; };
dsi1: dsi@ae96000 { @@ -1434,8 +1435,9 @@ #clock-cells = <1>; #phy-cells = <0>;
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; }; };
Quoting Matthias Kaehlcke (2018-11-30 16:52:53)
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Douglas Anderson dianders@chromium.org
Reviewed-by: Stephen Boyd swboyd@chromium.org
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke mka@chromium.org --- Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&xo_board>; };
Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Why is driver in quotes?
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Reviewed-by: Stephen Boyd swboyd@chromium.org
On Tue, Dec 04, 2018 at 08:48:22AM -0800, Stephen Boyd wrote:
Quoting Matthias Kaehlcke (2018-11-30 16:52:54)
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Why is driver in quotes?
It's not really a full fledged driver, but part of the 28nm 8960 PHY driver.
Signed-off-by: Matthias Kaehlcke mka@chromium.org
Reviewed-by: Stephen Boyd swboyd@chromium.org
Thanks for the review!
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