This patchset adds HDMI support for the Tegra114 Dalmore board. Tested with 1080p DVI and HDMI monitors.
Mikko Perttunen (6): host1x: hdmi: Add Tegra114 support host1x: hdmi: Detect whether display is connected with HDMI or DVI host1x: hdmi: Enable Vdd earlier for hotplug/DDC clk: tegra114: Initialize clocks needed for HDMI ARM: tegra: Add host1x, DC and HDMI to Tegra114 device tree ARM: tegra: Add HDMI to Tegra114 Dalmore device tree
arch/arm/boot/dts/tegra114-dalmore.dts | 17 ++++ arch/arm/boot/dts/tegra114.dtsi | 42 +++++++++ drivers/clk/tegra/clk-tegra114.c | 3 + drivers/gpu/host1x/dev.c | 1 + drivers/gpu/host1x/drm/drm.c | 1 + drivers/gpu/host1x/drm/hdmi.c | 125 ++++++++++++++++++++++++--- drivers/gpu/host1x/drm/hdmi.h | 152 +++++++++++++++++++++++++++++++++ 7 files changed, 331 insertions(+), 10 deletions(-)
Add Tegra114 TMDS configuration, add new peak_current field and use new place for drive current override bit on Tegra114 platform.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/gpu/host1x/dev.c | 1 + drivers/gpu/host1x/drm/drm.c | 1 + drivers/gpu/host1x/drm/hdmi.c | 102 +++++++++++++++++++++++++++- drivers/gpu/host1x/drm/hdmi.h | 152 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 253 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 28e28a2..421d469 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -80,6 +80,7 @@ static const struct host1x_info host1x01_info = { };
static struct of_device_id host1x_of_match[] = { + { .compatible = "nvidia,tegra114-host1x", .data = &host1x01_info, }, { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, { }, diff --git a/drivers/gpu/host1x/drm/drm.c b/drivers/gpu/host1x/drm/drm.c index 8c61cee..37f5166 100644 --- a/drivers/gpu/host1x/drm/drm.c +++ b/drivers/gpu/host1x/drm/drm.c @@ -88,6 +88,7 @@ static int host1x_parse_dt(struct host1x_drm *host1x) "nvidia,tegra30-dc", "nvidia,tegra30-hdmi", "nvidia,tegra30-gr2d", + "nvidia,tegra114-hdmi", }; unsigned int i; int err; diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index 01097da..d81fac8 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -149,6 +149,7 @@ struct tmds_config { u32 pll1; u32 pe_current; u32 drive_current; + u32 peak_current; };
static const struct tmds_config tegra2_tmds_config[] = { @@ -230,6 +231,85 @@ static const struct tmds_config tegra3_tmds_config[] = { }, };
+const struct tmds_config tegra114_tmds_config[] = { + { /* 480p/576p / 25.2MHz/27MHz modes */ + .pclk = 27000000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 720p / 74.25MHz modes */ + .pclk = 74250000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | + PE_CURRENT1(PE_CURRENT_15_mA_T114) | + PE_CURRENT2(PE_CURRENT_15_mA_T114) | + PE_CURRENT3(PE_CURRENT_15_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 1080p / 148.5MHz modes */ + .pclk = 148500000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | + PE_CURRENT1(PE_CURRENT_10_mA_T114) | + PE_CURRENT2(PE_CURRENT_10_mA_T114) | + PE_CURRENT3(PE_CURRENT_10_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 225/297MHz modes */ + .pclk = UINT_MAX, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) + | SOR_PLL_TMDS_TERM_ENABLE, + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), + }, +}; + static const struct tegra_hdmi_audio_config * tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) { @@ -593,8 +673,20 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
- value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE; - tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + if (of_device_is_compatible(hdmi->dev->of_node, + "nvidia,tegra114-hdmi")) { + tegra_hdmi_writel(hdmi, tmds->drive_current, + HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PAD_CTLS0); + value |= DRIVE_CURRENT_FUSE_OVERRIDE_T114; + tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PAD_CTLS0); + tegra_hdmi_writel(hdmi, tmds->peak_current, + HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); + } else { + value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE; + tegra_hdmi_writel(hdmi, value, + HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); + } }
static int tegra_output_hdmi_enable(struct tegra_output *output) @@ -726,7 +818,10 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) tegra_hdmi_setup_stereo_infoframe(hdmi);
/* TMDS CONFIG */ - if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { + if (of_device_is_compatible(node, "nvidia,tegra114-hdmi")) { + num_tmds = ARRAY_SIZE(tegra114_tmds_config); + tmds = tegra114_tmds_config; + } else if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { num_tmds = ARRAY_SIZE(tegra3_tmds_config); tmds = tegra3_tmds_config; } else { @@ -1299,6 +1394,7 @@ static int tegra_hdmi_remove(struct platform_device *pdev) static struct of_device_id tegra_hdmi_of_match[] = { { .compatible = "nvidia,tegra30-hdmi", }, { .compatible = "nvidia,tegra20-hdmi", }, + { .compatible = "nvidia,tegra114-hdmi", }, { }, };
diff --git a/drivers/gpu/host1x/drm/hdmi.h b/drivers/gpu/host1x/drm/hdmi.h index 52ac36e..37925c2 100644 --- a/drivers/gpu/host1x/drm/hdmi.h +++ b/drivers/gpu/host1x/drm/hdmi.h @@ -233,6 +233,10 @@ #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8) #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16) #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24) +#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0) +#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8) +#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16) +#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24) #define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
#define DRIVE_CURRENT_1_500_mA 0x00 @@ -299,6 +303,79 @@ #define DRIVE_CURRENT_24_375_mA 0x3d #define DRIVE_CURRENT_24_750_mA 0x3e
+#define DRIVE_CURRENT_0_000_mA_T114 0x00 +#define DRIVE_CURRENT_0_400_mA_T114 0x01 +#define DRIVE_CURRENT_0_800_mA_T114 0x02 +#define DRIVE_CURRENT_1_200_mA_T114 0x03 +#define DRIVE_CURRENT_1_600_mA_T114 0x04 +#define DRIVE_CURRENT_2_000_mA_T114 0x05 +#define DRIVE_CURRENT_2_400_mA_T114 0x06 +#define DRIVE_CURRENT_2_800_mA_T114 0x07 +#define DRIVE_CURRENT_3_200_mA_T114 0x08 +#define DRIVE_CURRENT_3_600_mA_T114 0x09 +#define DRIVE_CURRENT_4_000_mA_T114 0x0a +#define DRIVE_CURRENT_4_400_mA_T114 0x0b +#define DRIVE_CURRENT_4_800_mA_T114 0x0c +#define DRIVE_CURRENT_5_200_mA_T114 0x0d +#define DRIVE_CURRENT_5_600_mA_T114 0x0e +#define DRIVE_CURRENT_6_000_mA_T114 0x0f +#define DRIVE_CURRENT_6_400_mA_T114 0x10 +#define DRIVE_CURRENT_6_800_mA_T114 0x11 +#define DRIVE_CURRENT_7_200_mA_T114 0x12 +#define DRIVE_CURRENT_7_600_mA_T114 0x13 +#define DRIVE_CURRENT_8_000_mA_T114 0x14 +#define DRIVE_CURRENT_8_400_mA_T114 0x15 +#define DRIVE_CURRENT_8_800_mA_T114 0x16 +#define DRIVE_CURRENT_9_200_mA_T114 0x17 +#define DRIVE_CURRENT_9_600_mA_T114 0x18 +#define DRIVE_CURRENT_10_000_mA_T114 0x19 +#define DRIVE_CURRENT_10_400_mA_T114 0x1a +#define DRIVE_CURRENT_10_800_mA_T114 0x1b +#define DRIVE_CURRENT_11_200_mA_T114 0x1c +#define DRIVE_CURRENT_11_600_mA_T114 0x1d +#define DRIVE_CURRENT_12_000_mA_T114 0x1e +#define DRIVE_CURRENT_12_400_mA_T114 0x1f +#define DRIVE_CURRENT_12_800_mA_T114 0x20 +#define DRIVE_CURRENT_13_200_mA_T114 0x21 +#define DRIVE_CURRENT_13_600_mA_T114 0x22 +#define DRIVE_CURRENT_14_000_mA_T114 0x23 +#define DRIVE_CURRENT_14_400_mA_T114 0x24 +#define DRIVE_CURRENT_14_800_mA_T114 0x25 +#define DRIVE_CURRENT_15_200_mA_T114 0x26 +#define DRIVE_CURRENT_15_600_mA_T114 0x27 +#define DRIVE_CURRENT_16_000_mA_T114 0x28 +#define DRIVE_CURRENT_16_400_mA_T114 0x29 +#define DRIVE_CURRENT_16_800_mA_T114 0x2a +#define DRIVE_CURRENT_17_200_mA_T114 0x2b +#define DRIVE_CURRENT_17_600_mA_T114 0x2c +#define DRIVE_CURRENT_18_000_mA_T114 0x2d +#define DRIVE_CURRENT_18_400_mA_T114 0x2e +#define DRIVE_CURRENT_18_800_mA_T114 0x2f +#define DRIVE_CURRENT_19_200_mA_T114 0x30 +#define DRIVE_CURRENT_19_600_mA_T114 0x31 +#define DRIVE_CURRENT_20_000_mA_T114 0x32 +#define DRIVE_CURRENT_20_400_mA_T114 0x33 +#define DRIVE_CURRENT_20_800_mA_T114 0x34 +#define DRIVE_CURRENT_21_200_mA_T114 0x35 +#define DRIVE_CURRENT_21_600_mA_T114 0x36 +#define DRIVE_CURRENT_22_000_mA_T114 0x37 +#define DRIVE_CURRENT_22_400_mA_T114 0x38 +#define DRIVE_CURRENT_22_800_mA_T114 0x39 +#define DRIVE_CURRENT_23_200_mA_T114 0x3a +#define DRIVE_CURRENT_23_600_mA_T114 0x3b +#define DRIVE_CURRENT_24_000_mA_T114 0x3c +#define DRIVE_CURRENT_24_400_mA_T114 0x3d +#define DRIVE_CURRENT_24_800_mA_T114 0x3e +#define DRIVE_CURRENT_25_200_mA_T114 0x3f +#define DRIVE_CURRENT_25_400_mA_T114 0x40 +#define DRIVE_CURRENT_25_800_mA_T114 0x41 +#define DRIVE_CURRENT_26_200_mA_T114 0x42 +#define DRIVE_CURRENT_26_600_mA_T114 0x43 +#define DRIVE_CURRENT_27_000_mA_T114 0x44 +#define DRIVE_CURRENT_27_400_mA_T114 0x45 +#define DRIVE_CURRENT_27_800_mA_T114 0x46 +#define DRIVE_CURRENT_28_200_mA_T114 0x47 + #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80 #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81 @@ -358,6 +435,23 @@ #define PE_CURRENT_7_0_mA 0xe #define PE_CURRENT_7_5_mA 0xf
+#define PE_CURRENT_0_mA_T114 0x0 +#define PE_CURRENT_1_mA_T114 0x1 +#define PE_CURRENT_2_mA_T114 0x2 +#define PE_CURRENT_3_mA_T114 0x3 +#define PE_CURRENT_4_mA_T114 0x4 +#define PE_CURRENT_5_mA_T114 0x5 +#define PE_CURRENT_6_mA_T114 0x6 +#define PE_CURRENT_7_mA_T114 0x7 +#define PE_CURRENT_8_mA_T114 0x8 +#define PE_CURRENT_9_mA_T114 0x9 +#define PE_CURRENT_10_mA_T114 0xa +#define PE_CURRENT_11_mA_T114 0xb +#define PE_CURRENT_12_mA_T114 0xc +#define PE_CURRENT_13_mA_T114 0xd +#define PE_CURRENT_14_mA_T114 0xe +#define PE_CURRENT_15_mA_T114 0xf + #define HDMI_NV_PDISP_KEY_CTRL 0x9a #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c @@ -383,4 +477,62 @@ #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
+#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1 +#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0) +#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8) +#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16) +#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24) + +#define PEAK_CURRENT_0_000_mA 0x00 +#define PEAK_CURRENT_0_200_mA 0x01 +#define PEAK_CURRENT_0_400_mA 0x02 +#define PEAK_CURRENT_0_600_mA 0x03 +#define PEAK_CURRENT_0_800_mA 0x04 +#define PEAK_CURRENT_1_000_mA 0x05 +#define PEAK_CURRENT_1_200_mA 0x06 +#define PEAK_CURRENT_1_400_mA 0x07 +#define PEAK_CURRENT_1_600_mA 0x08 +#define PEAK_CURRENT_1_800_mA 0x09 +#define PEAK_CURRENT_2_000_mA 0x0a +#define PEAK_CURRENT_2_200_mA 0x0b +#define PEAK_CURRENT_2_400_mA 0x0c +#define PEAK_CURRENT_2_600_mA 0x0d +#define PEAK_CURRENT_2_800_mA 0x0e +#define PEAK_CURRENT_3_000_mA 0x0f +#define PEAK_CURRENT_3_200_mA 0x10 +#define PEAK_CURRENT_3_400_mA 0x11 +#define PEAK_CURRENT_3_600_mA 0x12 +#define PEAK_CURRENT_3_800_mA 0x13 +#define PEAK_CURRENT_4_000_mA 0x14 +#define PEAK_CURRENT_4_200_mA 0x15 +#define PEAK_CURRENT_4_400_mA 0x16 +#define PEAK_CURRENT_4_600_mA 0x17 +#define PEAK_CURRENT_4_800_mA 0x18 +#define PEAK_CURRENT_5_000_mA 0x19 +#define PEAK_CURRENT_5_200_mA 0x1a +#define PEAK_CURRENT_5_400_mA 0x1b +#define PEAK_CURRENT_5_600_mA 0x1c +#define PEAK_CURRENT_5_800_mA 0x1d +#define PEAK_CURRENT_6_000_mA 0x1e +#define PEAK_CURRENT_6_200_mA 0x1f +#define PEAK_CURRENT_6_400_mA 0x20 +#define PEAK_CURRENT_6_600_mA 0x21 +#define PEAK_CURRENT_6_800_mA 0x22 +#define PEAK_CURRENT_7_000_mA 0x23 +#define PEAK_CURRENT_7_200_mA 0x24 +#define PEAK_CURRENT_7_400_mA 0x25 +#define PEAK_CURRENT_7_600_mA 0x26 +#define PEAK_CURRENT_7_800_mA 0x27 +#define PEAK_CURRENT_8_000_mA 0x28 +#define PEAK_CURRENT_8_200_mA 0x29 +#define PEAK_CURRENT_8_400_mA 0x2a +#define PEAK_CURRENT_8_600_mA 0x2b +#define PEAK_CURRENT_8_800_mA 0x2c +#define PEAK_CURRENT_9_000_mA 0x2d +#define PEAK_CURRENT_9_200_mA 0x2e +#define PEAK_CURRENT_9_400_mA 0x2f + +#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2 +#define DRIVE_CURRENT_FUSE_OVERRIDE_T114 (1 << 31) + #endif /* TEGRA_HDMI_H */
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Add Tegra114 TMDS configuration, add new peak_current field and use new place for drive current override bit on Tegra114 platform.
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
static struct of_device_id host1x_of_match[] = {
- { .compatible = "nvidia,tegra114-host1x", .data = &host1x01_info, },
We should add that value to the host1x DT binding documentation.
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c
static const struct tegra_hdmi_audio_config * tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) { @@ -593,8 +673,20 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
- value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
- tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
- if (of_device_is_compatible(hdmi->dev->of_node,
"nvidia,tegra114-hdmi")) {
We shouldn't do this at run-time. Rather, set tegra_hdmi_of_match[]'s .data field to a structure that represents the various features of the HW, and then make this code conditional upon a feature flag in that structure.
On Wed, Sep 04, 2013 at 12:39:59PM -0600, Stephen Warren wrote:
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Add Tegra114 TMDS configuration, add new peak_current field and use new place for drive current override bit on Tegra114 platform.
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
static struct of_device_id host1x_of_match[] = {
- { .compatible = "nvidia,tegra114-host1x", .data = &host1x01_info, },
We should add that value to the host1x DT binding documentation.
That should be superseeded by a patch from my Tegra114 DSI series. Note that Tegra114 also uses a slightly updated version of host1x.
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c
static const struct tegra_hdmi_audio_config * tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) { @@ -593,8 +673,20 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
- value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
- tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
- if (of_device_is_compatible(hdmi->dev->of_node,
"nvidia,tegra114-hdmi")) {We shouldn't do this at run-time. Rather, set tegra_hdmi_of_match[]'s .data field to a structure that represents the various features of the HW, and then make this code conditional upon a feature flag in that structure.
I'll take a look at how this could be done. There are a few other places where we do this check at runtime, so that should be converted at the same time.
Thierry
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/gpu/host1x/drm/hdmi.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index d81fac8..140339b 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -702,6 +702,14 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) unsigned long value; int retries = 1000; int err; + struct drm_property_blob *edid_blob = output->connector.edid_blob_ptr; + + if (edid_blob && edid_blob->data && + drm_detect_hdmi_monitor((struct edid *)edid_blob->data)) { + hdmi->dvi = false; + } else { + hdmi->dvi = true; + }
pclk = mode->clock * 1000; h_sync_width = mode->hsync_end - mode->hsync_start;
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
This seems like a bug-fix that might even be worth CC: stable?
On Wed, Sep 04, 2013 at 12:40:58PM -0600, Stephen Warren wrote:
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Use EDID data to determine whether the display supports HDMI or just DVI. This used to be hardcoded to be HDMI, which broke support for DVI displays that couldn't understand the interspersed audio/other data.
If the EDID data isn't available, default to DVI, which should be a safer choice.
This seems like a bug-fix that might even be worth CC: stable?
Possibly. The patch reaches deeply into some DRM structures, which I'd like to avoid. I'll have another look to see if it can be done in a slightly different way.
Thierry
The Vdd regulator used to be enabled only at tegra_output_hdmi_enable, which is called after a sink is detected. However, the HDMI hotplug pin works by returning the voltage supplied by the Vdd pin, so this meant that the hotplug pin was never asserted and the sink was not detected unless the Vdd regulator was set to be always on.
This patch moves the enable to the tegra_hdmi_drm_init function to make sure the regulator will get enabled.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/gpu/host1x/drm/hdmi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index 140339b..96a6ae1 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -716,12 +716,6 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) h_back_porch = mode->htotal - mode->hsync_end; h_front_porch = mode->hsync_start - mode->hdisplay;
- err = regulator_enable(hdmi->vdd); - if (err < 0) { - dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); - return err; - } - err = regulator_enable(hdmi->pll); if (err < 0) { dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); @@ -943,7 +937,6 @@ static int tegra_output_hdmi_disable(struct tegra_output *output) tegra_periph_reset_assert(hdmi->clk); clk_disable(hdmi->clk); regulator_disable(hdmi->pll); - regulator_disable(hdmi->vdd);
return 0; } @@ -1240,6 +1233,12 @@ static int tegra_hdmi_drm_init(struct host1x_client *client, struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); int err;
+ err = regulator_enable(hdmi->vdd); + if (err < 0) { + dev_err(client->dev, "vdd regulator enable failed: %d\n", err); + return err; + } + hdmi->output.type = TEGRA_OUTPUT_HDMI; hdmi->output.dev = client->dev; hdmi->output.ops = &hdmi_ops; @@ -1283,6 +1282,8 @@ static int tegra_hdmi_drm_exit(struct host1x_client *client) return err; }
+ regulator_disable(hdmi->vdd); + return 0; }
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
The Vdd regulator used to be enabled only at tegra_output_hdmi_enable, which is called after a sink is detected. However, the HDMI hotplug pin works by returning the voltage supplied by the Vdd pin, so this meant that the hotplug pin was never asserted and the sink was not detected unless the Vdd regulator was set to be always on.
This patch moves the enable to the tegra_hdmi_drm_init function to make sure the regulator will get enabled.
The DT binding document isn't very clear on this topic (and should be fixed): What is this regulator intended to control? If this regulator solely controls the supply to the hotplug detection circuit, this change makes sense. If the regulator mainly supplies something else (e.g. part of the HDMI core on the Tegra chip), then perhaps this change isn't correct. The correct approach might be to introduce another (optional) regulator specifically for the hotplug circuit. Presumably both DT properties vdd-supply and hotplug-supply could point at the same regulator if that's the way the HW was wired up.
On 09/04/2013 09:44 PM, Stephen Warren wrote:
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
The Vdd regulator used to be enabled only at tegra_output_hdmi_enable, which is called after a sink is detected. However, the HDMI hotplug pin works by returning the voltage supplied by the Vdd pin, so this meant that the hotplug pin was never asserted and the sink was not detected unless the Vdd regulator was set to be always on.
This patch moves the enable to the tegra_hdmi_drm_init function to make sure the regulator will get enabled.
The DT binding document isn't very clear on this topic (and should be fixed): What is this regulator intended to control? If this regulator solely controls the supply to the hotplug detection circuit, this change makes sense. If the regulator mainly supplies something else (e.g. part of the HDMI core on the Tegra chip), then perhaps this change isn't correct. The correct approach might be to introduce another (optional) regulator specifically for the hotplug circuit. Presumably both DT properties vdd-supply and hotplug-supply could point at the same regulator if that's the way the HW was wired up. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
AFAICT, it controls the Vdd pin on the HDMI port, so it just affects the hotplug pin and the DDC I2C bus power.
On 09/04/2013 04:03 PM, Mikko Perttunen wrote:
On 09/04/2013 09:44 PM, Stephen Warren wrote:
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
The Vdd regulator used to be enabled only at tegra_output_hdmi_enable, which is called after a sink is detected. However, the HDMI hotplug pin works by returning the voltage supplied by the Vdd pin, so this meant that the hotplug pin was never asserted and the sink was not detected unless the Vdd regulator was set to be always on.
This patch moves the enable to the tegra_hdmi_drm_init function to make sure the regulator will get enabled.
The DT binding document isn't very clear on this topic (and should be fixed): What is this regulator intended to control? If this regulator solely controls the supply to the hotplug detection circuit, this change makes sense. If the regulator mainly supplies something else (e.g. part of the HDMI core on the Tegra chip), then perhaps this change isn't correct. The correct approach might be to introduce another (optional) regulator specifically for the hotplug circuit. Presumably both DT properties vdd-supply and hotplug-supply could point at the same regulator if that's the way the HW was wired up. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
AFAICT, it controls the Vdd pin on the HDMI port, so it just affects the hotplug pin and the DDC I2C bus power.
Ah OK, then this code change makes sense. It'd be useful to put what you just wrote into the binding doc.
Add host1x, disp1 and disp2 clocks to the clock initialization table. These clocks are required for HDMI support.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- drivers/clk/tegra/clk-tegra114.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index cd94b0c..a491dea 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2211,6 +2211,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { {i2s4, pll_a_out0, 11289600, 0}, {dfll_soc, pll_p, 51000000, 1}, {dfll_ref, pll_p, 51000000, 1}, + {host1x, pll_c, 150000000, 0}, + {disp1, pll_p, 600000000, 0}, + {disp2, pll_p, 600000000, 0}, {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ };
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Add host1x, disp1 and disp2 clocks to the clock initialization table. These clocks are required for HDMI support.
This patch should be sent to Mike Turquette so it can be taken through the clock tree.
Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- arch/arm/boot/dts/tegra114.dtsi | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2905145..088b594 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -27,6 +27,48 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
+ host1x { + compatible = "nvidia,tegra114-host1x", "simple-bus"; + reg = <0x50000000 0x00028000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + + dc@54200000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc"; + reg = <0x54200000 0x00040000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "disp1", "parent"; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra30-dc"; + reg = <0x54240000 0x00040000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "disp2", "parent"; + }; + + hdmi { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + + status = "disabled"; + }; + }; + timer@60005000 { compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>;
On 08/28/2013 09:48 AM, Mikko Perttunen wrote:
Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree.
Patches 5 and 6 should be sent separately to the Tegra maintainer (me) to be taken through the Tegra tree.
Add HDMI node to Dalmore device tree to supply Dalmore-specific data: VDD and PLL regulators for HDMI port, DDC bus and HDMI cable hotplug GPIO.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com --- arch/arm/boot/dts/tegra114-dalmore.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 6023028..f979e74 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -713,6 +713,19 @@ }; };
+ host1x { + hdmi { + status = "okay"; + + vdd-supply = <&vdd_hdmi_reg>; + pll-supply = <&palmas_smps3_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + serial@70006300 { status = "okay"; }; @@ -740,6 +753,10 @@ }; };
+ hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>;
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Mikko Perttunen -
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Thierry Reding