This is an SMMU for the adreno gpu, and adding this compatible lets the driver use per-fd page tables, which are required for security between GPU clients.

Signed-off-by: Emma Anholt emma@anholt.net ---

Tested with a full deqp-vk run on RB5, which did involve some iommu faults.

arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a92230bec1dd..483c0e0f1d1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { };

adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>;

On Wed, 15 Jun 2022 at 02:01, Emma Anholt emma@anholt.net wrote:

Required for turning on per-process page tables for the GPU.

Signed-off-by: Emma Anholt emma@anholt.net

Reviewed-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org

---

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index d8e1ef83c01b..bb9220937068 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -233,6 +233,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc7280-mss-pil" }, { .compatible = "qcom,sc8180x-mdss" },

•   { .compatible = "qcom,sm8250-mdss" },
    { .compatible = "qcom,sdm845-mdss" },
    { .compatible = "qcom,sdm845-mss-pil" },
    { }
  

-- 2.36.1