Much of the code in Exynos DRM subsystem is generic enough to use it for older (non-Exynos) Samsung SoCs as well, after minor modifications.
This series starts adding support for previous SoCs to Exynos DRM by introducing S3C64xx support to exynos_drm_fimd driver.
Adding support for remaining SoCs between S3C64xx and Exynos4 (S5PC100, S5P64x0 and S5PV210) should be rather straightforward, but at the moment I can test only on S3C6410, so I limited my changes only to this SoC.
On Tiny6410 (Mini6410-compatible) board based on Samsung S3C6410 SoC, using my to-be-resubmitted patches for Device Tree support:
Tested-by: Tomasz Figa tomasz.figa@gmail.com
Tomasz Figa (4): drm/exynos: fimd: Hold pointer to driver data in context struct drm/exynos: fimd: Add support for FIMD versions without SHADOWCON register drm/exynos: fimd: Add support for FIMD variants with clock selection drm/exynos: fimd: Add support for S3C64xx SoCs
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 90 ++++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 22 deletions(-)
This patch adds pointer to driver data to fimd_context structure, to remove the need to call drm_fimd_get_driver_data() each time access to driver data is necessary.
Signed-off-by: Tomasz Figa tomasz.figa@gmail.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 746b282..264434f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -107,6 +107,7 @@ struct fimd_context { atomic_t wait_vsync_event;
struct exynos_drm_panel_info *panel; + struct fimd_driver_data *driver_data; };
#ifdef CONFIG_OF @@ -239,10 +240,9 @@ static void fimd_commit(struct device *dev) struct exynos_drm_panel_info *panel = ctx->panel; struct fb_videomode *timing = &panel->timing; struct fimd_driver_data *driver_data; - struct platform_device *pdev = to_platform_device(dev); u32 val;
- driver_data = drm_fimd_get_driver_data(pdev); + driver_data = ctx->driver_data; if (ctx->suspended) return;
@@ -949,6 +949,7 @@ static int fimd_probe(struct platform_device *pdev) return ret; }
+ ctx->driver_data = drm_fimd_get_driver_data(pdev); ctx->vidcon0 = pdata->vidcon0; ctx->vidcon1 = pdata->vidcon1; ctx->default_win = pdata->default_win;
Some platforms that can be supported with this driver have PRTCON register instead of SHADOWCON, which requires slightly different handling.
This patch factors out all register shadow control code from the driver and adds a function to control register shadowing appropriately, depending on driver data.
Signed-off-by: Tomasz Figa tomasz.figa@gmail.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 69 +++++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 264434f..a5559f6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -63,14 +63,18 @@
struct fimd_driver_data { unsigned int timing_base; + + unsigned int has_shadowcon:1; };
static struct fimd_driver_data exynos4_fimd_driver_data = { .timing_base = 0x0, + .has_shadowcon = 1, };
static struct fimd_driver_data exynos5_fimd_driver_data = { .timing_base = 0x20000, + .has_shadowcon = 1, };
struct fimd_win_data { @@ -489,6 +493,33 @@ static void fimd_win_set_colkey(struct device *dev, unsigned int win) writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); }
+/** + * shadow_protect_win() - disable updating values from shadow registers at vsync + * + * @win: window to protect registers for + * @protect: 1 to protect (disable updates) + */ +static void fimd_shadow_protect_win(struct fimd_context *ctx, + int win, bool protect) +{ + u32 reg, bits, val; + + if (ctx->driver_data->has_shadowcon) { + reg = SHADOWCON; + bits = SHADOWCON_WINx_PROTECT(win); + } else { + reg = PRTCON; + bits = PRTCON_PROTECT; + } + + val = readl(ctx->regs + reg); + if (protect) + val |= bits; + else + val &= ~bits; + writel(val, ctx->regs + reg); +} + static void fimd_win_commit(struct device *dev, int zpos) { struct fimd_context *ctx = get_fimd_context(dev); @@ -512,7 +543,7 @@ static void fimd_win_commit(struct device *dev, int zpos) win_data = &ctx->win_data[win];
/* - * SHADOWCON register is used for enabling timing. + * SHADOWCON/PRTCON register is used for enabling timing. * * for example, once only width value of a register is set, * if the dma is started then fimd hardware could malfunction so @@ -522,9 +553,7 @@ static void fimd_win_commit(struct device *dev, int zpos) */
/* protect windows */ - val = readl(ctx->regs + SHADOWCON); - val |= SHADOWCON_WINx_PROTECT(win); - writel(val, ctx->regs + SHADOWCON); + fimd_shadow_protect_win(ctx, win, true);
/* buffer start address */ val = (unsigned long)win_data->dma_addr; @@ -602,10 +631,13 @@ static void fimd_win_commit(struct device *dev, int zpos) writel(val, ctx->regs + WINCON(win));
/* Enable DMA channel and unprotect windows */ - val = readl(ctx->regs + SHADOWCON); - val |= SHADOWCON_CHx_ENABLE(win); - val &= ~SHADOWCON_WINx_PROTECT(win); - writel(val, ctx->regs + SHADOWCON); + fimd_shadow_protect_win(ctx, win, false); + + if (ctx->driver_data->has_shadowcon) { + val = readl(ctx->regs + SHADOWCON); + val |= SHADOWCON_CHx_ENABLE(win); + writel(val, ctx->regs + SHADOWCON); + }
win_data->enabled = true; } @@ -634,9 +666,7 @@ static void fimd_win_disable(struct device *dev, int zpos) }
/* protect windows */ - val = readl(ctx->regs + SHADOWCON); - val |= SHADOWCON_WINx_PROTECT(win); - writel(val, ctx->regs + SHADOWCON); + fimd_shadow_protect_win(ctx, win, true);
/* wincon */ val = readl(ctx->regs + WINCON(win)); @@ -644,10 +674,13 @@ static void fimd_win_disable(struct device *dev, int zpos) writel(val, ctx->regs + WINCON(win));
/* unprotect windows */ - val = readl(ctx->regs + SHADOWCON); - val &= ~SHADOWCON_CHx_ENABLE(win); - val &= ~SHADOWCON_WINx_PROTECT(win); - writel(val, ctx->regs + SHADOWCON); + if (ctx->driver_data->has_shadowcon) { + val = readl(ctx->regs + SHADOWCON); + val &= ~SHADOWCON_CHx_ENABLE(win); + writel(val, ctx->regs + SHADOWCON); + } + + fimd_shadow_protect_win(ctx, win, false);
win_data->enabled = false; } @@ -777,8 +810,6 @@ static int fimd_calc_clkdiv(struct fimd_context *ctx,
static void fimd_clear_win(struct fimd_context *ctx, int win) { - u32 val; - DRM_DEBUG_KMS("%s\n", __FILE__);
writel(0, ctx->regs + WINCON(win)); @@ -789,9 +820,7 @@ static void fimd_clear_win(struct fimd_context *ctx, int win) if (win == 1 || win == 2) writel(0, ctx->regs + VIDOSD_D(win));
- val = readl(ctx->regs + SHADOWCON); - val &= ~SHADOWCON_WINx_PROTECT(win); - writel(val, ctx->regs + SHADOWCON); + fimd_shadow_protect_win(ctx, win, false); }
static int fimd_clock(struct fimd_context *ctx, bool enable)
Some platforms that can be supported this driver has additional clock source selection bits in VIDCON0 register that allows to select which clock should be used to drive the pixel clock: bus clock or special clock.
Since this driver assumes that special clock always drives the pixel clock, this patch sets the selection bitfield to use the special clock.
Signed-off-by: Tomasz Figa tomasz.figa@gmail.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index a5559f6..a2e385d 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -65,6 +65,7 @@ struct fimd_driver_data { unsigned int timing_base;
unsigned int has_shadowcon:1; + unsigned int has_clksel:1; };
static struct fimd_driver_data exynos4_fimd_driver_data = { @@ -278,6 +279,11 @@ static void fimd_commit(struct device *dev) val = ctx->vidcon0; val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+ if (ctx->driver_data->has_clksel) { + val &= ~VIDCON0_CLKSEL_MASK; + val |= VIDCON0_CLKSEL_LCD; + } + if (ctx->clkdiv > 1) val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; else
The FIMD block present on S3C6400/S3C6410 SoCs is compatible with this driver, so it can be supported by it as well.
This patch adds appropriate device IDs and driver data to enable this driver for S3C64xx SoCs.
Signed-off-by: Tomasz Figa tomasz.figa@gmail.com --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index a2e385d..a1669d4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -68,6 +68,11 @@ struct fimd_driver_data { unsigned int has_clksel:1; };
+static struct fimd_driver_data s3c64xx_fimd_driver_data = { + .timing_base = 0x0, + .has_clksel = 1, +}; + static struct fimd_driver_data exynos4_fimd_driver_data = { .timing_base = 0x0, .has_shadowcon = 1, @@ -117,6 +122,8 @@ struct fimd_context {
#ifdef CONFIG_OF static const struct of_device_id fimd_driver_dt_match[] = { + { .compatible = "samsung,s3c6400-fimd", + .data = &s3c64xx_fimd_driver_data }, { .compatible = "samsung,exynos4210-fimd", .data = &exynos4_fimd_driver_data }, { .compatible = "samsung,exynos5250-fimd", @@ -1108,6 +1115,9 @@ static int fimd_runtime_resume(struct device *dev)
static struct platform_device_id fimd_driver_ids[] = { { + .name = "s3c64xx-fb", + .driver_data = (unsigned long)&s3c64xx_fimd_driver_data, + }, { .name = "exynos4-fb", .driver_data = (unsigned long)&exynos4_fimd_driver_data, }, {
Hi,
On Wednesday 01 of May 2013 21:02:25 Tomasz Figa wrote:
Much of the code in Exynos DRM subsystem is generic enough to use it for older (non-Exynos) Samsung SoCs as well, after minor modifications.
This series starts adding support for previous SoCs to Exynos DRM by introducing S3C64xx support to exynos_drm_fimd driver.
Adding support for remaining SoCs between S3C64xx and Exynos4 (S5PC100, S5P64x0 and S5PV210) should be rather straightforward, but at the moment I can test only on S3C6410, so I limited my changes only to this SoC.
On Tiny6410 (Mini6410-compatible) board based on Samsung S3C6410 SoC, using my to-be-resubmitted patches for Device Tree support:
Tested-by: Tomasz Figa tomasz.figa@gmail.com
Tomasz Figa (4): drm/exynos: fimd: Hold pointer to driver data in context struct drm/exynos: fimd: Add support for FIMD versions without SHADOWCON register drm/exynos: fimd: Add support for FIMD variants with clock selection drm/exynos: fimd: Add support for S3C64xx SoCs
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 90 ++++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 22 deletions(-)
Any comments for this series?
Best regards, Tomasz
On Sunday 19 of May 2013 13:26:57 Tomasz Figa wrote:
Hi,
On Wednesday 01 of May 2013 21:02:25 Tomasz Figa wrote:
Much of the code in Exynos DRM subsystem is generic enough to use it for older (non-Exynos) Samsung SoCs as well, after minor modifications.
This series starts adding support for previous SoCs to Exynos DRM by introducing S3C64xx support to exynos_drm_fimd driver.
Adding support for remaining SoCs between S3C64xx and Exynos4 (S5PC100, S5P64x0 and S5PV210) should be rather straightforward, but at the moment I can test only on S3C6410, so I limited my changes only to this SoC.
On Tiny6410 (Mini6410-compatible) board based on Samsung S3C6410 SoC, using my to-be-resubmitted patches for Device Tree support:
Tested-by: Tomasz Figa tomasz.figa@gmail.com
Tomasz Figa (4): drm/exynos: fimd: Hold pointer to driver data in context struct drm/exynos: fimd: Add support for FIMD versions without SHADOWCON
registerdrm/exynos: fimd: Add support for FIMD variants with clock selection drm/exynos: fimd: Add support for S3C64xx SoCs
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 90
++++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 22 deletions(-)
Any comments for this series?
Best regards, Tomasz
Ping.
Best regards, Tomasz
On 06/06/2013 03:14 AM, Tomasz Figa wrote:
On Sunday 19 of May 2013 13:26:57 Tomasz Figa wrote:
Hi,
On Wednesday 01 of May 2013 21:02:25 Tomasz Figa wrote:
Much of the code in Exynos DRM subsystem is generic enough to use it for older (non-Exynos) Samsung SoCs as well, after minor modifications.
This series starts adding support for previous SoCs to Exynos DRM by introducing S3C64xx support to exynos_drm_fimd driver.
Adding support for remaining SoCs between S3C64xx and Exynos4 (S5PC100, S5P64x0 and S5PV210) should be rather straightforward, but at the moment I can test only on S3C6410, so I limited my changes only to this SoC.
On Tiny6410 (Mini6410-compatible) board based on Samsung S3C6410 SoC, using my to-be-resubmitted patches for Device Tree support:
Tested-by: Tomasz Figa tomasz.figa@gmail.com
Tomasz Figa (4): drm/exynos: fimd: Hold pointer to driver data in context struct drm/exynos: fimd: Add support for FIMD versions without SHADOWCON
registerdrm/exynos: fimd: Add support for FIMD variants with clock selection drm/exynos: fimd: Add support for S3C64xx SoCs
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 90
++++++++++++++++++++++++-------- 1 file changed, 68 insertions(+), 22 deletions(-)
Any comments for this series?
Best regards, Tomasz
Ping.
Best regards, Tomasz
This series looks good to me.
Acked-by: Joonyoung Shim jy0922.shim@samsung.com
Applied.
Thanks, Inki Dae
2013/6/6 Joonyoung Shim jy0922.shim@samsung.com
On 06/06/2013 03:14 AM, Tomasz Figa wrote:
On Sunday 19 of May 2013 13:26:57 Tomasz Figa wrote:
Hi,
On Wednesday 01 of May 2013 21:02:25 Tomasz Figa wrote:
Much of the code in Exynos DRM subsystem is generic enough to use it for older (non-Exynos) Samsung SoCs as well, after minor modifications.
This series starts adding support for previous SoCs to Exynos DRM by introducing S3C64xx support to exynos_drm_fimd driver.
Adding support for remaining SoCs between S3C64xx and Exynos4 (S5PC100, S5P64x0 and S5PV210) should be rather straightforward, but at the moment I can test only on S3C6410, so I limited my changes only to this SoC.
On Tiny6410 (Mini6410-compatible) board based on Samsung S3C6410 SoC, using my to-be-resubmitted patches for Device Tree support:
Tested-by: Tomasz Figa tomasz.figa@gmail.com
Tomasz Figa (4): drm/exynos: fimd: Hold pointer to driver data in context struct drm/exynos: fimd: Add support for FIMD versions without SHADOWCON register drm/exynos: fimd: Add support for FIMD variants with clock selection drm/exynos: fimd: Add support for S3C64xx SoCs drivers/gpu/drm/exynos/exynos_**drm_fimd.c | 90
++++++++++++++++++++++++------**-- 1 file changed, 68 insertions(+), 22 deletions(-)
Any comments for this series?
Best regards, Tomasz
Ping.
Best regards, Tomasz
This series looks good to me.
Acked-by: Joonyoung Shim jy0922.shim@samsung.com
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