Hi Laurent,
Thanks for the reply.
On 17 December 2012 20:55, Laurent Pinchart <
laurent.pinchart(a)ideasonboard.com> wrote:
> Hi Vikas,
>
> Sorry for the late reply. I now have more time to work on CDF, so delays
> should be much shorter.
>
> On Thursday 06 December 2012 10:51:15 Vikas Sajjan wrote:
> > Hi Laurent,
> >
> > I was thinking of porting CDF to samsung EXYNOS 5250 platform, what I
> found
> > is that, the exynos display controller …
[View More]is MIPI DSI based controller.
> >
> > But if I look at CDF patches, it has only support for MIPI DBI based
> Display
> > controller.
> >
> > So my question is, do we have any generic framework for MIPI DSI based
> > display controller? basically I wanted to know, how to go about porting
> CDF
> > for such kind of display controller.
>
> MIPI DSI support is not available yet. The only reason for that is that I
> don't have any MIPI DSI hardware to write and test the code with :-)
>
> The common display framework should definitely support MIPI DSI. I think
> the
> existing MIPI DBI code could be used as a base, so the implementation
> shouldn't be too high.
>
> Yeah, i was also thinking in similar lines, below is my though for MIPI
DSI support in CDF.
o MIPI DSI support as part of CDF framework will expose
§ mipi_dsi_register_device(mpi_device) (will be called mach-xxx-dt.c file )
§ mipi_dsi_register_driver(mipi_driver, bus ops) (will be called from
platform specific init driver call )
· bus ops will be
o read data
o write data
o write command
§ MIPI DSI will be registered as bus_register()
When MIPI DSI probe is called, it (e.g., Exynos or OMAP MIPI DSI) will
initialize the MIPI DSI HW IP.
This probe will also parse the DT file for MIPI DSI based panel, add
the panel device (device_add() ) to kernel and register the display
entity with its control and video ops with CDF.
I can give this a try. Does the existing Exynos 5250 driver support MIPI
> DSI ?
> Is the device documentation publicly available ? Can you point me to a MIPI
> DSI panel with public documentation (preferably with an existing mainline
> driver if possible) ?
>
> yeah, existing Exynos 5250 driver support MIPI DSI ass well as eDP.
i think device documentation is NOT available publicly.
--
> Regards,
>
> Laurent Pinchart
>
> --
Thanks and Regards
Vikas Sajjan
[View Less]
https://bugs.freedesktop.org/show_bug.cgi?id=46006
Bug #: 46006
Summary: [r300g, bisected] piglit glsl-max-varyings fails
Classification: Unclassified
Product: Mesa
Version: git
Platform: Other
OS/Version: All
Status: NEW
Keywords: regression
Severity: normal
Priority: medium
Component: Drivers/Gallium/r300
AssignedTo: dri-devel(a)lists.freedesktop.org
…
[View More]ReportedBy: pavel.ondracka(a)email.cz
CC: maraeo(a)gmail.com
This is the last r300g piglit regression from 7.11 to 8.0. I'm not sure if this is a valid bug, there is lots of errors:
r300: ERROR: FS input generic 20 unassigned, not enough hardware slots (it's not a bug, do not report it).
r300: ERROR: FS input generic 21 unassigned, not enough hardware slots (it's not a bug, do not report it).
However since this is a regression I'm reporting it nevertheless. May also be related to bug 34201
Output:
Vertical axis: Increasing numbers of varyings.
Horizontal axis: Which of the varyings contains the color.
GL_MAX_VARYING_FLOATS = 40
Probe at (8,98)
Expected: 0.000000 1.000000 0.000000
Observed: 0.000000 0.000000 0.000000
Failure with 9 vec4 varyings used in varying index 0
Probe at (8,110)
Expected: 0.000000 1.000000 0.000000
Observed: 0.000000 0.000000 0.000000
Failure with 10 vec4 varyings used in varying index 0
1ded658ce074a85bc08c989ff17840b840ff3051 is the first bad commit
commit 1ded658ce074a85bc08c989ff17840b840ff3051
Author: Marek Olšák <maraeo(a)gmail.com>
Date: Tue Nov 22 15:05:29 2011 +0100
st/mesa: add color varyings to MaxVarying
The linker now adds color varyings to the number of used varyings and checks
against that limit.
NOTE: This is a candidate for the 7.11 branch.
GPU: RV530
Mesa: df1cd55ebf362948788c04d2fa7da55c80991605
Kernel: 3.2.3
Libdrm: 2.4.31
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Hi Linus,
this one fixes a sleep while locked regression that was introduced earlier
in 3.8.
Dave.
The following changes since commit 6bacaa9ddacb71c691d32c678d37bc59ffc71fac:
Merge tag 'sound-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound (2013-02-07 08:43:30 +1100)
are available in the git repository at:
git://people.freedesktop.org/~airlied/linux drm-fixes
for you to fetch changes up to ff7c60c580d9722f820d85c9c58ca55ecc1ee7c4:
drm/ttm: fix fence locking in …
[View More]ttm_buffer_object_transfer, 2nd try (2013-02-08 10:44:31 +1000)
----------------------------------------------------------------
Daniel Vetter (1):
drm/ttm: fix fence locking in ttm_buffer_object_transfer, 2nd try
drivers/gpu/drm/ttm/ttm_bo_util.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
[View Less]
https://bugs.freedesktop.org/show_bug.cgi?id=60347
Priority: medium
Bug ID: 60347
Assignee: dri-devel(a)lists.freedesktop.org
Summary: Reproducible GPU lockup CP stall in Amnesia game
Severity: normal
Classification: Unclassified
OS: Linux (All)
Reporter: anonymous(a)dodgeit.com
Hardware: x86-64 (AMD64)
Status: NEW
Version: git
Component: Drivers/Gallium/r600
…
[View More]Product: Mesa
There is/are a reproducible GPU lockup in Amnesia: Dark Descent video game on
Linux x86-64. Often it occurs when looking at certain doors in the levels. I
find that using VT-switch helps to recover the GPU in a reasonable timeframe to
a somewhat usable state. I do experience some jerkiness though after the stall
recovery.
Radeon 6750M
3.8.0-rc5
Everything else taken from xorg-edgers ppa
I'm happy to investigate this issue further.
[ 9902.661056] radeon 0000:01:00.0: GPU lockup CP stall for more than 10000msec
[ 9902.661059] radeon 0000:01:00.0: GPU lockup (waiting for 0x0000000000049060)
[ 9902.661062] radeon 0000:01:00.0: failed to get a new IB (-35)
[ 9902.661063] [drm:radeon_cs_ib_chunk] *ERROR* Failed to get ib !
[ 9902.662124] radeon 0000:01:00.0: Saved 10007 dwords of commands on ring 0.
[ 9902.662127] radeon 0000:01:00.0: GPU softreset: 0x00000003
[ 9902.673782] radeon 0000:01:00.0: GRBM_STATUS = 0xA7732CA4
[ 9902.673784] radeon 0000:01:00.0: GRBM_STATUS_SE0 = 0x7C000005
[ 9902.673786] radeon 0000:01:00.0: GRBM_STATUS_SE1 = 0x00000007
[ 9902.673787] radeon 0000:01:00.0: SRBM_STATUS = 0x200000C0
[ 9902.673789] radeon 0000:01:00.0: R_008674_CP_STALLED_STAT1 = 0x04000000
[ 9902.673791] radeon 0000:01:00.0: R_008678_CP_STALLED_STAT2 = 0x000C0000
[ 9902.673793] radeon 0000:01:00.0: R_00867C_CP_BUSY_STAT = 0x00048402
[ 9902.673794] radeon 0000:01:00.0: R_008680_CP_STAT = 0x80860243
[ 9902.673796] radeon 0000:01:00.0: GRBM_SOFT_RESET=0x00007F6B
[ 9902.673848] radeon 0000:01:00.0: GRBM_STATUS = 0x00003828
[ 9902.673850] radeon 0000:01:00.0: GRBM_STATUS_SE0 = 0x00000007
[ 9902.673851] radeon 0000:01:00.0: GRBM_STATUS_SE1 = 0x00000007
[ 9902.673853] radeon 0000:01:00.0: SRBM_STATUS = 0x200000C0
[ 9902.673855] radeon 0000:01:00.0: R_008674_CP_STALLED_STAT1 = 0x00000000
[ 9902.673857] radeon 0000:01:00.0: R_008678_CP_STALLED_STAT2 = 0x00000000
[ 9902.673858] radeon 0000:01:00.0: R_00867C_CP_BUSY_STAT = 0x00000000
[ 9902.673860] radeon 0000:01:00.0: R_008680_CP_STAT = 0x00000000
[ 9902.691442] radeon 0000:01:00.0: GPU reset succeeded, trying to resume
[ 9902.709761] [drm] probing gen 2 caps for device 8086:101 = 2/0
[ 9902.709765] [drm] PCIE gen 2 link speeds already enabled
[ 9902.711799] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
[ 9902.711901] radeon 0000:01:00.0: WB enabled
[ 9902.711904] radeon 0000:01:00.0: fence driver on ring 0 use gpu addr
0x0000000040000c00 and cpu addr 0xffff880451db8c00
[ 9902.711905] radeon 0000:01:00.0: fence driver on ring 3 use gpu addr
0x0000000040000c0c and cpu addr 0xffff880451db8c0c
[ 9902.728078] [drm] ring test on 0 succeeded in 3 usecs
[ 9902.728142] [drm] ring test on 3 succeeded in 1 usecs
[ 9902.777649] [drm] ib test on ring 0 succeeded in 0 usecs
[ 9902.777738] [drm] ib test on ring 3 succeeded in 1 usecs
[ 9914.739076] [drm] Forcing lvds to dual link mode on Apple MacBook Pro (Core
i5/i7 Series)
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From: Alex Deucher <alexander.deucher(a)amd.com>
Hi Dave,
This is the first drm-next pull for 3.9 for radeon. Highlights:
- CS ioctl cleanup and unification. Unification of a lot of functionality
that was duplicated across multiple generates of hardware.
- Add support for Oland GPUs
- Deprecate UMS support. Mesa and the ddx dropped support for UMS and
apparently very few people still use it since the UMS CS ioctl was broken
for several kernels and no one reported it. It was fixed …
[View More]in 3.8/stable.
- Rework GPU reset. Use the status registers to determine what blocks
to reset. This better matches the recommended reset programming model.
This also allows us to properly reset blocks besides GFX and DMA.
- Switch the VM set page code to use an IB rather than the ring. This
fixes overflow issues when doing large page table updates using a small
ring like DMA.
- Several small cleanups and bug fixes.
The following changes since commit 3646e4209f2bd0d09022ed792e594fb4f559b86c:
drm/radeon: switch back to the CP ring for VM PT updates (2013-01-31 16:19:19 -0500)
are available in the git repository at:
git://people.freedesktop.org/~agd5f/linux drm-next-3.9
Alex Deucher (24):
drm/radeon: add additional reset flags
drm/radeon: add a bios scratch asic hung helper
drm/radeon: rework GPU reset on r6xx/r7xx
drm/radeon: rework GPU reset on evergreen
drm/radeon: rework GPU reset on cayman/TN
drm/radeon: rework GPU reset on cayman/TN
drm/radeon: use status regs to determine what to reset (6xx/7xx)
drm/radeon: use status regs to determine what to reset (evergreen)
drm/radeon: use status regs to determine what to reset (cayman)
drm/radeon: use status regs to determine what to reset (si)
drm/radeon: halt engines before disabling MC (6xx/7xx)
drm/radeon: halt engines before disabling MC (evergreen)
drm/radeon: halt engines before disabling MC (cayman/TN)
drm/radeon: halt engines before disabling MC (si)
drm/radeon: use the reset mask to determine if rings are hung
drm/radeon: don't reset the MC on IGPs/APUs
drm/radeon: use IBs for VM page table updates v2
drm/radeon: switch back to using the DMA ring for VM PT updates
drm/radeon: add Oland chip family
drm/radeon: fill in gpu init for Oland
drm/radeon: add ucode loading support for Oland
drm/radeon: radeon-asic updates for Oland
drm/radeon: add Oland pci ids
drm/radeon/dce6: fix display powergating
Christian König (1):
drm/radeon: Deprecate UMS support v2
Ilija Hadzic (12):
drm/radeon: remove unecessary assignment
drm/radeon: remove unused prototype from radeon_cs
drm/radeon: fix formatting
drm/radeon: implement common cs packet parse function
drm/radeon: use common cs packet parse function
drm/radeon: factor out cs_next_is_pkt3_nop function
drm/radeon: refactor vline packet parsing function
drm/radeon: add a check to wait_reg_mem command
drm/radeon: rename r100_cs_dump_packet to radeon_cs_dump_packet
drm/radeon: pull out common next_reloc function
drm/radeon: use common next_reloc function
drm/radeon: consolidate redundant macros and constants
Jerome Glisse (1):
radeon/kms: cleanup async dma packet checking
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/radeon/Kconfig | 33 +-
drivers/gpu/drm/radeon/Makefile | 10 +-
drivers/gpu/drm/radeon/atombios_crtc.c | 6 +-
drivers/gpu/drm/radeon/evergreen.c | 353 +++++++---
drivers/gpu/drm/radeon/evergreen_cs.c | 1149 +++++++++++++-------------------
drivers/gpu/drm/radeon/evergreen_reg.h | 1 +
drivers/gpu/drm/radeon/evergreend.h | 54 +-
drivers/gpu/drm/radeon/ni.c | 339 ++++++----
drivers/gpu/drm/radeon/nid.h | 27 +-
drivers/gpu/drm/radeon/r100.c | 224 ++-----
drivers/gpu/drm/radeon/r100_track.h | 4 -
drivers/gpu/drm/radeon/r100d.h | 11 -
drivers/gpu/drm/radeon/r200.c | 26 +-
drivers/gpu/drm/radeon/r300.c | 42 +-
drivers/gpu/drm/radeon/r300_cmdbuf.c | 2 +
drivers/gpu/drm/radeon/r300d.h | 11 -
drivers/gpu/drm/radeon/r500_reg.h | 1 +
drivers/gpu/drm/radeon/r600.c | 384 +++++++----
drivers/gpu/drm/radeon/r600_blit.c | 33 +-
drivers/gpu/drm/radeon/r600_blit_kms.c | 31 +
drivers/gpu/drm/radeon/r600_cp.c | 2 +
drivers/gpu/drm/radeon/r600_cs.c | 332 +++-------
drivers/gpu/drm/radeon/r600d.h | 17 +-
drivers/gpu/drm/radeon/radeon.h | 31 +-
drivers/gpu/drm/radeon/radeon_asic.c | 52 +-
drivers/gpu/drm/radeon/radeon_asic.h | 17 +-
drivers/gpu/drm/radeon/radeon_cp.c | 2 +
drivers/gpu/drm/radeon/radeon_cs.c | 176 +++++-
drivers/gpu/drm/radeon/radeon_device.c | 1 +
drivers/gpu/drm/radeon/radeon_drv.c | 70 +-
drivers/gpu/drm/radeon/radeon_drv.h | 16 +-
drivers/gpu/drm/radeon/radeon_family.h | 1 +
drivers/gpu/drm/radeon/radeon_gart.c | 60 +-
drivers/gpu/drm/radeon/radeon_irq.c | 2 +
drivers/gpu/drm/radeon/radeon_mem.c | 2 +
drivers/gpu/drm/radeon/radeon_reg.h | 15 +
drivers/gpu/drm/radeon/radeon_ring.c | 19 +
drivers/gpu/drm/radeon/radeon_state.c | 2 +
drivers/gpu/drm/radeon/rv515d.h | 11 -
drivers/gpu/drm/radeon/si.c | 478 ++++++++++----
drivers/gpu/drm/radeon/sid.h | 25 +-
include/drm/drm_pciids.h | 13 +
43 files changed, 2199 insertions(+), 1887 deletions(-)
[View Less]
https://bugs.freedesktop.org/show_bug.cgi?id=26891
--- Comment #54 from Austin Lund <austin.lund(a)gmail.com> ---
This does seem to be fixed in 3.8 series kernels. I just tested 3.8-rc6 and
booted fine into radeondrmfb. I could get the vgaswitcheroo to move between
the integrated and discrete, but I couldn't get the intel console to work (will
have to check my config).
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https://bugs.freedesktop.org/show_bug.cgi?id=60034
Priority: medium
Bug ID: 60034
Assignee: dri-devel(a)lists.freedesktop.org
Summary: rv790 etqw regression since r600g: add async for
staging buffer upload v2
Severity: normal
Classification: Unclassified
OS: Linux (All)
Reporter: lists(a)andyfurniss.entadsl.com
Hardware: x86 (IA32)
Status: NEW
Version: git
…
[View More] Component: Drivers/Gallium/r600
Product: Mesa
Card PCIE HD4890, drm fixes kernel.
Since -
commit 325422c49449acdd8df1eb2ca8ed81f7696c38cc
Author: Jerome Glisse <jglisse(a)redhat.com>
Date: Mon Jan 7 17:45:59 2013 -0500
r600g: add async for staging buffer upload v2
v2: Add virtual address to dma src/dst offset for cayman
I can see some reflection rendering errors in etqw.
They are not visible on most maps but looking from high up on island where the
sky is reflected in the sea they are obvious from a cold boot, but far more
subtle after running repeatedly for bisect.
attached screenshots showing both cases.
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