dri-devel June 2013

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[PATCH] drm/mgag200: Hardware cursor support
by Christopher Harvey 17 Jun '13

17 Jun '13

G200 cards support, at best, 16 colour palleted images for the cursor so we do a conversion in the cursor_set function, and reject cursors with more than 16 colours, or cursors with partial transparency. Xorg falls back gracefully to software cursors in this case. We can't disable/enable the cursor hardware without causing momentary corruption around the cursor. Instead, once the cursor is on we leave it on, and simulate turning the cursor off by moving it offscreen. This works well. Since we … [View More]can't disable -> update -> enable the cursors, we double buffer cursor icons, then just move the base address that points to the old cursor, to the new. This also works well, but uses an extra page of memory. The cursor buffers are lazily-allocated on first cursor_set. This is to make sure they don't take priority over any framebuffers in case of limited memory. Here is a representation of how the bitmap for the cursor is mapped in G200 memory : Each line of color cursor use 6 Slices of 8 bytes. Slices 0 to 3 are used for the 4bpp bitmap, slice 4 for XOR mask and slice 5 for AND mask. Each line has the following format: // Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 // // S0: P00-01 P02-03 P04-05 P06-07 P08-09 P10-11 P12-13 P14-15 // S1: P16-17 P18-19 P20-21 P22-23 P24-25 P26-27 P28-29 P30-31 // S2: P32-33 P34-35 P36-37 P38-39 P40-41 P42-43 P44-45 P46-47 // S3: P48-49 P50-51 P52-53 P54-55 P56-57 P58-59 P60-61 P62-63 // S4: X63-56 X55-48 X47-40 X39-32 X31-24 X23-16 X15-08 X07-00 // S5: A63-56 A55-48 A47-40 A39-32 A31-24 A23-16 A15-08 A07-00 // // S0 to S5 = Slices 0 to 5 // P00 to P63 = Bitmap - pixels 0 to 63 // X00 to X63 = always 0 - pixels 0 to 63 // A00 to A63 = transparent markers - pixels 0 to 63 // 1 means colour, 0 means transparent Signed-off-by: Christopher Harvey <charvey(a)matrox.com> Signed-off-by: Mathieu Larouche <mathieu.larouche(a)matrox.com> Acked-by: Julia Lemire <jlemire(a)matrox.com> Tested-by: Julia Lemire <jlemire(a)matrox.com> --- drivers/gpu/drm/mgag200/Makefile | 2 +- drivers/gpu/drm/mgag200/mgag200_cursor.c | 275 +++++++++++++++++++++++++++++++ drivers/gpu/drm/mgag200/mgag200_drv.h | 21 +++ drivers/gpu/drm/mgag200/mgag200_main.c | 21 ++- drivers/gpu/drm/mgag200/mgag200_mode.c | 2 + drivers/gpu/drm/mgag200/mgag200_reg.h | 6 +- 6 files changed, 324 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/mgag200/mgag200_cursor.c diff --git a/drivers/gpu/drm/mgag200/Makefile b/drivers/gpu/drm/mgag200/Makefile index 7db592e..a9a0300 100644 --- a/drivers/gpu/drm/mgag200/Makefile +++ b/drivers/gpu/drm/mgag200/Makefile @@ -1,5 +1,5 @@ ccflags-y := -Iinclude/drm -mgag200-y := mgag200_main.o mgag200_mode.o \ +mgag200-y := mgag200_main.o mgag200_mode.o mgag200_cursor.o \ mgag200_drv.o mgag200_fb.o mgag200_i2c.o mgag200_ttm.o obj-$(CONFIG_DRM_MGAG200) += mgag200.o diff --git a/drivers/gpu/drm/mgag200/mgag200_cursor.c b/drivers/gpu/drm/mgag200/mgag200_cursor.c new file mode 100644 index 0000000..801731a --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_cursor.c @@ -0,0 +1,275 @@ +/* + * Copyright 2013 Matrox Graphics + * + * This file is subject to the terms and conditions of the GNU General + * Public License version 2. See the file COPYING in the main + * directory of this archive for more details. + * + * Author: Christopher Harvey <charvey(a)matrox.com> + */ + +#include <drm/drmP.h> +#include "mgag200_drv.h" + +static bool warn_transparent = true; +static bool warn_palette = true; + +/* + Hide the cursor off screen. We can't disable the cursor hardware because it + takes too long to re-activate and causes momentary corruption +*/ +static void mga_hide_cursor(struct mga_device *mdev) +{ + WREG8(MGA_CURPOSXL, 0); + WREG8(MGA_CURPOSXH, 0); + mgag200_bo_unpin(mdev->cursor.pixels_1); + mgag200_bo_unpin(mdev->cursor.pixels_2); +} + +int mga_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height) +{ + struct drm_device *dev = (struct drm_device *)file_priv->minor->dev; + struct mga_device *mdev = (struct mga_device *)dev->dev_private; + struct mgag200_bo *pixels_1 = mdev->cursor.pixels_1; + struct mgag200_bo *pixels_2 = mdev->cursor.pixels_2; + struct mgag200_bo *pixels_current = mdev->cursor.pixels_current; + struct mgag200_bo *pixels_prev = mdev->cursor.pixels_prev; + struct drm_gem_object *obj; + struct mgag200_bo *bo = NULL; + int ret = 0; + unsigned int i, row, col; + uint32_t colour_set[16]; + uint32_t *next_space = &colour_set[0]; + uint32_t *palette_iter; + uint32_t this_colour; + bool found = false; + int colour_count = 0; + u64 gpu_addr; + u8 reg_index; + u8 this_row[48]; + + if (!pixels_1 || !pixels_2) { + WREG8(MGA_CURPOSXL, 0); + WREG8(MGA_CURPOSXH, 0); + return -ENOTSUPP; /* Didn't allocate space for cursors */ + } + + if ((width != 64 || height != 64) && handle) { + WREG8(MGA_CURPOSXL, 0); + WREG8(MGA_CURPOSXH, 0); + return -EINVAL; + } + + BUG_ON(pixels_1 != pixels_current && pixels_1 != pixels_prev); + BUG_ON(pixels_2 != pixels_current && pixels_2 != pixels_prev); + BUG_ON(pixels_current == pixels_prev); + + ret = mgag200_bo_reserve(pixels_1, true); + if (ret) { + WREG8(MGA_CURPOSXL, 0); + WREG8(MGA_CURPOSXH, 0); + return ret; + } + ret = mgag200_bo_reserve(pixels_2, true); + if (ret) { + WREG8(MGA_CURPOSXL, 0); + WREG8(MGA_CURPOSXH, 0); + mgag200_bo_unreserve(pixels_1); + return ret; + } + + if (!handle) { + mga_hide_cursor(mdev); + ret = 0; + goto out1; + } + + /* Move cursor buffers into VRAM if they aren't already */ + if (!pixels_1->pin_count) { + ret = mgag200_bo_pin(pixels_1, TTM_PL_FLAG_VRAM, + &mdev->cursor.pixels_1_gpu_addr); + if (ret) + goto out1; + } + if (!pixels_2->pin_count) { + ret = mgag200_bo_pin(pixels_2, TTM_PL_FLAG_VRAM, + &mdev->cursor.pixels_2_gpu_addr); + if (ret) { + mgag200_bo_unpin(pixels_1); + goto out1; + } + } + + mutex_lock(&dev->struct_mutex); + obj = drm_gem_object_lookup(dev, file_priv, handle); + if (!obj) { + mutex_unlock(&dev->struct_mutex); + ret = -ENOENT; + goto out1; + } + drm_gem_object_unreference(obj); + mutex_unlock(&dev->struct_mutex); + + bo = gem_to_mga_bo(obj); + ret = mgag200_bo_reserve(bo, true); + if (ret) { + dev_err(&dev->pdev->dev, "failed to reserve user bo\n"); + goto out1; + } + if (!bo->kmap.virtual) { + ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); + if (ret) { + dev_err(&dev->pdev->dev, "failed to kmap user buffer updates\n"); + goto out2; + } + } + + memset(&colour_set[0], 0, sizeof(uint32_t)*16); + /* width*height*4 = 16384 */ + for (i = 0; i < 16384; i += 4) { + this_colour = ioread32(bo->kmap.virtual + i); + /* No transparency */ + if (this_colour>>24 != 0xff && + this_colour>>24 != 0x0) { + if (warn_transparent) { + dev_info(&dev->pdev->dev, "Video card doesn't support cursors with partial transparency.\n"); + dev_info(&dev->pdev->dev, "Not enabling hardware cursor.\n"); + warn_transparent = false; /* Only tell the user once. */ + } + ret = -EINVAL; + goto out3; + } + /* Don't need to store transparent pixels as colours */ + if (this_colour>>24 == 0x0) + continue; + found = false; + for (palette_iter = &colour_set[0]; palette_iter != next_space; palette_iter++) { + if (*palette_iter == this_colour) { + found = true; + break; + } + } + if (found) + continue; + /* We only support 4bit paletted cursors */ + if (colour_count >= 16) { + if (warn_palette) { + dev_info(&dev->pdev->dev, "Video card only supports cursors with up to 16 colours.\n"); + dev_info(&dev->pdev->dev, "Not enabling hardware cursor.\n"); + warn_palette = false; /* Only tell the user once. */ + } + ret = -EINVAL; + goto out3; + } + *next_space = this_colour; + next_space++; + colour_count++; + } + + /* Program colours from cursor icon into palette */ + for (i = 0; i < colour_count; i++) { + if (i <= 2) + reg_index = 0x8 + i*0x4; + else + reg_index = 0x60 + i*0x3; + WREG_DAC(reg_index, colour_set[i] & 0xff); + WREG_DAC(reg_index+1, colour_set[i]>>8 & 0xff); + WREG_DAC(reg_index+2, colour_set[i]>>16 & 0xff); + BUG_ON((colour_set[i]>>24 & 0xff) != 0xff); + } + + /* Map up-coming buffer to write colour indices */ + if (!pixels_prev->kmap.virtual) { + ret = ttm_bo_kmap(&pixels_prev->bo, 0, + pixels_prev->bo.num_pages, + &pixels_prev->kmap); + if (ret) { + dev_err(&dev->pdev->dev, "failed to kmap cursor updates\n"); + goto out3; + } + } + + /* now write colour indices into hardware cursor buffer */ + for (row = 0; row < 64; row++) { + memset(&this_row[0], 0, 48); + for (col = 0; col < 64; col++) { + this_colour = ioread32(bo->kmap.virtual + 4*(col + 64*row)); + /* write transparent pixels */ + if (this_colour>>24 == 0x0) { + this_row[47 - col/8] |= 0x80>>(col%8); + continue; + } + + /* write colour index here */ + for (i = 0; i < colour_count; i++) { + if (colour_set[i] == this_colour) { + if (col % 2) + this_row[col/2] |= i<<4; + else + this_row[col/2] |= i; + break; + } + } + } + memcpy_toio(pixels_prev->kmap.virtual + row*48, &this_row[0], 48); + } + + /* Program gpu address of cursor buffer */ + if (pixels_prev == pixels_1) + gpu_addr = mdev->cursor.pixels_1_gpu_addr; + else + gpu_addr = mdev->cursor.pixels_2_gpu_addr; + WREG_DAC(MGA1064_CURSOR_BASE_ADR_LOW, (u8)((gpu_addr>>10) & 0xff)); + WREG_DAC(MGA1064_CURSOR_BASE_ADR_HI, (u8)((gpu_addr>>18) & 0x3f)); + + /* Adjust cursor control register to turn on the cursor */ + WREG_DAC(MGA1064_CURSOR_CTL, 4); /* 16-colour palletized cursor mode */ + + /* Now swap internal buffer pointers */ + if (mdev->cursor.pixels_1 == mdev->cursor.pixels_prev) { + mdev->cursor.pixels_prev = mdev->cursor.pixels_2; + mdev->cursor.pixels_current = mdev->cursor.pixels_1; + } else if (mdev->cursor.pixels_1 == mdev->cursor.pixels_current) { + mdev->cursor.pixels_prev = mdev->cursor.pixels_1; + mdev->cursor.pixels_current = mdev->cursor.pixels_2; + } else { + BUG(); + } + ret = 0; + + ttm_bo_kunmap(&pixels_prev->kmap); + out3: + ttm_bo_kunmap(&bo->kmap); + out2: + mgag200_bo_unreserve(bo); + out1: + if (ret) + mga_hide_cursor(mdev); + mgag200_bo_unreserve(pixels_1); + mgag200_bo_unreserve(pixels_2); + return ret; +} + +int mga_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) +{ + struct mga_device *mdev = (struct mga_device *)crtc->dev->dev_private; + /* Our origin is at (64,64) */ + x += 64; + y += 64; + + BUG_ON(x <= 0); + BUG_ON(y <= 0); + BUG_ON(x & ~0xffff); + BUG_ON(y & ~0xffff); + + WREG8(MGA_CURPOSXL, x & 0xff); + WREG8(MGA_CURPOSXH, (x>>8) & 0xff); + + WREG8(MGA_CURPOSYL, y & 0xff); + WREG8(MGA_CURPOSYH, (y>>8) & 0xff); + return 0; +} diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h index bf29b2f..364a05a 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.h +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -149,6 +149,21 @@ struct mga_connector { struct mga_i2c_chan *i2c; }; +struct mga_cursor { + /* + We have to have 2 buffers for the cursor to avoid occasional + corruption while switching cursor icons. + If either of these is NULL, then don't do hardware cursors, and + fall back to software. + */ + struct mgag200_bo *pixels_1; + struct mgag200_bo *pixels_2; + u64 pixels_1_gpu_addr, pixels_2_gpu_addr; + /* The currently displayed icon, this points to one of pixels_1, or pixels_2 */ + struct mgag200_bo *pixels_current; + /* The previously displayed icon */ + struct mgag200_bo *pixels_prev; +}; struct mga_mc { resource_size_t vram_size; @@ -181,6 +196,7 @@ struct mga_device { struct mga_mode_info mode_info; struct mga_fbdev *mfbdev; + struct mga_cursor cursor; bool suspended; int num_crtc; @@ -273,4 +289,9 @@ int mgag200_mmap(struct file *filp, struct vm_area_struct *vma); int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr); int mgag200_bo_unpin(struct mgag200_bo *bo); int mgag200_bo_push_sysram(struct mgag200_bo *bo); + /* mgag200_cursor.c */ +int mga_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, + uint32_t handle, uint32_t width, uint32_t height); +int mga_crtc_cursor_move(struct drm_crtc *crtc, int x, int y); + #endif /* __MGAG200_DRV_H__ */ diff --git a/drivers/gpu/drm/mgag200/mgag200_main.c b/drivers/gpu/drm/mgag200/mgag200_main.c index 9905923..5189675 100644 --- a/drivers/gpu/drm/mgag200/mgag200_main.c +++ b/drivers/gpu/drm/mgag200/mgag200_main.c @@ -221,8 +221,27 @@ int mgag200_driver_load(struct drm_device *dev, unsigned long flags) dev->mode_config.prefer_shadow = 1; r = mgag200_modeset_init(mdev); - if (r) + if (r) { dev_err(&dev->pdev->dev, "Fatal error during modeset init: %d\n", r); + goto out; + } + + /* Make small buffers to store a hardware cursor (double buffered icon updates) */ + mgag200_bo_create(dev, roundup(48*64, PAGE_SIZE), 0, 0, + &mdev->cursor.pixels_1); + mgag200_bo_create(dev, roundup(48*64, PAGE_SIZE), 0, 0, + &mdev->cursor.pixels_2); + if (!mdev->cursor.pixels_2 || !mdev->cursor.pixels_1) + goto cursor_nospace; + mdev->cursor.pixels_current = mdev->cursor.pixels_1; + mdev->cursor.pixels_prev = mdev->cursor.pixels_2; + goto cursor_done; + cursor_nospace: + mdev->cursor.pixels_1 = NULL; + mdev->cursor.pixels_2 = NULL; + dev_warn(&dev->pdev->dev, "Could not allocate space for cursors. Not doing hardware cursors.\n"); + cursor_done: + out: if (r) mgag200_driver_unload(dev); diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index 77b8a45..deed0bd 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -1252,6 +1252,8 @@ static void mga_crtc_destroy(struct drm_crtc *crtc) /* These provide the minimum set of functions required to handle a CRTC */ static const struct drm_crtc_funcs mga_crtc_funcs = { + .cursor_set = mga_crtc_cursor_set, + .cursor_move = mga_crtc_cursor_move, .gamma_set = mga_crtc_gamma_set, .set_config = drm_crtc_helper_set_config, .destroy = mga_crtc_destroy, diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h index fb24d86..3ae442a6 100644 --- a/drivers/gpu/drm/mgag200/mgag200_reg.h +++ b/drivers/gpu/drm/mgag200/mgag200_reg.h @@ -235,7 +235,11 @@ #define MGAREG_CRTCEXT_INDEX 0x1fde #define MGAREG_CRTCEXT_DATA 0x1fdf - +/* Cursor X and Y position */ +#define MGA_CURPOSXL 0x3c0c +#define MGA_CURPOSXH 0x3c0d +#define MGA_CURPOSYL 0x3c0e +#define MGA_CURPOSYH 0x3c0f /* MGA bits for registers PCI_OPTION_REG */ #define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 ) -- 1.8.1.5 [View Less]

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WARNING: at drivers/gpu/drm/nouveau/core/core/mm.c:242
by Jiri Slaby 17 Jun '13

17 Jun '13

Hi, we have a report of WARNING from 3.7.6 in nouveau at drivers/gpu/drm/nouveau/core/core/mm.c:242 here: https://bugzilla.novell.com/show_bug.cgi?id=802347#c11 There is an order 4 allocation failure in nouveau_drm_open -> nouveau_vm_create, i.e. this one failed: vm->pgt = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); Then, on the error path in still in nouveau_drm_open, it is followed by a call to nouveau_cli_destroy. But that one calls nouveau_vm_ref -> … [View More]

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linux-next: manual merge of the drm-intel tree with Linus' tree
by Stephen Rothwell 17 Jun '13

17 Jun '13

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in drivers/gpu/drm/i915/intel_sdvo.c between commit 7ba220cec0bb ("drm/i915: Enable hotplug interrupts after querying hw capabilities") from Linus' tree and commit e596a02ccfc6 ("drm/i915: Remove dead code from SDVO initialisation") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary (no action is required). -- Cheers, Stephen Rothwell sfr(a)canb.auug.org.au diff --cc … [View More]

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linux-next: manual merge of the drm-intel tree with Linus' tree
by Stephen Rothwell 17 Jun '13

17 Jun '13

Hi all, Today's linux-next merge of the drm-intel tree got a conflict in drivers/gpu/drm/i915/intel_display.c between commit d62cf62ad07d ("drm/i915: Quirk the pipe A quirk in the modeset state checker") from Linus' tree and commit 6c49f24180c3 ("drm/i915: hw state readout support for pixel_multiplier") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary (no action is required). -- Cheers, Stephen Rothwell sfr(a)canb.auug.org.au diff --… [View More]

1 0

[Bug 57381] Radeon HD6950: Resuming from hibernation fails sometimes
by bugzilla-daemon＠bugzilla.kernel.org 17 Jun '13

17 Jun '13

1 0

[PATCH 1/3] drm: add mmap function to prime helpers
by Joonyoung Shim 17 Jun '13

17 Jun '13

This adds to call low-level mmap() from prime helpers. Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- drivers/gpu/drm/drm_prime.c | 5 ++++- include/drm/drmP.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index d92853e..3a008b2 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -165,7 +165,10 @@ static void drm_gem_dmabuf_kunmap(struct dma_buf *dma_buf, … [View More]

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[libdrm] intel: get rid of the .data section
by Arjan van de Ven 17 Jun '13

17 Jun '13

>From 8e61934c3918484bae10d9ff771c93ad1fa73e29 Mon Sep 17 00:00:00 2001 From: Arjan van de Ven <arjanvandeven(a)gmail.com> Date: Sun, 16 Jun 2013 11:12:53 -0700 Subject: [PATCH 2/2] intel: get rid of the .data section head_offset and tail_offset are the only two global variables in the whole library that are not 0 initialized (and thus make up the .data section) However, the first thing that drm_intel_decode() does is give them a new value, and all uses of instr_out() that uses … [View More]

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[libdrm] intel: Mark large read only local arrays as static const
by Arjan van de Ven 17 Jun '13

17 Jun '13

>From 27eef3eba293163a0c2348566d2470978c3f6c0e Mon Sep 17 00:00:00 2001 From: Arjan van de Ven <arjanvandeven(a)gmail.com> Date: Sun, 16 Jun 2013 10:56:35 -0700 Subject: [PATCH 1/2] intel: Mark large read only local arrays as static const In the instruction decoder, various arrays that are local to functions, but are read only, were not declared static const... causing the compiler to construct said array on the stack each call. Rather than using code to do this... just declare these … [View More]arrays static const. In addition, to avoid relocations, use char [] instead of char * (as per DSOHowto), this may appear to waste a little bit of space, but that is very limited in practice, and it means these arrays can just be mapped in the read-only section. on x86-64, some basic size results Before: libdrm_intel.so.1.0.0: 76 relocations, 69 relative (90%), 56 PLT entries, 11 for local syms (19%) [11] .text PROGBITS 0000000000002c80 00002c80 00013c48 0 AX 0 0 16 [13] .rodata PROGBITS 00000000000168e0 000168e0 00005c3b 0 A 0 0 32 [19] .data.rel.ro PROGBITS 000000000021f018 0001f018 00000008 0 WA 0 0 8 [23] .data PROGBITS 000000000021f440 0001f440 00000640 0 WA 0 0 32 [24] .bss NOBITS 000000000021fa80 0001fa80 00000020 0 WA 0 0 8 After: libdrm_intel.so.1.0.0: 32 relocations, 25 relative (78%), 56 PLT entries, 11 for local syms (19%) [11] .text PROGBITS 0000000000002860 00002860 00011db8 0 AX 0 0 16 [13] .rodata PROGBITS 0000000000014640 00014640 00005c63 0 A 0 0 32 [19] .data.rel.ro PROGBITS 000000000021d020 0001d020 00001a08 0 WA 0 0 32 [23] .data PROGBITS 000000000021ee48 0001ee48 00000008 0 WA 0 0 4 [24] .bss NOBITS 000000000021ee50 0001ee50 00000048 0 WA 0 0 8 Signed-off-by: Arjan van de Ven <arjan(a)linux.intel.com> --- intel/intel_decode.c | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/intel/intel_decode.c b/intel/intel_decode.c index ff19f92..fdbbe0c 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -229,12 +229,12 @@ decode_mi(struct drm_intel_decode *ctx) const char *post_sync_op = ""; uint32_t *data = ctx->data; - struct { + static const struct { uint32_t opcode; int len_mask; unsigned int min_len; unsigned int max_len; - const char *name; + const char name[24]; int (*func)(struct drm_intel_decode *ctx); } opcodes_mi[] = { { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" }, @@ -420,11 +420,11 @@ decode_2d(struct drm_intel_decode *ctx) unsigned int opcode, len; uint32_t *data = ctx->data; - struct { + static const struct { uint32_t opcode; unsigned int min_len; unsigned int max_len; - const char *name; + const char name[38]; } opcodes_2d[] = { { 0x40, 5, 5, "COLOR_BLT" }, { 0x43, 6, 6, "SRC_COPY_BLT" }, @@ -1271,12 +1271,12 @@ decode_3d_1d(struct drm_intel_decode *ctx) uint32_t *data = ctx->data; uint32_t devid = ctx->devid; - struct { + static const struct { uint32_t opcode; int i830_only; unsigned int min_len; unsigned int max_len; - const char *name; + const char name[34]; } opcodes_3d_1d[] = { { 0x86, 0, 4, 4, "3DSTATE_CHROMA_KEY" }, { 0x88, 0, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" }, @@ -2543,11 +2543,11 @@ decode_3d(struct drm_intel_decode *ctx) unsigned int idx; uint32_t *data = ctx->data; - struct { + static const struct { uint32_t opcode; unsigned int min_len; unsigned int max_len; - const char *name; + const char name[34]; } opcodes_3d[] = { { 0x06, 1, 1, "3DSTATE_ANTI_ALIASING" }, { 0x08, 1, 1, "3DSTATE_BACKFACE_STENCIL_OPS" }, @@ -3138,12 +3138,12 @@ decode_3d_965(struct drm_intel_decode *ctx) uint32_t *data = ctx->data; uint32_t devid = ctx->devid; - struct { + static const struct { uint32_t opcode; uint32_t len_mask; int unsigned min_len; int unsigned max_len; - const char *name; + const char name[34]; int gen; int (*func)(struct drm_intel_decode *ctx); } opcodes_3d[] = { @@ -3169,8 +3169,8 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x780a, 0x00ff, 3, 3, "3DSTATE_INDEX_BUFFER" }, { 0x780b, 0xffff, 1, 1, "3DSTATE_VF_STATISTICS" }, { 0x780d, 0x00ff, 4, 4, "3DSTATE_VIEWPORT_STATE_POINTERS" }, - { 0x780e, 0xffff, 4, 4, NULL, 6, gen6_3DSTATE_CC_STATE_POINTERS }, - { 0x780e, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_CC_STATE_POINTERS }, + { 0x780e, 0xffff, 4, 4, "", 6, gen6_3DSTATE_CC_STATE_POINTERS }, + { 0x780e, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_CC_STATE_POINTERS }, { 0x780f, 0x00ff, 2, 2, "3DSTATE_SCISSOR_POINTERS" }, { 0x7810, 0x00ff, 6, 6, "3DSTATE_VS" }, { 0x7811, 0x00ff, 7, 7, "3DSTATE_GS" }, @@ -3194,10 +3194,10 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x781e, 0x00ff, 3, 3, "3DSTATE_STREAMOUT" }, { 0x781f, 0x00ff, 14, 14, "3DSTATE_SBE" }, { 0x7820, 0x00ff, 8, 8, "3DSTATE_PS" }, - { 0x7821, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP }, - { 0x7823, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC }, - { 0x7824, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_BLEND_STATE_POINTERS }, - { 0x7825, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS }, + { 0x7821, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP }, + { 0x7823, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC }, + { 0x7824, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_BLEND_STATE_POINTERS }, + { 0x7825, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS }, { 0x7826, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_VS" }, { 0x7827, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_HS" }, { 0x7828, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_DS" }, @@ -3208,10 +3208,10 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x782d, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_DS" }, { 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" }, { 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" }, - { 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS }, - { 0x7831, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_HS }, - { 0x7832, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_DS }, - { 0x7833, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_GS }, + { 0x7830, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_URB_VS }, + { 0x7831, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_URB_HS }, + { 0x7832, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_URB_DS }, + { 0x7833, 0x00ff, 2, 2, "", 7, gen7_3DSTATE_URB_GS }, { 0x7900, 0xffff, 4, 4, "3DSTATE_DRAWING_RECTANGLE" }, { 0x7901, 0xffff, 5, 5, "3DSTATE_CONSTANT_COLOR" }, { 0x7905, 0xffff, 5, 7, "3DSTATE_DEPTH_BUFFER" }, @@ -3233,8 +3233,8 @@ decode_3d_965(struct drm_intel_decode *ctx) { 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" }, { 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" }, { 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" }, - { 0x7b00, 0x00ff, 7, 7, NULL, 7, gen7_3DPRIMITIVE }, - { 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE }, + { 0x7b00, 0x00ff, 7, 7, "", 7, gen7_3DPRIMITIVE }, + { 0x7b00, 0x00ff, 6, 6, "", 0, gen4_3DPRIMITIVE }, }, *opcode_3d = NULL; opcode = (data[0] & 0xffff0000) >> 16; @@ -3751,11 +3751,11 @@ decode_3d_i830(struct drm_intel_decode *ctx) uint32_t opcode; uint32_t *data = ctx->data; - struct { + static const struct { uint32_t opcode; unsigned int min_len; unsigned int max_len; - const char *name; + const char name[28]; } opcodes_3d[] = { { 0x02, 1, 1, "3DSTATE_MODES_3" }, { 0x03, 1, 1, "3DSTATE_ENABLES_1" }, -- 1.7.11.7 [View Less]

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[Bug 65377] New: Backlight control via /sys/class/backlight/radeon_bl0 not working
by bugzilla-daemon＠freedesktop.org 16 Jun '13

16 Jun '13

https://bugs.freedesktop.org/show_bug.cgi?id=65377 Priority: medium Bug ID: 65377 Assignee: dri-devel(a)lists.freedesktop.org Summary: Backlight control via /sys/class/backlight/radeon_bl0 not working Severity: normal Classification: Unclassified OS: Linux (All) Reporter: bastian.triller(a)gmail.com Hardware: x86-64 (AMD64) Status: NEW Version: XOrg CVS … [View More]

1 9

[Bug 65803] New: r600g: segfault with Kerbal Space Program
by bugzilla-daemon＠freedesktop.org 16 Jun '13

16 Jun '13

https://bugs.freedesktop.org/show_bug.cgi?id=65803 Priority: medium Bug ID: 65803 Assignee: dri-devel(a)lists.freedesktop.org Summary: r600g: segfault with Kerbal Space Program Severity: normal Classification: Unclassified OS: Linux (All) Reporter: corey(a)octayn.net Hardware: x86-64 (AMD64) Status: NEW Version: git Component: Drivers/Gallium/r600 Product: … [View More]

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dri-devel June 2013