dri-devel May 2014

dri-devel@lists.freedesktop.org

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970 discussions

[RFC v3 PATCH 00/16] drm/exynos: support MIPI DSI command mode display
by YoungJun Cho 08 May '14

08 May '14

This patch series includes the followings: - FIMD I80 interface - DSI command mode interface for Exynos5420 SoC - S6E3FA0 command mode type panel driver This patch series is based on exynos-drm-next branch. Previous patch set, RFC v1: http://www.spinics.net/lists/dri-devel/msg57513.html RFC v2: http://www.spinics.net/lists/dri-devel/msg57945.html Changelog v2: - Moves panel delays and size DT properties to panel probe routine. - Moves CPU timings relevant DT properties from FIMD to panel DT.… [View More] Changelog v3: - Splits core and driver patchset. - Renames CPU timings to CPU mode timings. - Enhances panel code readability. Thank you. Best regards YJ YoungJun Cho (16): drm/exynos: dsi: move the Eot packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: sysreg: add exynos5 compatible to DT bindings ARM: dts: samsung-fimd: add I80 specific properties drm/panel: add CPU mode timings structure drm/exynos: add TE handler to support MIPI DSI command mode interface drm/exynos: dsi: add TE handler to support command mode interface drm/exynos: fimd: support I80 interface ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5420 ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register node ARM: dts: exynos5: add system register support ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/arm/samsung/sysreg.txt | 1 + .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 68 +++ .../devicetree/bindings/video/exynos_dsim.txt | 4 +- .../devicetree/bindings/video/samsung-fimd.txt | 2 + arch/arm/boot/dts/exynos4.dtsi | 1 + arch/arm/boot/dts/exynos5.dtsi | 6 + arch/arm/boot/dts/exynos5420.dtsi | 21 + drivers/gpu/drm/exynos/Kconfig | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 16 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 + drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 172 +++++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 280 +++++++-- drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 595 ++++++++++++++++++++ include/drm/drm_mipi_dsi.h | 8 + include/drm/drm_panel.h | 18 + include/video/samsung_fimd.h | 3 +- 19 files changed, 1143 insertions(+), 71 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.7.9.5 [View Less]

4 26

[Bug 74347] New: openra screen corruption on a HD2600
by bugzilla-daemon＠freedesktop.org 07 May '14

07 May '14

https://bugs.freedesktop.org/show_bug.cgi?id=74347 Priority: medium Bug ID: 74347 Assignee: dri-devel(a)lists.freedesktop.org Summary: openra screen corruption on a HD2600 Severity: normal Classification: Unclassified OS: Linux (All) Reporter: higuita(a)gmx.net Hardware: Other Status: NEW Version: git Component: Drivers/DRI/Radeon Product: Mesa Created … [View More]

1 12

[PATCH] drm/radeon: avoid segfault on device open when accel is not working.
by j.glisse＠gmail.com 07 May '14

07 May '14

From: Jérôme Glisse <jglisse(a)redhat.com> When accel is not working on device with virtual address space radeon segfault because the ib buffer is NULL and trying to map it inside the virtual address space trigger segfault. This patch only map the ib buffer if accel is working. Cc: <stable(a)vger.kernel.org> Signed-off-by: Jérôme Glisse <jglisse(a)redhat.com> --- drivers/gpu/drm/radeon/radeon_kms.c | 55 +++++++++++++++++++------------------ 1 file changed, 29 insertions(+),… [View More] 26 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 0cc47f1..eaaedba 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -577,28 +577,29 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) return r; } - r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); - if (r) { - radeon_vm_fini(rdev, &fpriv->vm); - kfree(fpriv); - return r; - } + if (rdev->accel_working) { + r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); + if (r) { + radeon_vm_fini(rdev, &fpriv->vm); + kfree(fpriv); + return r; + } - /* map the ib pool buffer read only into - * virtual address space */ - bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, - rdev->ring_tmp_bo.bo); - r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, - RADEON_VM_PAGE_READABLE | - RADEON_VM_PAGE_SNOOPED); + /* map the ib pool buffer read only into + * virtual address space */ + bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, + rdev->ring_tmp_bo.bo); + r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, + RADEON_VM_PAGE_READABLE | + RADEON_VM_PAGE_SNOOPED); - radeon_bo_unreserve(rdev->ring_tmp_bo.bo); - if (r) { - radeon_vm_fini(rdev, &fpriv->vm); - kfree(fpriv); - return r; + radeon_bo_unreserve(rdev->ring_tmp_bo.bo); + if (r) { + radeon_vm_fini(rdev, &fpriv->vm); + kfree(fpriv); + return r; + } } - file_priv->driver_priv = fpriv; } @@ -626,13 +627,15 @@ void radeon_driver_postclose_kms(struct drm_device *dev, struct radeon_bo_va *bo_va; int r; - r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); - if (!r) { - bo_va = radeon_vm_bo_find(&fpriv->vm, - rdev->ring_tmp_bo.bo); - if (bo_va) - radeon_vm_bo_rmv(rdev, bo_va); - radeon_bo_unreserve(rdev->ring_tmp_bo.bo); + if (rdev->accel_working) { + r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); + if (!r) { + bo_va = radeon_vm_bo_find(&fpriv->vm, + rdev->ring_tmp_bo.bo); + if (bo_va) + radeon_vm_bo_rmv(rdev, bo_va); + radeon_bo_unreserve(rdev->ring_tmp_bo.bo); + } } radeon_vm_fini(rdev, &fpriv->vm); -- 1.9.0 [View Less]

2 1

[PATCH] drm/radeon: check VCE relocation buffer range v3
by Christian König 07 May '14

07 May '14

From: Leo Liu <leo.liu(a)amd.com> v2 (chk): fix image size storage v3 (chk): fix UV size calculation Signed-off-by: Leo Liu <leo.liu(a)amd.com> --- drivers/gpu/drm/radeon/radeon.h | 3 +- drivers/gpu/drm/radeon/radeon_vce.c | 130 +++++++++++++++++++++++++++--------- 2 files changed, 102 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 6852861..91be3d6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/… [View More]drivers/gpu/drm/radeon/radeon.h @@ -1642,6 +1642,7 @@ struct radeon_vce { unsigned fb_version; atomic_t handles[RADEON_MAX_VCE_HANDLES]; struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; + unsigned img_size[RADEON_MAX_VCE_HANDLES]; struct delayed_work idle_work; }; @@ -1655,7 +1656,7 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence); void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); void radeon_vce_note_usage(struct radeon_device *rdev); -int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi); +int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); int radeon_vce_cs_parse(struct radeon_cs_parser *p); bool radeon_vce_semaphore_emit(struct radeon_device *rdev, struct radeon_ring *ring, diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index ced53dd..992b74e 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -442,13 +442,16 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, * @p: parser context * @lo: address of lower dword * @hi: address of higher dword + * @size: size of checker for relocation buffer * * Patch relocation inside command stream with real buffer address */ -int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi) +int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, + unsigned size) { struct radeon_cs_chunk *relocs_chunk; - uint64_t offset; + struct radeon_cs_reloc *reloc; + uint64_t start, end, offset; unsigned idx; relocs_chunk = &p->chunks[p->chunk_relocs_idx]; @@ -461,15 +464,60 @@ int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi) return -EINVAL; } - offset += p->relocs_ptr[(idx / 4)]->gpu_offset; + reloc = p->relocs_ptr[(idx / 4)]; + start = reloc->gpu_offset; + end = start + radeon_bo_size(reloc->robj); + start += offset; - p->ib.ptr[lo] = offset & 0xFFFFFFFF; - p->ib.ptr[hi] = offset >> 32; + p->ib.ptr[lo] = start & 0xFFFFFFFF; + p->ib.ptr[hi] = start >> 32; + + if (end <= start) { + DRM_ERROR("invalid reloc offset %llX!\n", offset); + return -EINVAL; + } + if ((end - start) < size) { + DRM_ERROR("buffer to small (%d / %d)!\n", + (unsigned)(end - start), size); + return -EINVAL; + } return 0; } /** + * radeon_vce_validate_handle - validate stream handle + * + * @p: parser context + * @handle: handle to validate + * + * Validates the handle and return the found session index or -EINVAL + * we we don't have another free session index. + */ +int radeon_vce_validate_handle(struct radeon_cs_parser *p, uint32_t handle) +{ + unsigned i; + + /* validate the handle */ + for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { + if (atomic_read(&p->rdev->vce.handles[i]) == handle) + return i; + } + + /* handle not found try to alloc a new one */ + for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { + if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) { + p->rdev->vce.filp[i] = p->filp; + p->rdev->vce.img_size[i] = 0; + return i; + } + } + + DRM_ERROR("No more free VCE handles!\n"); + return -EINVAL; +} + +/** * radeon_vce_cs_parse - parse and validate the command stream * * @p: parser context @@ -477,8 +525,10 @@ int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi) */ int radeon_vce_cs_parse(struct radeon_cs_parser *p) { - uint32_t handle = 0; - bool destroy = false; + int session_idx = -1; + bool destroyed = false; + uint32_t tmp, handle = 0; + uint32_t *size = &tmp; int i, r; while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) { @@ -490,13 +540,29 @@ int radeon_vce_cs_parse(struct radeon_cs_parser *p) return -EINVAL; } + if (destroyed) { + DRM_ERROR("No other command allowed after destroy!\n"); + return -EINVAL; + } + switch (cmd) { case 0x00000001: // session handle = radeon_get_ib_value(p, p->idx + 2); + session_idx = radeon_vce_validate_handle(p, handle); + if (session_idx < 0) + return session_idx; + size = &p->rdev->vce.img_size[session_idx]; break; case 0x00000002: // task info + break; + case 0x01000001: // create + *size = radeon_get_ib_value(p, p->idx + 8) * + radeon_get_ib_value(p, p->idx + 10) * + 8 * 3 / 2; + break; + case 0x04000001: // config extension case 0x04000002: // pic control case 0x04000005: // rate control @@ -505,23 +571,39 @@ int radeon_vce_cs_parse(struct radeon_cs_parser *p) break; case 0x03000001: // encode - r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9); + r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9, + *size); if (r) return r; - r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11); + r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11, + *size / 3); if (r) return r; break; case 0x02000001: // destroy - destroy = true; + destroyed = true; break; case 0x05000001: // context buffer + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, + *size * 2); + if (r) + return r; + break; + case 0x05000004: // video bitstream buffer + tmp = radeon_get_ib_value(p, p->idx + 4); + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, + tmp); + if (r) + return r; + break; + case 0x05000005: // feedback buffer - r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2); + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, + 4096); if (r) return r; break; @@ -531,33 +613,21 @@ int radeon_vce_cs_parse(struct radeon_cs_parser *p) return -EINVAL; } + if (session_idx == -1) { + DRM_ERROR("no session command at start of IB\n"); + return -EINVAL; + } + p->idx += len / 4; } - if (destroy) { + if (destroyed) { /* IB contains a destroy msg, free the handle */ for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0); - - return 0; - } - - /* create or encode, validate the handle */ - for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { - if (atomic_read(&p->rdev->vce.handles[i]) == handle) - return 0; } - /* handle not found try to alloc a new one */ - for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { - if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) { - p->rdev->vce.filp[i] = p->filp; - return 0; - } - } - - DRM_ERROR("No more free VCE handles!\n"); - return -EINVAL; + return 0; } /** -- 1.9.1 [View Less]

2 1

Atomicity in KMS panic notifier
by Takashi Iwai 07 May '14

07 May '14

Hi, while debugging a few reported bugs, I noticed that drm_fb_helper_force_kernel_mode() that is called in the KMS panic notifier isn't really atomic-safe. It invokes crtc's set_config(), and all implementations seem to involve with page allocations (kmalloc with GFP_KERNEL, via some ttm ops, etc). I've actually seen the Oops with cirrus KMS during panic due to this. Does anyone have an idea to fix this? I thought of re-using drm_fb_helper_debug_enter(), but this won't work with many … [View More]

4 10

[Bug 78297] New: Radeon uvd makes Flash player with VDPAU enabled to crash at vlVdpDecoderCreate
by bugzilla-daemon＠freedesktop.org 07 May '14

07 May '14

https://bugs.freedesktop.org/show_bug.cgi?id=78297 Priority: medium Bug ID: 78297 Assignee: dri-devel(a)lists.freedesktop.org Summary: Radeon uvd makes Flash player with VDPAU enabled to crash at vlVdpDecoderCreate Severity: normal Classification: Unclassified OS: Linux (All) Reporter: mail(a)3v1n0.net Hardware: Other Status: NEW Version: 10.1 … [View More]

1 19

[PATCH] drm/exynos: dp: Use DPCD defines of drm_dp_helper.h
by Jingoo Han 07 May '14

07 May '14

Use DPCD defines of drm_dp_helper.h; thus, duplicated DPCD defines of exynos_dp_core.h can be removed. Also, DP_TEST_EDID_CHECKSUM define is added to drm_dp_helper.h. There is no functional change. Signed-off-by: Jingoo Han <jg1.han(a)samsung.com> --- drivers/gpu/drm/exynos/exynos_dp_core.c | 98 +++++++++++++++---------------- drivers/gpu/drm/exynos/exynos_dp_core.h | 59 ++----------------- include/drm/drm_dp_helper.h | 2 + 3 files changed, 55 insertions(+), 104 … [View More]deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index 64b2dd8..92cfbb3 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -141,15 +141,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) return -EIO; } - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST, + exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector); - if (test_vector & DPCD_TEST_EDID_READ) { + if (test_vector & DP_TEST_LINK_EDID_READ) { exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TEST_EDID_CHECKSUM, + DP_TEST_EDID_CHECKSUM, edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TEST_RESPONSE, - DPCD_TEST_EDID_CHECKSUM_WRITE); + DP_TEST_RESPONSE, + DP_TEST_EDID_CHECKSUM_WRITE); } } else { dev_info(dp->dev, "EDID data does not include any extensions.\n"); @@ -171,15 +171,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp) } exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_TEST_REQUEST, + DP_TEST_REQUEST, &test_vector); - if (test_vector & DPCD_TEST_EDID_READ) { + if (test_vector & DP_TEST_LINK_EDID_READ) { exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TEST_EDID_CHECKSUM, + DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TEST_RESPONSE, - DPCD_TEST_EDID_CHECKSUM_WRITE); + DP_TEST_RESPONSE, + DP_TEST_EDID_CHECKSUM_WRITE); } } @@ -193,8 +193,8 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp) int i; int retval; - /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */ - retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, + /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ + retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); if (retval) return retval; @@ -214,14 +214,14 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, { u8 data; - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data); + exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); if (enable) - exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, - DPCD_ENHANCED_FRAME_EN | + exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, + DP_LANE_COUNT_ENHANCED_FRAME_EN | DPCD_LANE_COUNT_SET(data)); else - exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, + exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, DPCD_LANE_COUNT_SET(data)); } @@ -230,7 +230,7 @@ static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) u8 data; int retval; - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); retval = DPCD_ENHANCED_FRAME_CAP(data); return retval; @@ -250,8 +250,8 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) exynos_dp_set_training_pattern(dp, DP_NONE); exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, - DPCD_TRAINING_PATTERN_DISABLED); + DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_DISABLE); } static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, @@ -295,7 +295,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) /* Setup RX configuration */ buf[0] = dp->link_train.link_rate; buf[1] = dp->link_train.lane_count; - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); if (retval) return retval; @@ -322,16 +322,16 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) /* Set RX training pattern */ retval = exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, - DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1); + DP_TRAINING_PATTERN_SET, + DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); if (retval) return retval; for (lane = 0; lane < lane_count; lane++) - buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | - DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; + buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 | + DP_TRAIN_VOLTAGE_SWING_400; - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, buf); return retval; @@ -352,7 +352,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) for (lane = 0; lane < lane_count; lane++) { lane_status = exynos_dp_get_lane_status(link_status, lane); - if ((lane_status & DPCD_LANE_CR_DONE) == 0) + if ((lane_status & DP_LANE_CR_DONE) == 0) return -EINVAL; } return 0; @@ -364,13 +364,13 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane; u8 lane_status; - if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0) + if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) return -EINVAL; for (lane = 0; lane < lane_count; lane++) { lane_status = exynos_dp_get_lane_status(link_status, lane); - lane_status &= DPCD_CHANNEL_EQ_BITS; - if (lane_status != DPCD_CHANNEL_EQ_BITS) + lane_status &= DP_CHANNEL_EQ_BITS; + if (lane_status != DP_CHANNEL_EQ_BITS) return -EINVAL; } @@ -468,9 +468,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) - training_lane |= DPCD_MAX_SWING_REACHED; + training_lane |= DP_TRAIN_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) - training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; + training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; } @@ -487,12 +487,12 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) lane_count = dp->link_train.lane_count; retval = exynos_dp_read_bytes_from_dpcd(dp, - DPCD_ADDR_LANE0_1_STATUS, 2, link_status); + DP_LANE0_1_STATUS, 2, link_status); if (retval) return retval; retval = exynos_dp_read_bytes_from_dpcd(dp, - DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval) return retval; @@ -501,9 +501,9 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) exynos_dp_set_training_pattern(dp, TRAINING_PTN2); retval = exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, - DPCD_SCRAMBLING_DISABLED | - DPCD_TRAINING_PATTERN_2); + DP_TRAINING_PATTERN_SET, + DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_2); if (retval) return retval; @@ -543,7 +543,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) dp->link_train.training_lane[lane], lane); retval = exynos_dp_write_bytes_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET, lane_count, + DP_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); if (retval) return retval; @@ -562,7 +562,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) lane_count = dp->link_train.lane_count; retval = exynos_dp_read_bytes_from_dpcd(dp, - DPCD_ADDR_LANE0_1_STATUS, 2, link_status); + DP_LANE0_1_STATUS, 2, link_status); if (retval) return retval; @@ -572,12 +572,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) } retval = exynos_dp_read_bytes_from_dpcd(dp, - DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval) return retval; retval = exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align); + DP_LANE_ALIGN_STATUS_UPDATED, &link_align); if (retval) return retval; @@ -619,7 +619,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); return retval; @@ -634,7 +634,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps */ - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; } @@ -647,7 +647,7 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, * For DP rev.1.1, Maximum number of Main Link lanes * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes */ - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); *lane_count = DPCD_MAX_LANE_COUNT(data); } @@ -819,20 +819,20 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) exynos_dp_enable_scrambling(dp); exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_SET, &data); exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); + DP_TRAINING_PATTERN_SET, + (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); } else { exynos_dp_disable_scrambling(dp); exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_SET, &data); exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data | DPCD_SCRAMBLING_DISABLED)); + DP_TRAINING_PATTERN_SET, + (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); } } diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h index d6a900d..6324f51 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.h +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h @@ -14,6 +14,7 @@ #define _EXYNOS_DP_CORE_H #include <drm/drm_crtc.h> +#include <drm/drm_dp_helper.h> #include <drm/exynos_drm.h> #define DP_TIMEOUT_LOOP_COUNT 100 @@ -261,69 +262,17 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp); #define EDID_EXTENSION_FLAG 0x7e #define EDID_CHECKSUM 0x7f -/* Definition for DPCD Register */ -#define DPCD_ADDR_DPCD_REV 0x0000 -#define DPCD_ADDR_MAX_LINK_RATE 0x0001 -#define DPCD_ADDR_MAX_LANE_COUNT 0x0002 -#define DPCD_ADDR_LINK_BW_SET 0x0100 -#define DPCD_ADDR_LANE_COUNT_SET 0x0101 -#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102 -#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103 -#define DPCD_ADDR_LANE0_1_STATUS 0x0202 -#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204 -#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206 -#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207 -#define DPCD_ADDR_TEST_REQUEST 0x0218 -#define DPCD_ADDR_TEST_RESPONSE 0x0260 -#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261 -#define DPCD_ADDR_SINK_POWER_STATE 0x0600 - -/* DPCD_ADDR_MAX_LANE_COUNT */ +/* DP_MAX_LANE_COUNT */ #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) -/* DPCD_ADDR_LANE_COUNT_SET */ -#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) +/* DP_LANE_COUNT_SET */ #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) -/* DPCD_ADDR_TRAINING_PATTERN_SET */ -#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) -#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) -#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) -#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) -#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) - -/* DPCD_ADDR_TRAINING_LANE0_SET */ -#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5) +/* DP_TRAINING_LANE0_SET */ #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) -#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3) -#define DPCD_MAX_SWING_REACHED (0x1 << 2) #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) -#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0) - -/* DPCD_ADDR_LANE0_1_STATUS */ -#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2) -#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1) -#define DPCD_LANE_CR_DONE (0x1 << 0) -#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \ - DPCD_LANE_CHANNEL_EQ_DONE|\ - DPCD_LANE_SYMBOL_LOCKED) - -/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */ -#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) -#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) -#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) - -/* DPCD_ADDR_TEST_REQUEST */ -#define DPCD_TEST_EDID_READ (0x1 << 2) - -/* DPCD_ADDR_TEST_RESPONSE */ -#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) - -/* DPCD_ADDR_SINK_POWER_STATE */ -#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) -#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) #endif /* _EXYNOS_DP_CORE_H */ diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index cfcacec..918a226 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -291,6 +291,8 @@ # define DP_TEST_NAK (1 << 1) # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) +#define DP_TEST_EDID_CHECKSUM 0x261 + #define DP_TEST_SINK 0x270 #define DP_TEST_SINK_START (1 << 0) -- 1.7.10.4 [View Less]

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DPCD/AUX locking
by Dave Airlie 07 May '14

07 May '14

So now I've been playing with MST I think get the feeling I might need some explicit locking on the AUX channel, I think at the moment the mode_config mutex implicitly defends the aux channel as the only real paths into it are a) from userspace connector probing, b) from HPD irqs, currently both of these on i915 at least take mode config, however with MST I can't use mode_config for this, so I'm wondering if I should be adding some explicit locking in the helpers or make it the drivers … [View More]

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[RFC v4 PATCH 00/18] drm/exynos: support MIPI DSI command mode display
by YoungJun Cho 07 May '14

07 May '14

This patch series includes the followings: - Generic command mode interface - FIMD I80 interface - DSI command mode interface for Exynos5420 SoC - S6E3FA0 command mode type panel driver This patch series is based on exynos-drm-next branch. Previous patch set, RFC v1: http://www.spinics.net/lists/dri-devel/msg57513.html RFC v2: http://www.spinics.net/lists/dri-devel/msg57945.html RFC v3: http://www.spinics.net/lists/dri-devel/msg58364.html Changelog v2: - Moves panel delays and size DT … [View More]properties to panel probe routine. - Moves CPU timings relevant DT properties from FIMD to panel DT. Changelog v3: - Splits core and driver patchset. - Renames CPU timings to CPU mode timings. - Enhances panel code readability. Changelog v4: - Implements generic command mode interface. - Adds command mode information to drm_display_mode. - Removes CPU mode timings. Thank you. Best regards YJ YoungJun Cho (18): drm/exynos: dsi: move the EoT packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: video: add command mode display timing DT bindings video: add command mode and command mode display timing drm_modes: add command mode helpers ARM: dts: sysreg: add exynos5 compatible to DT bindings ARM: dts: samsung-fimd: add I80 specific properties drm/exynos: add TE handler to support MIPI DSI command mode interface drm/exynos: dsi: add TE handler to support command mode interface drm/exynos: fimd: support I80 interface ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5420 ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register node ARM: dts: exynos5: add system register support ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/arm/samsung/sysreg.txt | 1 + .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 45 ++ .../bindings/video/cmdmode-display-timing.txt | 64 +++ .../devicetree/bindings/video/exynos_dsim.txt | 4 +- .../devicetree/bindings/video/samsung-fimd.txt | 2 + arch/arm/boot/dts/exynos4.dtsi | 1 + arch/arm/boot/dts/exynos5.dtsi | 6 + arch/arm/boot/dts/exynos5420.dtsi | 21 + drivers/gpu/drm/drm_modes.c | 59 ++ drivers/gpu/drm/exynos/Kconfig | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 16 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 + drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 175 +++++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 277 ++++++++-- drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 570 ++++++++++++++++++++ drivers/video/Kconfig | 3 + drivers/video/Makefile | 2 + drivers/video/cmdmode.c | 42 ++ drivers/video/cmdmode_display_timing.c | 26 + drivers/video/of_cmdmode.c | 55 ++ drivers/video/of_cmdmode_display_timing.c | 212 ++++++++ include/drm/drm_mipi_dsi.h | 8 + include/drm/drm_modes.h | 12 + include/video/cmdmode.h | 67 +++ include/video/cmdmode_display_timing.h | 59 ++ include/video/of_cmdmode.h | 19 + include/video/of_cmdmode_display_timing.h | 26 + include/video/samsung_fimd.h | 3 +- 31 files changed, 1723 insertions(+), 71 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 Documentation/devicetree/bindings/video/cmdmode-display-timing.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c create mode 100644 drivers/video/cmdmode.c create mode 100644 drivers/video/cmdmode_display_timing.c create mode 100644 drivers/video/of_cmdmode.c create mode 100644 drivers/video/of_cmdmode_display_timing.c create mode 100644 include/video/cmdmode.h create mode 100644 include/video/cmdmode_display_timing.h create mode 100644 include/video/of_cmdmode.h create mode 100644 include/video/of_cmdmode_display_timing.h -- 1.7.9.5 [View Less]

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[PULL] drm-intel-next
by Daniel Vetter 07 May '14

07 May '14

Hi Dave, drm-intel-next-2014-04-16: - vlv infoframe fixes from Jesse - dsi/mipi fixes from Shobhit - gen8 pageflip fixes for LRI/SRM from Damien - cmd parser fixes from Brad Volkin - some prep patches for CHV, DRRS, ... - and tons of little things all over drm-intel-next-2014-04-04: - cmd parser for gen7 but only in enforcing and not yet granting mode - the batch copying stuff is still missing. Also performance is a bit ... rough (Brad Volkin + OACONTROL fix from Ken). - deprecate UMS … [View More]harder (i.e. CONFIG_BROKEN) - interrupt rework from Paulo Zanoni - runtime PM support for bdw and snb, again from Paulo - a pile of refactorings from various people all over the place to prep for new stuff (irq reworks, power domain polish, ...) drm-intel-next-2014-04-04: - cmd parser for gen7 but only in enforcing and not yet granting mode - the batch copying stuff is still missing. Also performance is a bit ... rough (Brad Volkin + OACONTROL fix from Ken). - deprecate UMS harder (i.e. CONFIG_BROKEN) - interrupt rework from Paulo Zanoni - runtime PM support for bdw and snb, again from Paulo - a pile of refactorings from various people all over the place to prep for new stuff (irq reworks, power domain polish, ...) As discussed on irc this contains a (not yet fully tuned and also not yet in granting mode) cmd parser for gen7. Performance is still a bit rough, but not quite as bad as originally feared (Ken later on discovered that he also changed something in his glamour setup which made things worse). If it doesn't get better (and ofc if we don't get all the missing bits in for granting mode) I'll disable it before 3.16 again. But I want to give this beast as much testing as possible for now to avoid ugly regressions once we switch it on. Also please don't use the autogenerate merge commit since that'll miss the stuff from the 1st drm-intel-next tag. If I read the merges in -nightly correctly there's a bit a conflict in i915_gem_context.c. I can provide an example merge if you want (or otherwise just peak at linux-next or drm-intel-nightly). Cheers, Daniel The following changes since commit c39b06951f1dc2e384650288676c5b7dcc0ec92c: DRM: armada: fix corruption while loading cursors (2014-04-08 10:51:03 +1000) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-2014-04-16 for you to fetch changes up to c79057922ed6c2c6df1214e6ab4414fea1b23db2: drm/i915: Remove vblank wait from haswell_write_eld (2014-04-16 18:52:47 +0200) ---------------------------------------------------------------- - vlv infoframe fixes from Jesse - dsi/mipi fixes from Shobhit - gen8 pageflip fixes for LRI/SRM from Damien - cmd parser fixes from Brad Volkin - some prep patches for CHV, DRRS, ... - and tons of little things all over ---------------------------------------------------------------- Akash Goel (2): drm/i915: Enabling the TLB invalidate bit in GFX Mode register drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' Ben Widawsky (10): drm/i915: Split out GTT specific header file drm/i915: Allow full PPGTT with param override drm/i915/bdw: Set initial rps freq to RP1 drm/i915/bdw: Extract rp_state_caps logic drm/i915/bdw: RPS frequency bits are the same as HSW drm/i915/bdw: Expand FADD to 64bit drm/i915: Invariably invalidate before ctx switch drm/i915: Unref context on failed eb_create drm/i915: Dump the whole context object. drm/i915/bdw: Add 42ms delay for IPS disable Brad Volkin (15): drm/i915: Initial command parser table definitions drm/i915: Reject privileged commands drm/i915: Allow some privileged commands from master drm/i915: Add register whitelists for mesa drm/i915: Add register whitelist for DRM master drm/i915: Enable register whitelist checks drm/i915: Reject commands that explicitly generate interrupts drm/i915: Enable PPGTT command parser checks drm/i915: Reject commands that would store to global HWS page drm/i915: Add a CMD_PARSER_VERSION getparam drm/i915: Enable command parsing by default drm/i915: BUG_ON() when cmd/reg tables are not sorted drm/i915: Refactor cmd parser checks into a function drm/i915: Track OACONTROL register enable/disable during parsing drm/i915: Add more registers to the whitelist for mesa Chris Wilson (4): drm/i915: Rename GFX_TLB_INVALIDATE_ALWAYS drm/i915: Add PM interrupt details and RPS thresholds to debugfs drm/i915: Move all ring resets before setting the HWS page drm/i915: dma_buf_vunmap is presumed not to fail, don't let it Christoph Jaeger (1): drm/i915: drop __FUNCTION__ as argument to DRM_DEBUG_KMS Damien Lespiau (10): drm/i915: Don't store the max cursor width/height in the crtc drm/i915: Hide vlv_force_wake_{get, put}() in intel_uncore.c drm/i915: Hide the per forcewake-engine register ranges drm/i915: Use a macro to express the range of valid gens for reg_read drm/i915: Protect the argument expansion in LRI and SRM macros drm/i915/bdw: Provide a gen8 version of SRM drm/i915/bdw: Use the GEN8 SRM when qeueing a flip drm/i915: Rename GEN8_PIPE_FLIP_DONE to PRIMARY_FLIP_DONE drm/i915: Remove misleading debug message drm/i915: Remove spurious semicolons Daniel Vetter (10): drm/i915: Add FIXME for bdw semaphore detection in hancheck drm/i915: make semaphore signaller detection more robust drm/i915: Deprecate UMS harder drm/i915: Add debug module option for VTd validation drm/i915: dmesg output for VT-d testing Merge remote-tracking branch 'airlied/drm-next' into HEAD Revert "drm/i915: fix infinite loop at gen6_update_ring_freq" drm/i915: Don't set the 8to6 dither flag when not scaling drm/i915: Don't vblank wait on ilk-ivb after pipe enable drm/i915: Remove vblank wait from haswell_write_eld Deepak S (1): drm/i915: Match debugfs interface name to new RPS naming Egbert Eich (1): drm/i915/SDVO: For sysfs link put directory and target in correct order Imre Deak (2): drm/i915: vlv: cache current CD clock rate drm/i915: vlv: get power domain for eDP vdd Jani Nikula (2): drm/i915: drop the typedef for drm_i915_private_t drm/i915: fix command parser debug print format mismatches Jesse Barnes (5): drm/i915: warn when a vblank wait times out drm/i915/vlv: write the port field in the per-pipe DIP control reg drm/i915/vlv: disable AVI infoframe emission when writing infoframes drm/i915: enable HDMI mode on VLV when an HDMI sink is detected drm/i915: move infoframe setting to after pll enable v3 Kenneth Graunke (1): drm/i915: Add OACONTROL to the command parser register whitelist. Mika Kuoppala (1): drm/i915: add flags to i915_ring_stop Paulo Zanoni (27): drm/i915: add GEN5_IRQ_INIT macro drm/i915: also use GEN5_IRQ_INIT with south display interrupts drm/i915: use GEN8_IRQ_INIT on GEN5 drm/i915: add GEN5_IRQ_FINI drm/i915: don't forget to uninstall the PM IRQs drm/i915: properly clear IIR at irq_uninstall on Gen5+ drm/i915: add GEN5_IRQ_INIT drm/i915: check if IIR is still zero at postinstall on Gen5+ drm/i915: fix SERR_INT init/reset code drm/i915: fix GEN7_ERR_INT init/reset code drm/i915: fix open coded gen5_gt_irq_preinstall drm/i915: extract ibx_irq_uninstall drm/i915: call ibx_irq_uninstall from gen8_irq_uninstall drm/i915: enable SDEIER later drm/i915: remove ibx_irq_uninstall drm/i915: add missing intel_hpd_irq_uninstall drm/i915: add ironlake_irq_reset drm/i915: add gen8_irq_reset drm/i915: only enable HWSTAM interrupts on postinstall on ILK+ drm/i915: kill dev_priv->pm.regsave drm/i915: add gen-specific runtime suspend/resume functions drm/i915: add SNB runtime PM support drm/i915: remove HAS_PC8 check drm/i915: BDW needs D_COMP writes through MCHBAR drm/i915: add BDW runtime PM support drm/i915: only check for irqs_disabled when disabling LCPLL drm/i915: fix infinite loop at gen6_update_ring_freq Pradeep Bhat (3): drm/i915: Adding VBT fields to support eDP DRRS feature drm/i915: Parse EDID probed modes for DRRS support drm/i915: Add support for DRRS to switch RR Rafael Barbalho (1): drm/i915: Fix framecount offset Shobhit Kumar (9): drm/i915: Program Rcomp and band gap reset everytime we resume from power gate drm/i915: Enable MIPI port before the plane and pipe enable drm/i915: Disable DPOunit clock gating drm/i915: Parameterize the Clockstop and escape_clk_div drm/i915: Panel commands can be sent only when clock is in LP11 drm/i915: Send DPI command explicitely in LP mode drm/i915: Enable RANDOM resolution support for MIPI panels drm/i915: Add parsing support for new MIPI blocks in VBT drm/i915: Code cleanup patch to fix checkpatch errors Ville Syrjälä (17): drm/i915: Kill crtc->plane checks from the primary plane update hooks drm/i915: Split dp post_disable hooks drm/i915: Refactor gmch hpd irq handling drm: Make drm_clflush_virt_range() void* drm/i915: Implement WaProgramMiArbOnOffAroundMiSetContext:bdw drm/i915: Fix debugfs PDP register dump drm/i915: Move DP M/N setup from update_pll to mode_set for gmch platforms drm/i915: Warn when DPIO read returns 0xffffffff drm/i915: Provide a bit more info when pipestat bits are wrong drm/i915: Make contexts non-snooped on non-LLC platforms drm/i915: Don't read sprite LP2+ registers on ILK/SNB drm/i915: Add some more tracked state to intel_pipe_wm drm/i915: Skip watermark merging for inactive pipes drm/i916: Refactor WM register maximums drm/i915/chv: IS_BROADWELL() should not be true for Cherryview drm/i915/chv: Add IS_CHERRYVIEW() macro drm/i915: Disable/enable planes as the first/last thing during modeset on ILK+ Zhenyu Wang (1): drm/i915: Allow i915_pc8_status debug info on BDW drivers/gpu/drm/drm_cache.c | 4 +- drivers/gpu/drm/i915/Kconfig | 2 +- drivers/gpu/drm/i915/dvo_ch7xxx.c | 2 +- drivers/gpu/drm/i915/dvo_ivch.c | 2 +- drivers/gpu/drm/i915/dvo_ns2501.c | 24 +- drivers/gpu/drm/i915/dvo_sil164.c | 2 +- drivers/gpu/drm/i915/dvo_tfp410.c | 2 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 616 +++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_debugfs.c | 25 +- drivers/gpu/drm/i915/i915_dma.c | 3 + drivers/gpu/drm/i915/i915_drv.c | 53 ++- drivers/gpu/drm/i915/i915_drv.h | 265 +++---------- drivers/gpu/drm/i915/i915_gem.c | 5 +- drivers/gpu/drm/i915/i915_gem_context.c | 18 +- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 6 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 75 +--- drivers/gpu/drm/i915/i915_gem_gtt.h | 283 +++++++++++++ drivers/gpu/drm/i915/i915_gpu_error.c | 23 +- drivers/gpu/drm/i915/i915_irq.c | 504 +++++++++++------------ drivers/gpu/drm/i915/i915_params.c | 8 +- drivers/gpu/drm/i915/i915_reg.h | 117 +++++- drivers/gpu/drm/i915/intel_bios.c | 242 +++++++++++- drivers/gpu/drm/i915/intel_bios.h | 60 +++ drivers/gpu/drm/i915/intel_display.c | 283 ++++++------- drivers/gpu/drm/i915/intel_dp.c | 197 ++++++++- drivers/gpu/drm/i915/intel_drv.h | 35 +- drivers/gpu/drm/i915/intel_dsi.c | 125 ++++-- drivers/gpu/drm/i915/intel_dsi.h | 4 +- drivers/gpu/drm/i915/intel_dsi_cmd.c | 4 +- drivers/gpu/drm/i915/intel_dsi_cmd.h | 5 +- drivers/gpu/drm/i915/intel_hdmi.c | 38 +- drivers/gpu/drm/i915/intel_lvds.c | 7 - drivers/gpu/drm/i915/intel_panel.c | 8 +- drivers/gpu/drm/i915/intel_pm.c | 219 ++++++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 75 ++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +- drivers/gpu/drm/i915/intel_sdvo.c | 4 +- drivers/gpu/drm/i915/intel_sideband.c | 8 + drivers/gpu/drm/i915/intel_uncore.c | 24 +- include/drm/drmP.h | 2 +- include/uapi/drm/i915_drm.h | 1 + 42 files changed, 2354 insertions(+), 1034 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_gtt.h -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch [View Less]

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dri-devel May 2014