dri-devel October 2015

dri-devel@lists.freedesktop.org

201 participants
1170 discussions

[PATCH] drm: sti: fix typos in stih4xx binding
by Michael Opdenacker 13 Oct '15

13 Oct '15

Fix typos in the st,stih4xx binding, in particular replacing "pinctrl-name" by "pinctrl-names". Fix minor typos in the descriptions too. Signed-off-by: Michael Opdenacker <michael.opdenacker(a)free-electrons.com> --- Documentation/devicetree/bindings/gpu/st,stih4xx.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt index a36dfce0032e..a352ed30cd70 100644 --- a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt +++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt @@ -61,7 +61,7 @@ STMicroelectronics stih4xx platforms - reg-names: names of the mapped memory regions listed in regs property in the same order. - interrupts : HDMI interrupt number to the CPU. - - interrupt-names: name of the interrupts listed in interrupts property in + - interrupt-names: names of the interrupts listed in interrupts property in the same order - clocks: from common clock binding: handle hardware IP needed clocks, the number of clocks may depend of the SoC type. @@ -95,7 +95,7 @@ sti-dvo: - clock-names: names of the clocks listed in clocks property in the same order. - pinctrl-0: pin control handle - - pinctrl-name: names of the pin control to use + - pinctrl-names: names of the pin control states to use - sti,panel: phandle of the panel connected to the DVO output sti-hqvdp: -- 2.1.4

2 1

[Bug 92427] [HSW] deqp-gles3 functional / shaders is having a lot of failures in different sub tests
by bugzilla-daemon＠freedesktop.org 13 Oct '15

13 Oct '15

https://bugs.freedesktop.org/show_bug.cgi?id=92427 Bug ID: 92427 Summary: [HSW] deqp-gles3 functional / shaders is having a lot of failures in different sub tests Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/i830 Assignee: dri-devel(a)lists.freedesktop.org Reporter: elio.martinez.monroy(a)intel.com QA Contact: dri-devel(a)lists.freedesktop.org Created attachment 118820 --> https://bugs.freedesktop.org/attachment.cgi?id=118820&action=edit Dmesg log Test Enviroment: kernel: 4.3.0 Mesa: (11.2)git- Xf86_video_intel:2.99.917 Libdrm:libdrm-2.4.65 Libva: 1.6.1 vaapi-in tel-driver: 1.6.1 Cairo: 1.14.2 Xserver: xorg-server-latests Hardware: Hardware Platform: Intel NUC D54250WYK Processor Intel Core I5-425OU 1.30 GHz Software Linux distribution: Ubuntu 14.04 LTS 64Bits BIOS: WTLPT10H.86A.0021.2013.1.017.1606 Steps to reproduce: Install Graphic stack with configuration mentioned before. Install deqp tool. Execute: sudo ./deqp-gles3 --deqp-case=dEQP-GLES3.functional.clipping. Actual result: -------------- Test <% eqp-gles3@functional@shaders@arrays@invalid@empty_declaration_without_var_name_vertex Fail new EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@acos@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@asin@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@lowp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@mediump_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@mediump_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@mediump_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan2@mediump_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@atan@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@cos@mediump_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@lowp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@mix@mediump_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@highp_fragment Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@highp_vertex Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@lowp_fragment Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@lowp_vertex Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@mediump_fragment Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@modf@mediump_vertex Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@reflect@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@reflect@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@sin@mediump_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tan@mediump_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_fragment@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_fragment@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_fragment@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_fragment@vec4 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_vertex@scalar Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_vertex@vec2 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_vertex@vec3 Fail EditRemove deqp-gles3@functional@shaders@builtin_functions@precision@tanh@highp_vertex@vec4 Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec2_highp Fail new EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec2_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec2_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec3_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec3_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec3_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec4_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec4_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fastest@fbo_float@vec4_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec2_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec2_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec2_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec3_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec3_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec3_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec4_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec4_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@fbo_float@vec4_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec2_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec2_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec2_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec3_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec3_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec3_mediump Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec4_highp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec4_lowp Fail EditRemove deqp-gles3@functional@shaders@derivate@dfdx@nicest@fbo_float@vec4_mediump Fail EditRemove deqp-gles3@functional@shaders@fragdata@draw_buffers Fail EditRemove deqp-gles3@functional@shaders@fragdata@invalid_assign_to_1 Fail %> fail Expected result: ----------------- Test Passes -- You are receiving this mail because: You are the assignee for the bug.

1 1

[PATCH 00/22] Color Management for DRM
by Shashank Sharma 13 Oct '15

13 Oct '15

This patch set adds Color Manager implementation in DRM layer. Color Manager is an extension in DRM framework to support color correction/enhancement. Various Hardware platforms can support several color correction capabilities. Color Manager provides abstraction of these capabilities and allows a user space UI agent to correct/enhance the display using the DRM property interface. How is this going to work? ========================== 1. This patch series adds a few new properties in DRM framework. These properties are: a. color_capabilities property (type blob) b. Color Transformation Matrix property for corrections like CSC (called CTM, type blob) c. Palette correction properties for corrections like gamma fixup (called palette_correction, type blob) 2. Also, this patch series adds few structures to indicate specifications of a property like size, no_of_samples for correction etc. 3. These properties are present in mode_config. 4. When the platform's display driver loads, it fills up the values of color_capabilities property using the standard structures (added in step 2). For example, Intel's I915 driver adds following color correction capabilities: a. gamma correction capability as palette correction property, with 257 correction coefficients and a max/min value b. csc correction capability as CTM correction property, with 3x3 transformation matrix values and max/min values 5. Now when userspace comes up, it queries the platform's color capabilities by doing a get_property() on color_capabilities DRM property 6. Reading the blob, the userspace understands the color capabilities of the platform. For example, userspace will understand it can support: a. palette_correction with 257 coefficients b. CSC correction with 3x3 = 9 values 7. To set color correction values, userspace: a. creates a blob using the create_blob_ioctl in standard palette_correction structure format, with the correction values b. calls the set_property_ioctl with the blob_id as value for the property 8. Driver refers to the blob, gets the correction values and applies the correction in HW. 9. To get currently applied color correction values, userspace: a. calls a get_property_ioctl on that color property b. gets the blob_id for the currently applied correction from DRM infrastructure c. gets the blob using get_blob_ioctl and hence the currently applied values That's all! :) About the patch series: ======================= The patch series first adds the color management support in DRM layer. Then it adds the color management framework in I915 layer. After that, it implements platform specific core color correction functios. Intel color manager registers color correction with DRM color manager in this way: - CSC transformation is registered as CTM DRM property - Gamma correction is registered as palette_after_ctm DRM property - Degamma correction is registered as palette_before_ctm DRM property Our thanks to all the reviewers who have given valuable comments in terms of design and implementation to our previous sets of patches. Special mention of thanks should go to Matt Roper for all his inputs/suggestions in implementation of this module, using DRM atomic CRTC commit path. V2: Worked on review comments from Matt, Jim, Thierry, Rob. V3: Worked on review comments from Matt, Jim, Rob: - Jim, Rob: ======== Re-arranged the whole patch series in the sequence of features, currently: First 5 patches add color management support in DRM layer Next 7 patches add Intel color management framework in I915 driver Next 5 patches add color correction for CHV (gamma, degamma and CSC) Next 2 patches enable color management, by attaching the properties to CRTC(Matt) Next 4 patches add color correction for BDW (gamma, degamma) - Matt: ===== Patch 3: Added refernce/unreference for blob Patch 7: return -EINVAL and added debug message Patch 8: check for valid blob, from create blob moved call to intel_crtc_attach_color_prop in the end of full implementation (CHV) Patch 9: DRM_ERROR->DRM_DEBUG for NULL blob case Patch 13: Added static for internal functions Patch 20-24: renamed gen9_* functions to bdw_* Added new variables in device_info structure num_samples_after_ctm and num_samples_before_ctm Added new function in patch 8 to load capabilities based on device_info across all platforms V4: Worked on review comments from Daniel, Matt, Rob, Jim - Rob, Jim: ========= Patch 15, 22: Prepare CSC coeff properly(chv, bdw). Patch 13, 20: Gamma max should be (1<<24) -1(chv, bdw). - Daniel, Matt: ============= Patch 2: Create separate properties to query color capabilities, not a single blob. Patch 4, 5, 10: Add set/get property interface in DRM layer, not in I915 layer. Shashank Sharma (22): drm: Create Color Management DRM properties drm: Create Color Management query properties drm: Add color correction blobs in CRTC state drm: Add set property support for color manager drm: Add get property support for color manager drm: Add drm structures for palette color property drm: Add structure to set/get a CTM color property drm/i915: Add set property interface for CRTC drm/i915: Create color management files drm/i915: Register color correction capabilities drm/i915: CHV: Load gamma color correction values drm/i915: CHV: Load degamma color correction values drm/i915: CHV: Pipe level Gamma correction drm/i915: CHV: Pipe level degamma correction drm/i915: CHV: Pipe level CSC correction drm/i915: Commit color correction to CRTC drm/i915: Attach color properties to CRTC drm/i915: BDW: Load gamma correction values drm/i915: BDW: Pipe level Gamma correction drm/i915: BDW: Load degamma correction values drm/i915: BDW: Pipe level degamma correction drm/i915: BDW: Pipe level CSC correction drivers/gpu/drm/drm_atomic.c | 61 ++- drivers/gpu/drm/drm_atomic_helper.c | 12 + drivers/gpu/drm/drm_crtc.c | 32 ++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.c | 17 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 58 +- drivers/gpu/drm/i915/intel_color_manager.c | 825 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 111 ++++ drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_drv.h | 5 + include/drm/drm_crtc.h | 14 + include/uapi/drm/drm.h | 36 ++ 13 files changed, 1175 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h -- 1.9.1

5 76

[PATCH 2/3] of: add URT UMSH-8596MD-xT panel DT bindings
by Maciej S. Szmigiero 13 Oct '15

13 Oct '15

This patch adds DT bindings for United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panels. Signed-off-by: Maciej Szmigiero <mail(a)maciej.szmigiero.name> --- Documentation/devicetree/bindings/panel/urt,umsh-8596md.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/urt,umsh-8596md.txt diff --git a/Documentation/devicetree/bindings/panel/urt,umsh-8596md.txt b/Documentation/devicetree/bindings/panel/urt,umsh-8596md.txt new file mode 100644 index 0000000..57c5fa4 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/urt,umsh-8596md.txt @@ -0,0 +1,12 @@ +United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panel + +Supported are LVDS versions (-11T, -19T) and parallel ones +(-T, -1T, -7T, -20T). + +Required properties: +- compatible: should be one of: + "urt,umsh-8596md-t", "urt,umsh-8596md-1t", "urt,umsh-8596md-7t", + "urt,umsh-8596md-11t", "urt,umsh-8596md-19t" or "urt,umsh-8596md-20t". + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory.

3 2

[PATCH v5 00/22] Color Management for DRM
by Shashank Sharma 13 Oct '15

13 Oct '15

This patch set adds Color Manager implementation in DRM layer. Color Manager is an extension in DRM framework to support color correction/enhancement. Various Hardware platforms can support several color correction capabilities. Color Manager provides abstraction of these capabilities and allows a user space UI agent to correct/enhance the display using the DRM property interface. How is this going to work? ========================== 1. This patch series adds a few new properties in DRM framework. These properties are: a. color_capabilities property (type blob) b. Color Transformation Matrix property for corrections like CSC (called CTM, type blob) c. Palette correction properties for corrections like gamma fixup (called palette_correction, type blob) 2. Also, this patch series adds few structures to indicate specifications of a property like size, no_of_samples for correction etc. 3. These properties are present in mode_config. 4. When the platform's display driver loads, it fills up the values of color_capabilities property using the standard structures (added in step 2). For example, Intel's I915 driver adds following color correction capabilities: a. gamma correction capability as palette correction property, with 257 correction coefficients and a max/min value b. csc correction capability as CTM correction property, with 3x3 transformation matrix values and max/min values 5. Now when userspace comes up, it queries the platform's color capabilities by doing a get_property() on color_capabilities DRM property 6. Reading the blob, the userspace understands the color capabilities of the platform. For example, userspace will understand it can support: a. palette_correction with 257 coefficients b. CSC correction with 3x3 = 9 values 7. To set color correction values, userspace: a. creates a blob using the create_blob_ioctl in standard palette_correction structure format, with the correction values b. calls the set_property_ioctl with the blob_id as value for the property 8. Driver refers to the blob, gets the correction values and applies the correction in HW. 9. To get currently applied color correction values, userspace: a. calls a get_property_ioctl on that color property b. gets the blob_id for the currently applied correction from DRM infrastructure c. gets the blob using get_blob_ioctl and hence the currently applied values That's all! :) About the patch series: ======================= The patch series first adds the color management support in DRM layer. Then it adds the color management framework in I915 layer. After that, it implements platform specific core color correction functios. Intel color manager registers color correction with DRM color manager in this way: - CSC transformation is registered as CTM DRM property - Gamma correction is registered as palette_after_ctm DRM property - Degamma correction is registered as palette_before_ctm DRM property Our thanks to all the reviewers who have given valuable comments in terms of design and implementation to our previous sets of patches. Special mention of thanks should go to Matt Roper for all his inputs/suggestions in implementation of this module, using DRM atomic CRTC commit path. V2: Worked on review comments from Matt, Jim, Thierry, Rob. V3: Worked on review comments from Matt, Jim, Rob: - Jim, Rob: ======== Re-arranged the whole patch series in the sequence of features, currently: First 5 patches add color management support in DRM layer Next 7 patches add Intel color management framework in I915 driver Next 5 patches add color correction for CHV (gamma, degamma and CSC) Next 2 patches enable color management, by attaching the properties to CRTC(Matt) Next 4 patches add color correction for BDW (gamma, degamma) - Matt: ===== Patch 3: Added refernce/unreference for blob Patch 7: return -EINVAL and added debug message Patch 8: check for valid blob, from create blob moved call to intel_crtc_attach_color_prop in the end of full implementation (CHV) Patch 9: DRM_ERROR->DRM_DEBUG for NULL blob case Patch 13: Added static for internal functions Patch 20-24: renamed gen9_* functions to bdw_* Added new variables in device_info structure num_samples_after_ctm and num_samples_before_ctm Added new function in patch 8 to load capabilities based on device_info across all platforms V4: Worked on review comments from Daniel, Matt, Rob, Jim - Rob, Jim: ========= Patch 15, 22: Prepare CSC coeff properly(chv, bdw). Patch 13, 20: Gamma max should be (1<<24) -1(chv, bdw). - Daniel, Matt: ============= Patch 2: Create separate properties to query color capabilities, not a single blob. Patch 4, 5, 10: Add set/get property interface in DRM layer, not in I915 layer. V5: Addressed review comments from Emil, Rob. -Emil: ====== Patch 3: Fixed changes from patch 2, which were merged in patch 3 Patch 4: Added static for drm_atomic_crtc_set_blob Patch 13: Removed unnecessary initialization for various functions Patch 14: Removed unnecessary initialization for variables Checked for overflow for length Dropped variable ret, using direct returns instead Patch 15: Fixed type of return value of function chv_prepare_csc_coeff Fixed the type of variable csc_s3_12_format Changed the looping approach to write csc coefficients Patch 16: Fixed typo in intel_drv.h (intel_color_manager.c) Patch 19: Made bdw_write_12_bit_gamma_precision function static Fixed alignment problems with debug message Patch 21: Fixed indentation of debug message Patch 22: Removed change which belonged to another patch Made function bdw_set_csc static -Rob: ====== Patch 19: Clipped -> Clamped SET_BITS in 10bit gamma was taking red_fraction variable for all channels, fixed that. Added check for MAX values in 12_bit_gamma function Added new function for 8_bit_gamma mode (legacy) with MAX value checks Patch 20: Fixed commit message (BDW degamma values was mentioned as 65 in it). Patch 21: Removed unused length variable Moved mode variable closer to a place where its being used Removed cast for correction_values DeGamma -> degamma Shashank Sharma (22): drm: Create Color Management DRM properties drm: Create Color Management query properties drm: Add color correction blobs in CRTC state drm: Add set property support for color manager drm: Add get property support for color manager drm: Add drm structures for palette color property drm: Add structure to set/get a CTM color property drm/i915: Add set property interface for CRTC drm/i915: Create color management files drm/i915: Register color correction capabilities drm/i915: CHV: Load gamma color correction values drm/i915: CHV: Load degamma color correction values drm/i915: CHV: Pipe level Gamma correction drm/i915: CHV: Pipe level degamma correction drm/i915: CHV: Pipe level CSC correction drm/i915: Commit color correction to CRTC drm/i915: Attach color properties to CRTC drm/i915: BDW: Load gamma correction values drm/i915: BDW: Pipe level Gamma correction drm/i915: BDW: Load degamma correction values drm/i915: BDW: Pipe level degamma correction drm/i915: BDW: Pipe level CSC correction drivers/gpu/drm/drm_atomic.c | 61 ++- drivers/gpu/drm/drm_atomic_helper.c | 12 + drivers/gpu/drm/drm_crtc.c | 32 ++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.c | 17 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 58 +- drivers/gpu/drm/i915/intel_color_manager.c | 850 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 111 ++++ drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_drv.h | 5 + include/drm/drm_crtc.h | 14 + include/uapi/drm/drm.h | 36 ++ 13 files changed, 1200 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_color_manager.c create mode 100644 drivers/gpu/drm/i915/intel_color_manager.h -- 1.9.1

1 22

[PATCH] drm/exynos/gem: remove DMA-mapping hacks used for constructing page array
by Marek Szyprowski 13 Oct '15

13 Oct '15

Exynos GEM objects contains an array of pointers to the pages, which the allocated buffer consists of. Till now the code used some hacks (like relying on DMA-mapping internal structures or using ARM-specific dma_to_pfn helper) to build this array. This patch fixes this by adding proper call to dma_get_sgtable_attrs() and using the acquired scatter-list to construct needed array. This approach is more portable (work also for ARM64) and finally fixes the layering violation that was present in this code. Signed-off-by: Marek Szyprowski <m.szyprowski(a)samsung.com> --- Patch is based on exynos-drm-next branch. --- drivers/gpu/drm/exynos/exynos_drm_gem.c | 60 +++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index 29f48756e72f..e998a64a3dd0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -25,6 +25,10 @@ static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem) struct drm_device *dev = exynos_gem->base.dev; enum dma_attr attr; unsigned int nr_pages; + struct sg_table sgt; + struct scatterlist *s; + int ret = -ENOMEM; + int i, j; if (exynos_gem->dma_addr) { DRM_DEBUG_KMS("already allocated.\n"); @@ -56,13 +60,10 @@ static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem) nr_pages = exynos_gem->size >> PAGE_SHIFT; - if (!is_drm_iommu_supported(dev)) { - exynos_gem->pages = drm_calloc_large(nr_pages, - sizeof(struct page *)); - if (!exynos_gem->pages) { - DRM_ERROR("failed to allocate pages.\n"); - return -ENOMEM; - } + exynos_gem->pages = drm_calloc_large(nr_pages, sizeof(struct page *)); + if (!exynos_gem->pages) { + DRM_ERROR("failed to allocate pages.\n"); + return -ENOMEM; } exynos_gem->cookie = dma_alloc_attrs(dev->dev, exynos_gem->size, @@ -70,30 +71,40 @@ static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem) &exynos_gem->dma_attrs); if (!exynos_gem->cookie) { DRM_ERROR("failed to allocate buffer.\n"); - if (exynos_gem->pages) - drm_free_large(exynos_gem->pages); - return -ENOMEM; + goto err_free; } - if (exynos_gem->pages) { - dma_addr_t start_addr; - unsigned int i = 0; - - start_addr = exynos_gem->dma_addr; - while (i < nr_pages) { - exynos_gem->pages[i] = - pfn_to_page(dma_to_pfn(dev->dev, start_addr)); - start_addr += PAGE_SIZE; - i++; - } - } else { - exynos_gem->pages = exynos_gem->cookie; + ret = dma_get_sgtable_attrs(dev->dev, &sgt, exynos_gem->cookie, + exynos_gem->dma_addr, exynos_gem->size, + &exynos_gem->dma_attrs); + if (ret < 0) { + DRM_ERROR("failed to get sgtable.\n"); + goto err_dma_free; + } + + j = 0; + for_each_sg(sgt.sgl, s, sgt.orig_nents, i) { + int size = s->length >> PAGE_SHIFT; + struct page *page = sg_page(s); + + while (size-- > 0) + exynos_gem->pages[j++] = page++; } + sg_free_table(&sgt); + DRM_DEBUG_KMS("dma_addr(0x%lx), size(0x%lx)\n", (unsigned long)exynos_gem->dma_addr, exynos_gem->size); return 0; + +err_dma_free: + dma_free_attrs(dev->dev, exynos_gem->size, exynos_gem->cookie, + exynos_gem->dma_addr, &exynos_gem->dma_attrs); +err_free: + drm_free_large(exynos_gem->pages); + + return ret; } static void exynos_drm_free_buf(struct exynos_drm_gem *exynos_gem) @@ -112,8 +123,7 @@ static void exynos_drm_free_buf(struct exynos_drm_gem *exynos_gem) (dma_addr_t)exynos_gem->dma_addr, &exynos_gem->dma_attrs); - if (!is_drm_iommu_supported(dev)) - drm_free_large(exynos_gem->pages); + drm_free_large(exynos_gem->pages); } static int exynos_drm_gem_handle_create(struct drm_gem_object *obj, -- 1.9.2

2 2

[PATCH] MAINTAINERS: add maintainer for the atmel-hlcdc DRM driver
by Boris Brezillon 13 Oct '15

13 Oct '15

Add myself as the maintainer of the atmel-hlcdc DRM driver. Signed-off-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 797236b..11173b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3591,6 +3591,13 @@ F: drivers/gpu/drm/i915/ F: include/drm/i915* F: include/uapi/drm/i915* +DRM DRIVERS FOR ATMEL_AT91 +M: Boris Brezillon <boris.brezillon(a)free-electrons.com> +L: dri-devel(a)lists.freedesktop.org +S: Supported +F: drivers/gpu/drm/atmel-hlcdc/ +F: Documentation/devicetree/bindings/drm/atmel/ + DRM DRIVERS FOR EXYNOS M: Inki Dae <inki.dae(a)samsung.com> M: Joonyoung Shim <jy0922.shim(a)samsung.com> -- 2.1.4

3 2

[PATCH] Fixed several comment coding style blasphemies.
by Michal Hrbek 13 Oct '15

13 Oct '15

Signed-off-by: Michal Hrbek <hrbmich(a)gmail.com> --- drivers/gpu/vga/vgaarb.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c index a0b4334..41f3e13 100644 --- a/drivers/gpu/vga/vgaarb.c +++ b/drivers/gpu/vga/vgaarb.c @@ -96,7 +96,8 @@ static const char *vga_iostate_to_str(unsigned int iostate) static int vga_str_to_iostate(char *buf, int str_size, int *io_state) { /* we could in theory hand out locks on IO and mem - * separately to userspace but it can cause deadlocks */ + * separately to userspace but it can cause deadlocks + */ if (strncmp(buf, "none", 4) == 0) { *io_state = VGA_RSRC_NONE; return 1; @@ -155,13 +156,15 @@ static inline void vga_irq_set_state(struct vga_device *vgadev, bool state) /* If we don't ever use VGA arb we should avoid - turning off anything anywhere due to old X servers getting - confused about the boot device not being VGA */ + * turning off anything anywhere due to old X servers getting + * confused about the boot device not being VGA + */ static void vga_check_first_use(void) { /* we should inform all GPUs in the system that * VGA arb has occurred and to try and disable resources - * if they can */ + * if they can + */ if (!vga_arbiter_used) { vga_arbiter_used = true; vga_arbiter_notify_clients(); @@ -985,11 +988,11 @@ static ssize_t vga_arb_write(struct file *file, const char __user *buf, goto done; } /* TODO: Add this? - if (io_state == VGA_RSRC_NONE) { - ret_val = -EPROTO; - goto done; - } - */ + * if (io_state == VGA_RSRC_NONE) { + * ret_val = -EPROTO; + * goto done; + * } + */ } pdev = priv->target; @@ -1037,10 +1040,10 @@ static ssize_t vga_arb_write(struct file *file, const char __user *buf, goto done; } /* TODO: Add this? - if (io_state == VGA_RSRC_NONE) { - ret_val = -EPROTO; - goto done; - } + * if (io_state == VGA_RSRC_NONE) { + * ret_val = -EPROTO; + * goto done; + * } */ pdev = priv->target; @@ -1276,7 +1279,8 @@ static int pci_notify(struct notifier_block *nb, unsigned long action, /* For now we're only intereted in devices added and removed. I didn't * test this thing here, so someone needs to double check for the - * cases of hotplugable vga cards. */ + * cases of hotplugable vga cards. + */ if (action == BUS_NOTIFY_ADD_DEVICE) notify = vga_arbiter_add_pci_device(pdev); else if (action == BUS_NOTIFY_DEL_DEVICE) @@ -1317,7 +1321,8 @@ static int __init vga_arb_device_init(void) bus_register_notifier(&pci_bus_type, &pci_notifier); /* We add all pci devices satisfying vga class in the arbiter by - * default */ + * default + */ pdev = NULL; while ((pdev = pci_get_subsys(PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, -- 2.5.2

1 0

[PATCH] drm/vmwgfx: Fix kernel NULL pointer dereference on older hardware
by Thomas Hellstrom 13 Oct '15

13 Oct '15

The commit "drm/vmwgfx: Fix up user_dmabuf refcounting", while fixing a kernel crash introduced a NULL pointer dereference on older hardware. Fix this. Cc: <stable(a)vger.kernel.org> Signed-off-by: Thomas Hellstrom <thellstrom(a)vmware.com> Reviewed-by: Sinclair Yeh <syeh(a)vmware.com> Reviewed-by: Brian Paul <brianp(a)vmware.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c index 64b5040..03f63c7 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c @@ -657,7 +657,8 @@ static void vmw_user_surface_base_release(struct ttm_base_object **p_base) struct vmw_resource *res = &user_srf->srf.res; *p_base = NULL; - ttm_base_object_unref(&user_srf->backup_base); + if (user_srf->backup_base) + ttm_base_object_unref(&user_srf->backup_base); vmw_resource_unreference(&res); } -- 2.1.0

1 0

[Bug 105871] New: UVD decoder fails after hibernate
by bugzilla-daemon＠bugzilla.kernel.org 13 Oct '15

13 Oct '15

https://bugzilla.kernel.org/show_bug.cgi?id=105871 Bug ID: 105871 Summary: UVD decoder fails after hibernate Product: Drivers Version: 2.5 Kernel Version: 4.1.8 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: jjorge(a)free.fr Regression: No [AMD/ATI] RS780 [Radeon HD 3200] works nicely, even after suspend/resume. But after a hibernate/resume, the UVD decoder fails, while OpenGL apps run ok. Full dmesg joined, here are the interesting lines : [ 258.694723] ACPI: Waking up from system sleep state S4 [ 258.696487] PM: noirq restore of devices complete after 0.724 msecs [ 258.696783] PM: early restore of devices complete after 0.260 msecs [ 258.735733] rtc_cmos 00:01: System wakeup disabled by ACPI [ 258.744344] [drm] PCIE GART of 512M enabled (table at 0x00000000C0258000). [ 258.744394] radeon 0000:01:05.0: WB enabled [ 258.744397] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x00000000a0000c00 and cpu addr 0xffff88003758dc00 [ 258.750826] radeon 0000:01:05.0: fence driver on ring 5 use gpu addr 0x00000000c0056038 and cpu addr 0xffffc90000816038 [ 258.783182] [drm] ring test on 0 succeeded in 0 usecs [ 258.959618] [drm] ring test on 5 succeeded in 1 usecs [ 258.959622] [drm] UVD initialized successfully. [ 258.959645] [drm] ib test on ring 0 succeeded in 0 usecs [ 269.631608] radeon 0000:01:05.0: ring 5 stalled for more than 10020msec [ 269.631610] radeon 0000:01:05.0: GPU lockup (current fence id 0x0000000000000862 last fence id 0x0000000000000864 on ring 5) [ 269.631693] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: fence wait failed (-35). [ 269.631719] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed testing IB on ring 5 (-35). -- You are receiving this mail because: You are watching the assignee of the bug.

1 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel October 2015