dri-devel April 2015

dri-devel@lists.freedesktop.org

175 participants
1044 discussions

[GIT PULL] exynos-drm-fixes
by inki.dae＠samsung.com 02 Apr '15

02 Apr '15

Hi Dave, Fix display on issue to Exynos5250 based Snow(1366x768) board. Please kindly let me know if there is any problem. Thanks, Inki Dae The following changes since commit 91fd89660ba2e8ee59a587294fa9b17761691b05: Merge branch 'drm-fixes-4.0' of git://people.freedesktop.org/~agd5f/linux into drm-fixes (2015-03-30 12:17:27 +1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git exynos-drm-fixes for you to fetch changes up to adacb228d72b9529f8de0769cc33414c3012054d: drm: Exynos: Respect framebuffer pitch for FIMD/Mixer (2015-04-02 22:37:13 +0900) ---------------------------------------------------------------- Daniel Stone (1): drm: Exynos: Respect framebuffer pitch for FIMD/Mixer drivers/gpu/drm/exynos/exynos_drm_fimd.c | 8 +++++--- drivers/gpu/drm/exynos/exynos_mixer.c | 17 ++++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-)

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[PULL] drm-intel-fixes
by Jani Nikula 02 Apr '15

02 Apr '15

Hi Dave - A colorkey ioctl oops fix from Ville, cc: stable, and a backport of Chris' 0-length batch allocation fix from drm-next. BR, Jani. The following changes since commit e42391cd048809d903291d07f86ed3934ce138e9: Linux 4.0-rc6 (2015-03-29 15:26:31 -0700) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-fixes-2015-04-02 for you to fetch changes up to 840a1cf0cd533f30da792527ca5ff6a023d4a727: drm/i915: Reject the colorkey ioctls for primary and cursor planes (2015-04-02 11:25:50 +0300) ---------------------------------------------------------------- Chris Wilson (1): drm/i915: Skip allocating shadow batch for 0-length batches Ville Syrjälä (1): drm/i915: Reject the colorkey ioctls for primary and cursor planes drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) -- Jani Nikula, Intel Open Source Technology Center

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screen goes blank when loading gma500_gfx (atom D2500)
by Michael Tokarev 02 Apr '15

02 Apr '15

Hello. Today I rebooted my router into a new kernel and noticed that the screen goes blank after booting the system (initial bootup messages are visible). After some debugging it turns out that the screen goes blank when loading gma500_gfx module. This is an intel D2500CC motherboard with Atom D5200 built-in, with a monitor connected to a VGA port, the following vga device is reported by lspci: 00:02.0 VGA compatible controller: Intel Corporation Atom Processor D2xxx/N2xxx Integrated Graphics Controller (rev 09) Here are the dmesg output after loading gma500_gfx: [ 176.427071] Linux agpgart interface v0.103 [ 176.452914] [drm] Initialized drm 1.1.0 20060810 [ 176.476037] gma500 0000:00:02.0: setting latency timer to 64 [ 176.476216] gma500 0000:00:02.0: irq 50 for MSI/MSI-X [ 176.491675] acpi device:29: registered as cooling_device2 [ 176.492041] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 176.492169] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input11 [ 176.492357] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010). [ 176.492396] [drm] No driver support for vblank timestamp query. [ 176.607485] gma500 0000:00:02.0: trying to get vblank count for disabled pipe 1 [ 176.607531] gma500 0000:00:02.0: trying to get vblank count for disabled pipe 1 [ 176.806078] [drm] Initialized gma500 1.0.0 2011-06-06 for 0000:00:02.0 on minor 0 which does not look bad or suspicious to me. fbcon is loaded so it isn't an issue. I tried 3.10 kernel initially (the above messages are from it), next I tried 3.13 kernel too, and that one behaves exactly the same. As far as I remember, this system never worked with graphics well. Previous kernel (from which I updated) was 3.2 which had no gma500 module (local build). What are the steps to debug this further? Thanks, /mjt

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[RFC 0/11] dw_hdmi cleanups, audio preparation, helpers and ahb audio support
by Russell King - ARM Linux 02 Apr '15

02 Apr '15

I'm sending this series for comments, and to allow people to update their code bases (for those who are using my AHB audio driver on iMX6). This is really several series, and I'm not expecting this to be ready for the upcoming merge window. That said, if anyone wants to say that they're happy with some of the initial four patches, I'm happy to queue those for David, if he's willing to take them. This series applies on top of my previous series, which finished with the patch "drm: bridge/dw_hdmi: adjust n/cts setting order". The first four patches are a few cleanups to the dw_hdmi driver. The next two patches introduce new interfaces to the dw_hdmi driver to support AHB audio, including the errata found on iMX6 which requires N to be programmed to zero when the audio FIFO is not full. I'm expecting some discussion with these last two as we try to work out how to deal with the two variants of audio support for this part (AHB audio vs I2S audio). The following three add various helpers to the DRM and ALSA subsystems for audio support which is non-specific to the AHB audio driver. For DRM, this is a helper macro to obtain the pointer into the short audio descriptors. For ALSA, it's a set of helpers to restrict an audio PCM device's capabilities according to the ELD, and to generate the IEC958 channel status data. If these helpers are acceptable, we can convert a number of drivers to them. The ELD helper isn't quite finished, but should be sufficient for initial testing. The last two patches add support for the dw_hdmi audio. This is an ALSA driver rather than an ASoC driver as it's a pretty simple affair. I couldn't find a suitable location in the sound/ subtree to place it, so I've placed it next to the bridge - yes, we probably need to find it a better home in the sound/ subtree, but it currently makes use of dw_hdmi.h in the directory it lives. drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c | 566 +++++++++++++++++++++++++++++ drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.h | 14 + drivers/gpu/drm/bridge/dw_hdmi.c | 250 ++++++++----- drivers/gpu/drm/bridge/dw_hdmi.h | 3 + include/drm/bridge/dw_hdmi.h | 7 + include/drm/drm_edid.h | 19 + include/sound/pcm_drm_eld.h | 6 + include/sound/pcm_iec958.h | 9 + sound/core/Kconfig | 6 + sound/core/Makefile | 3 + sound/core/pcm_drm_eld.c | 91 +++++ sound/core/pcm_iec958.c | 70 ++++ 14 files changed, 964 insertions(+), 92 deletions(-) -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

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[PATCH] drm/i915: Rip out GET_SPRITE_COLORKEY ioctl
by Daniel Vetter 02 Apr '15

02 Apr '15

It's completely unused and Tommi noticed that the #define is borked since forever. I've done a git search in userspace and only found broken definitions and no users anywhere. Cc: Tommi Rantala <tt.rantala(a)gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 2 -- drivers/gpu/drm/i915/intel_sprite.c | 24 ------------------------ 3 files changed, 1 insertion(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index d49ed68f041e..68e0c85a17cf 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1199,7 +1199,7 @@ const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index cb57b9c446f3..6036e3b73b7b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1282,8 +1282,6 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv, int intel_plane_restore(struct drm_plane *plane); int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); -int intel_sprite_get_colorkey(struct drm_device *dev, void *data, - struct drm_file *file_priv); bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count); void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f41e872ad858..e9ff6fc61267 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1134,30 +1134,6 @@ out_unlock: return ret; } -int intel_sprite_get_colorkey(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_intel_sprite_colorkey *get = data; - struct drm_plane *plane; - struct intel_plane *intel_plane; - int ret = 0; - - drm_modeset_lock_all(dev); - - plane = drm_plane_find(dev, get->plane_id); - if (!plane) { - ret = -ENOENT; - goto out_unlock; - } - - intel_plane = to_intel_plane(plane); - *get = intel_plane->ckey; - -out_unlock: - drm_modeset_unlock_all(dev); - return ret; -} - int intel_plane_restore(struct drm_plane *plane) { if (!plane->crtc || !plane->state->fb) -- 2.1.4

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[PULL] topic/drm-fixes
by Jani Nikula 02 Apr '15

02 Apr '15

Hi Dave - Here's a single drm core fix, cc: stable, that affects i915 users. Picked it up myself as explained in [1]. I'll still send a separate drm/i915 pull request. BR, Jani. [1] http://mid.gmane.org/874mp6r6bk.fsf@intel.com The following changes since commit bc465aa9d045feb0e13b4a8f32cc33c1943f62d6: Linux 4.0-rc5 (2015-03-22 16:50:21 -0700) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/topic/drm-fixes-2015-04-02 for you to fetch changes up to ad692b46dbf122ef90aadce3b389ef64c90e861d: drm/edid: set ELD for firmware and debugfs override EDIDs (2015-03-27 13:27:04 +0200) ---------------------------------------------------------------- Jani Nikula (1): drm/edid: set ELD for firmware and debugfs override EDIDs drivers/gpu/drm/drm_edid_load.c | 1 + drivers/gpu/drm/drm_probe_helper.c | 1 + 2 files changed, 2 insertions(+) -- Jani Nikula, Intel Open Source Technology Center

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[pull] drm/msm: msm-next for 4.1
by Rob Clark 02 Apr '15

02 Apr '15

Hi Dave, Main pull request for 4.1 for msm. Highlights: 1) support for "stolen mem" for splash-screen take-over 2) additional hdmi pixel clks 3) various pipe flush related fixes 4) support for snapdragon 410 (8x16) 5) support for DSI and dual-DSI It includes one small patch to export tile-group functions (which was ack'd by you), as these are used to explain to userspace dual-dsi configurations (with left and right tile). The following changes since commit 564b687b031ccc647943f946b93037cf0780612a: drm/bochs: disable video before changing video mode (2015-04-01 08:28:15 +1000) are available in the git repository at: git://people.freedesktop.org/~robclark/linux msm-next for you to fetch changes up to d5af49c92a8aff8236e7b0bb35e9af364000c017: drm/msm/mdp5: Enable DSI connector in msm drm driver (2015-04-01 19:29:38 -0400) ---------------------------------------------------------------- Hai Li (8): drm/msm/mdp5: Add pingpong entry to mdp5 config table drm/msm/mdp5: Update generated mdp5 header file with DSI support drm/msm/mdp5: Fix PIPE source image size settings drm/msm/dsi: Update generated DSI header file drm/msm/mdp5: Move *_modeset_init out of construct_encoder function drm/msm: Add split display interface drm/msm: Initial add DSI connector support drm/msm/mdp5: Enable DSI connector in msm drm driver Rob Clark (4): drm/msm: split out vram initialization drm/msm: add support for "stolen" mem drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clks drm: export tile-group functions Stephane Viau (12): drm/msm/mdp5: only flush on a CRTC ->atomic_flush() drm/msm/mdp5: Update generated header files drm/msm/mdp5: Enhance operation mode for pipeline configuration drm/msm/mdp5: Add START signal to kick off certain pipelines drm/msm/mdp5: Make the intf connection in config module drm/msm/mdp5: Update headers (introduce MDP5 domain) drm/msm/mdp5: Separate MDP5 domain from MDSS domain drm/msm/mdp5: Update headers (remove enum mdp5_client_id) drm/msm/mdp5: Get SMP client list from mdp5_cfg drm/msm/mdp5: Add hardware configuration for msm8x16 drm/msm/mdp5: Update headers (add CTL flush bits) drm/msm/mdp5: Remove CTL flush dummy bits drivers/gpu/drm/drm_crtc.c | 2 + drivers/gpu/drm/msm/Kconfig | 11 + drivers/gpu/drm/msm/Makefile | 5 + drivers/gpu/drm/msm/dsi/dsi.c | 212 +++ drivers/gpu/drm/msm/dsi/dsi.h | 117 ++ drivers/gpu/drm/msm/dsi/dsi.xml.h | 418 ++++- drivers/gpu/drm/msm/dsi/dsi_host.c | 1993 +++++++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_manager.c | 705 ++++++++ drivers/gpu/drm/msm/dsi/dsi_phy.c | 352 ++++ drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 34 + drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 399 +++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 102 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 18 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 343 ++++ drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 86 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 315 +++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 75 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 83 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 26 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 200 ++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 75 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 4 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 64 +- drivers/gpu/drm/msm/msm_drv.c | 100 +- drivers/gpu/drm/msm/msm_drv.h | 29 + drivers/gpu/drm/msm/msm_fbdev.c | 3 +- drivers/gpu/drm/msm/msm_gem.c | 25 +- drivers/gpu/drm/msm/msm_gem.h | 5 +- drivers/gpu/drm/msm/msm_kms.h | 4 + 29 files changed, 5327 insertions(+), 478 deletions(-) create mode 100644 drivers/gpu/drm/msm/dsi/dsi.c create mode 100644 drivers/gpu/drm/msm/dsi/dsi.h create mode 100644 drivers/gpu/drm/msm/dsi/dsi_host.c create mode 100644 drivers/gpu/drm/msm/dsi/dsi_manager.c create mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy.c create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c

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[PATCH 1/3] drm/msm/mdp5: Update generated header files with writeback support
by Jilai Wang 01 Apr '15

01 Apr '15

Add register field for MDP5 writeback block Signed-off-by: Jilai Wang <jilaiw(a)codeaurora.org> --- drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 373 ++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 18 +- 2 files changed, 373 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index 09bfaff..ea470a2 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h @@ -8,9 +8,9 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 26608 bytes, from 2015-02-05 23:01:09) -- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15) -- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-01-23 16:20:19) +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/mdp/mdp5.xml ( 31502 bytes, from 2015-01-16 22:36:33) +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-11-24 22:27:21) +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-01-16 22:37:14) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark(a)gmail.com> (robclark) @@ -120,6 +120,21 @@ enum mdp5_data_format { DATA_FORMAT_YUV = 1, }; +enum mdp5_block_size { + BLOCK_SIZE_64 = 0, + BLOCK_SIZE_128 = 1, +}; + +enum mdp5_rotate_mode { + ROTATE_0 = 0, + ROTATE_90 = 1, +}; + +enum mdp5_chroma_downsample_method { + DS_MTHD_NO_PIXEL_DROP = 0, + DS_MTHD_PIXEL_DROP = 1, +}; + #define MDP5_IRQ_WB_0_DONE 0x00000001 #define MDP5_IRQ_WB_1_DONE 0x00000002 #define MDP5_IRQ_WB_2_DONE 0x00000010 @@ -757,7 +772,7 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19 -static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val) +static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val) { return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK; } @@ -1121,6 +1136,356 @@ static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } +static inline uint32_t __offset_WB(uint32_t idx) +{ + switch (idx) { + case 0: return (mdp5_cfg->wb.base[0]); + case 1: return (mdp5_cfg->wb.base[1]); + case 2: return (mdp5_cfg->wb.base[2]); + case 3: return (mdp5_cfg->wb.base[3]); + case 4: return (mdp5_cfg->wb.base[4]); + default: return INVALID_IDX(idx); + } +} +static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } +#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003 +#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c +#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030 +#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0 +#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100 +#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600 +#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK; +} +#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000 +#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12 +static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000 +#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000 +#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000 +#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000 +#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19 +static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK; +} +#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000 +#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30 +static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } +#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001 +#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006 +#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1 +static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK; +} +#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010 +#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4 +static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK; +} +#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020 +#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5 +static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK; +} +#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040 +#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100 +#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200 +#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9 +static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400 +#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10 +static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); } +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); } +#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff +#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0 +static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK; +} +#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000 +#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16 +static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); } +#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff +#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0 +static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK; +} +#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000 +#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16 +static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } +#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff +#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0 +static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) +{ + return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK; +} +#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000 +#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16 +static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) +{ + return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK; +} + +static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK; +} +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00 +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8 +static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK; +} +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00 +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8 +static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff +#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff +#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK; +} + static inline uint32_t __offset_INTF(uint32_t idx) { switch (idx) { diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h index a1d35f1..73da38f 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h @@ -8,19 +8,9 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - -Copyright (C) 2013-2014 by the following authors: +- /local/mnt2/workspace2/jilaiw/chromeos/envytools/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-01-16 22:37:14) + +Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark(a)gmail.com> (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -52,7 +42,7 @@ enum mdp_chroma_samp_type { CHROMA_420 = 3, }; -enum mdp_sspp_fetch_type { +enum mdp_fetch_type { MDP_PLANE_INTERLEAVED = 0, MDP_PLANE_PLANAR = 1, MDP_PLANE_PSEUDO_PLANAR = 2, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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[PATCH] rnndb: Add register description in mdp5 writeback block
by Jilai Wang 01 Apr '15

01 Apr '15

This patch adds the register description in mdp5 writeback block. Signed-off-by: Jilai Wang <jilaiw(a)codeaurora.org> --- rnndb/mdp/mdp5.xml | 126 ++++++++++++++++++++++++++++++++++++++++++++++- rnndb/mdp/mdp_common.xml | 2 +- 2 files changed, 126 insertions(+), 2 deletions(-) diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml index 29c5992..f1a6397 100644 --- a/rnndb/mdp/mdp5.xml +++ b/rnndb/mdp/mdp5.xml @@ -332,7 +332,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/> <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/> <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/> - <bitfield name="NUM_PLANES" low="19" high="20" type="mdp_sspp_fetch_type"/> + <bitfield name="NUM_PLANES" low="19" high="20" type="mdp_fetch_type"/> <bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/> </reg32> <reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/> @@ -454,6 +454,130 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x2b0" name="GC_BASE"/> </array> + <enum name="mdp5_block_size"> + <value name="BLOCK_SIZE_64" value="0"/> + <value name="BLOCK_SIZE_128" value="1"/> + </enum> + + <enum name="mdp5_rotate_mode"> + <value name="ROTATE_0" value="0"/> + <value name="ROTATE_90" value="1"/> + </enum> + + <enum name="mdp5_chroma_downsample_method"> + <value name="DS_MTHD_NO_PIXEL_DROP" value="0"/> + <value name="DS_MTHD_PIXEL_DROP" value="1"/> + </enum> + + <array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],,mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400"> + <reg32 offset="0x000" name="DST_FORMAT"> + <bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/> + <bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/> + <bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/> + <bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/> + <bitfield name="DSTC3_EN" pos="8" type="boolean"/> + <bitfield name="DST_BPP" low="9" high="10" type="uint"/> + <bitfield name="PACK_COUNT" low="12" high="13" type="uint"/> + <bitfield name="DST_ALPHA_X" pos="14" type="boolean"/> + <bitfield name="PACK_TIGHT" pos="17" type="boolean"/> + <bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/> + <bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/> + <bitfield name="DST_DITHER_EN" pos="22" type="boolean"/> + <bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/> + <bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/> + <bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/> + </reg32> + <reg32 offset="0x004" name="DST_OP_MODE"> + <bitfield name="BWC_ENC_EN" pos="0" type="boolean"/> + <bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/> + <bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/> + <bitfield name="ROT_MODE" low="5" high="5" type="uint"/> + <bitfield name="ROT_EN" pos="6" type="boolean"/> + <bitfield name="CSC_EN" pos="8" type="boolean"/> + <bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/> + <bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/> + <bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/> + <bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/> + <bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/> + <bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/> + </reg32> + <reg32 offset="0x008" name="DST_PACK_PATTERN"> + <bitfield name="ELEMENT0" low="0" high="1" type="uint"/> + <bitfield name="ELEMENT1" low="8" high="9" type="uint"/> + <bitfield name="ELEMENT2" low="16" high="17" type="uint"/> + <bitfield name="ELEMENT3" low="24" high="25" type="uint"/> + </reg32> + <reg32 offset="0x00c" name="DST0_ADDR"/> + <reg32 offset="0x010" name="DST1_ADDR"/> + <reg32 offset="0x014" name="DST2_ADDR"/> + <reg32 offset="0x018" name="DST3_ADDR"/> + <reg32 offset="0x01c" name="DST_YSTRIDE0"> + <bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/> + <bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="0x020" name="DST_YSTRIDE1"> + <bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/> + <bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/> + <reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/> + <reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/> + <reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/> + <reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/> + <reg32 offset="0x048" name="DST_WRITE_CONFIG"/> + <reg32 offset="0x050" name="ROTATION_DNSCALER"/> + <reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/> + <reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/> + <reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/> + <reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/> + <reg32 offset="0x074" name="OUT_SIZE"> + <bitfield name="DST_W" low="0" high="15" type="uint"/> + <bitfield name="DST_H" low="16" high="31" type="uint"/> + </reg32> + <reg32 offset="0x078" name="ALPHA_X_VALUE"/> + <reg32 offset="0x260" name="CSC_MATRIX_COEFF_0"> + <bitfield name="COEFF_11" low="0" high="12" type="uint"/> + <bitfield name="COEFF_12" low="16" high="28" type="uint"/> + </reg32> + <reg32 offset="0x264" name="CSC_MATRIX_COEFF_1"> + <bitfield name="COEFF_13" low="0" high="12" type="uint"/> + <bitfield name="COEFF_21" low="16" high="28" type="uint"/> + </reg32> + <reg32 offset="0x268" name="CSC_MATRIX_COEFF_2"> + <bitfield name="COEFF_22" low="0" high="12" type="uint"/> + <bitfield name="COEFF_23" low="16" high="28" type="uint"/> + </reg32> + <reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3"> + <bitfield name="COEFF_31" low="0" high="12" type="uint"/> + <bitfield name="COEFF_32" low="16" high="28" type="uint"/> + </reg32> + <reg32 offset="0x270" name="CSC_MATRIX_COEFF_4"> + <bitfield name="COEFF_33" low="0" high="12" type="uint"/> + </reg32> + <array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4"> + <reg32 offset="0" name="REG"> + <bitfield name="HIGH" low="0" high="7" type="uint"/> + <bitfield name="LOW" low="8" high="15" type="uint"/> + </reg32> + </array> + <array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4"> + <reg32 offset="0" name="REG"> + <bitfield name="HIGH" low="0" high="7" type="uint"/> + <bitfield name="LOW" low="8" high="15" type="uint"/> + </reg32> + </array> + <array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4"> + <reg32 offset="0" name="REG"> + <bitfield name="VALUE" low="0" high="8" type="uint"/> + </reg32> + </array> + <array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4"> + <reg32 offset="0" name="REG"> + <bitfield name="VALUE" low="0" high="8" type="uint"/> + </reg32> + </array> + </array> + <array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200"> <reg32 offset="0x000" name="TIMING_ENGINE_EN"/> <reg32 offset="0x004" name="CONFIG"/> diff --git a/rnndb/mdp/mdp_common.xml b/rnndb/mdp/mdp_common.xml index 6f805f7..b4d1949 100644 --- a/rnndb/mdp/mdp_common.xml +++ b/rnndb/mdp/mdp_common.xml @@ -13,7 +13,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <value name="CHROMA_420" value="3"/> </enum> -<enum name="mdp_sspp_fetch_type"> +<enum name="mdp_fetch_type"> <value name="MDP_PLANE_INTERLEAVED" value="0"/> <value name="MDP_PLANE_PLANAR" value="1"/> <value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/> -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

1 0

[PULL] vmwgfx-next
by Thomas Hellstrom 01 Apr '15

01 Apr '15

Dave, The first pull request for 4.1. Mainly Sinclair's screen target work. The following changes since commit 03be70050c85768e9ce7c0d0887110d1b629e127: Merge tag 'topic/drm-misc-2015-03-10' of git://anongit.freedesktop.org/drm-intel into drm-next (2015-03-11 12:15:06 +1000) are available in the git repository at: git://people.freedesktop.org/~thomash for you to fetch changes up to 51850be6365084dc3ff6516bb9d89c6d7e3a98f1: drm/ttm: Add lockdep annotation to the TTM lock (2015-03-11 11:57:40 -0700) ---------------------------------------------------------------- Sinclair Yeh (4): drm/vmwgfx: SVGA device definition update drm/vmwgfx: Refactor vmw_gb_surface_define_ioctl() drm/vmwgfx: Major KMS refactoring / cleanup in preparation of screen targets drm/vmwgfx: Implement screen targets Thomas Hellstrom (3): drm/vmwgfx: Add an interface to pin a resource v3 drm/vmwgfx: Add "quirk" to handling command verification exceptions drm/ttm: Add lockdep annotation to the TTM lock drivers/gpu/drm/ttm/ttm_lock.c | 73 +- drivers/gpu/drm/vmwgfx/Makefile | 2 +- drivers/gpu/drm/vmwgfx/svga3d_reg.h | 56 +- drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h | 67 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 21 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | 52 +- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 10 + drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | 4 +- drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 4 + drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 608 +++--------- drivers/gpu/drm/vmwgfx/vmwgfx_kms.h | 97 +- drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 45 +- drivers/gpu/drm/vmwgfx/vmwgfx_mob.c | 3 +- drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c | 6 +- drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 91 +- drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 433 ++++++++- drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 1360 +++++++++++++++++++++++++++ drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 199 ++-- include/drm/ttm/ttm_lock.h | 13 +- include/uapi/drm/vmwgfx_drm.h | 1 + 20 files changed, 2470 insertions(+), 675 deletions(-) create mode 100644 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c

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dri-devel April 2015