dri-devel May 2016

dri-devel@lists.freedesktop.org

212 participants
1404 discussions

[PATCH] drm/amd/powerplay: rewrite pp_sw_init to make code readable
by Alex Deucher 10 May '16

10 May '16

From: Huang Rui <ray.huang(a)amd.com> Actually, pp_sw_init executes pptable_init and backend_init orderly if they are initialized successfully. So rewrite it to make code more readable. Reviewed-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Huang Rui <ray.huang(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 9f2d4069..8e345bf 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -68,15 +68,18 @@ static int pp_sw_init(void *handle) return -EINVAL; ret = hwmgr->pptable_func->pptable_init(hwmgr); + if (ret) + goto err; - if (ret == 0) - ret = hwmgr->hwmgr_func->backend_init(hwmgr); - + ret = hwmgr->hwmgr_func->backend_init(hwmgr); if (ret) - printk(KERN_ERR "amdgpu: powerplay initialization failed\n"); - else - printk(KERN_INFO "amdgpu: powerplay initialized\n"); + goto err; + pr_info("amdgpu: powerplay initialized\n"); + + return 0; +err: + pr_err("amdgpu: powerplay initialization failed\n"); return ret; } -- 2.5.5

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[PATCH] drm/imx: use bus_flags for pixel clock polarity
by Philipp Zabel 10 May '16

10 May '16

This patch allows panels to set pixel clock and data enable pin polarity other than the default of driving data at the rising pixel clock edge and active high display enable. Signed-off-by: Philipp Zabel <p.zabel(a)pengutronix.de> --- drivers/gpu/drm/imx/imx-drm-core.c | 9 ++++++--- drivers/gpu/drm/imx/imx-drm.h | 5 +++-- drivers/gpu/drm/imx/imx-tve.c | 4 +++- drivers/gpu/drm/imx/ipuv3-crtc.c | 9 ++++++--- drivers/gpu/drm/imx/parallel-display.c | 4 ++-- 5 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index 2453fb1..6e5891a 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -97,7 +97,7 @@ static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc) } int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format, - int hsync_pin, int vsync_pin) + int hsync_pin, int vsync_pin, u32 bus_flags) { struct imx_drm_crtc_helper_funcs *helper; struct imx_drm_crtc *imx_crtc; @@ -109,14 +109,17 @@ int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format, helper = &imx_crtc->imx_drm_helper_funcs; if (helper->set_interface_pix_fmt) return helper->set_interface_pix_fmt(encoder->crtc, - bus_format, hsync_pin, vsync_pin); + bus_format, hsync_pin, vsync_pin, + bus_flags); return 0; } EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins); int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format) { - return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3); + return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3, + DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_POSEDGE); } EXPORT_SYMBOL_GPL(imx_drm_set_bus_format); diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h index b0241b9..1400664 100644 --- a/drivers/gpu/drm/imx/imx-drm.h +++ b/drivers/gpu/drm/imx/imx-drm.h @@ -19,7 +19,8 @@ struct imx_drm_crtc_helper_funcs { int (*enable_vblank)(struct drm_crtc *crtc); void (*disable_vblank)(struct drm_crtc *crtc); int (*set_interface_pix_fmt)(struct drm_crtc *crtc, - u32 bus_format, int hsync_pin, int vsync_pin); + u32 bus_format, int hsync_pin, int vsync_pin, + u32 bus_flags); const struct drm_crtc_helper_funcs *crtc_helper_funcs; const struct drm_crtc_funcs *crtc_funcs; }; @@ -42,7 +43,7 @@ void imx_drm_mode_config_init(struct drm_device *drm); struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb); int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, - u32 bus_format, int hsync_pin, int vsync_pin); + u32 bus_format, int hsync_pin, int vsync_pin, u32 bus_flags); int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format); diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c index ae7a9fb..cb25582 100644 --- a/drivers/gpu/drm/imx/imx-tve.c +++ b/drivers/gpu/drm/imx/imx-tve.c @@ -295,7 +295,9 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder) switch (tve->mode) { case TVE_MODE_VGA: imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_GBR888_1X24, - tve->hsync_pin, tve->vsync_pin); + tve->hsync_pin, tve->vsync_pin, + DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_POSEDGE); break; case TVE_MODE_TVOUT: imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24); diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index dee8e8b..d8b58b0 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -66,6 +66,7 @@ struct ipu_crtc { struct ipu_flip_work *flip_work; int irq; u32 bus_format; + u32 bus_flags; int di_hsync_pin; int di_vsync_pin; }; @@ -271,8 +272,9 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, else sig_cfg.clkflags = 0; - sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 0; + sig_cfg.enable_pol = !(ipu_crtc->bus_flags & DRM_BUS_FLAG_DE_LOW); + sig_cfg.clk_pol = !!(ipu_crtc->bus_flags & + DRM_BUS_FLAG_PIXDATA_NEGEDGE); sig_cfg.bus_format = ipu_crtc->bus_format; sig_cfg.v_to_h_sync = 0; sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; @@ -396,11 +398,12 @@ static void ipu_disable_vblank(struct drm_crtc *crtc) } static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, - u32 bus_format, int hsync_pin, int vsync_pin) + u32 bus_format, int hsync_pin, int vsync_pin, u32 bus_flags) { struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); ipu_crtc->bus_format = bus_format; + ipu_crtc->bus_flags = bus_flags; ipu_crtc->di_hsync_pin = hsync_pin; ipu_crtc->di_vsync_pin = vsync_pin; diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c index 363e2c7..030235f 100644 --- a/drivers/gpu/drm/imx/parallel-display.c +++ b/drivers/gpu/drm/imx/parallel-display.c @@ -115,8 +115,8 @@ static void imx_pd_encoder_dpms(struct drm_encoder *encoder, int mode) static void imx_pd_encoder_prepare(struct drm_encoder *encoder) { struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); - - imx_drm_set_bus_format(encoder, imxpd->bus_format); + imx_drm_set_bus_format_pins(encoder, imxpd->bus_format, 2, 3, + imxpd->connector.display_info.bus_flags); } static void imx_pd_encoder_commit(struct drm_encoder *encoder) -- 2.8.0.rc3

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re: drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)
by Dan Carpenter 10 May '16

10 May '16

Hello Eric Huang, The patch 5632708f4452: "drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)" from Apr 12, 2016, leads to the following static checker warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:368 amdgpu_set_pp_dpm_sclk() warn: why is the last element skipped? drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 356 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 357 struct device_attribute *attr, 358 const char *buf, 359 size_t count) 360 { 361 struct drm_device *ddev = dev_get_drvdata(dev); 362 struct amdgpu_device *adev = ddev->dev_private; 363 int ret; 364 long level; 365 uint32_t i, mask = 0; 366 char sub_str[2]; 367 368 for (i = 0; i < strlen(buf) - 1; i++) { strlen() returns the number of characters not counting the NUL terminator. I guess this assumes that the last character is a newline? Could we check for that instead? 369 sub_str[0] = *(buf + i); 370 sub_str[1] = '\0'; 371 ret = kstrtol(sub_str, 0, &level); 372 373 if (ret) { 374 count = -EINVAL; 375 goto fail; 376 } 377 mask |= 1 << level; 378 } 379 380 if (adev->pp_enabled) 381 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); 382 fail: 383 return count; 384 } There are a couple other: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:412 amdgpu_set_pp_dpm_mclk() warn: why is the last element skipped? drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:456 amdgpu_set_pp_dpm_pcie() warn: why is the last element skipped? regards, dan carpenter

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[PATCH v2] drm/vc4: Return -EBUSY if there's already a pending flip event.
by robert.foss＠collabora.com 10 May '16

10 May '16

From: Robert Foss <robert.foss(a)collabora.com> As per the documentation in drm_crtc.h, atomic_commit should return -EBUSY if an asycnhronous update is requested and there is an earlier update pending. Note: docs cited here are drm_crtc.h, and the whole quote is: * - -EBUSY, if an asynchronous updated is requested and there is * an earlier updated pending. Drivers are allowed to support a queue * of outstanding updates, but currently no driver supports that. * Note that drivers must wait for preceding updates to complete if a * synchronous update is requested, they are not allowed to fail the * commit in that case. Signed-off-by: Robert Foss <robert.foss(a)collabora.com> --- Changes since v1: - Corrected and simplified patch to piggyback on a previously existing check. drivers/gpu/drm/vc4/vc4_kms.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index 4718ae5..7c7188d 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -117,10 +117,18 @@ static int vc4_atomic_commit(struct drm_device *dev, return -ENOMEM; /* Make sure that any outstanding modesets have finished. */ - ret = down_interruptible(&vc4->async_modeset); - if (ret) { - kfree(c); - return ret; + if (async) { + ret = down_trylock(&vc4->async_modeset); + if (ret) { + kfree(c); + return -EBUSY; + } + } else { + ret = down_interruptible(&vc4->async_modeset); + if (ret) { + kfree(c); + return ret; + } } ret = drm_atomic_helper_prepare_planes(dev, state); -- 2.5.0

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[PATCH] drm/mediatek: Use lockless gem BO free callback
by Philipp Zabel 10 May '16

10 May '16

Since commit 9f0ba539d13a ("drm/gem: support BO freeing without dev->struct_mutex"), drivers that are struct_mutex free are supposed to use the gem_free_object_unlocked callback. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") Reported-by: Daniel Vetter <daniel(a)ffwll.ch> Signed-off-by: Philipp Zabel <p.zabel(a)pengutronix.de> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b1223d5..06a417b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -243,7 +243,7 @@ static struct drm_driver mtk_drm_driver = { .enable_vblank = mtk_drm_crtc_enable_vblank, .disable_vblank = mtk_drm_crtc_disable_vblank, - .gem_free_object = mtk_drm_gem_free_object, + .gem_free_object_unlocked = mtk_drm_gem_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, .dumb_create = mtk_drm_gem_dumb_create, .dumb_map_offset = mtk_drm_gem_dumb_map_offset, -- 2.8.0.rc3

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[GIT PULL] drm/tegra: Changes for v4.7-rc1
by Thierry Reding 10 May '16

10 May '16

Hi Dave, The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca: Linux 4.6-rc1 (2016-03-26 16:03:24 -0700) are available in the git repository at: git://anongit.freedesktop.org/tegra/linux tags/drm/tegra/for-4.7-rc1 for you to fetch changes up to 057eab2013ecbba2e772293acc177e2e3210f05d: MAINTAINERS: Remove Terje Bergström as Tegra DRM maintainer (2016-04-29 14:23:02 +0200) Thanks, Thierry ---------------------------------------------------------------- drm/tegra: Changes for v4.7-rc1 Two small changes, one getting rid of the bogus gamma table size and another removing Terje from the MAINTAINERS file since he no longer does any work on host1x or display. ---------------------------------------------------------------- Daniel Vetter (1): drm/tegra: Don't set a gamma table size Thierry Reding (1): MAINTAINERS: Remove Terje Bergström as Tegra DRM maintainer MAINTAINERS | 1 - drivers/gpu/drm/tegra/dc.c | 1 - 2 files changed, 2 deletions(-)

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[GIT PULL 2nd] exynos-drm-next
by Inki Dae 10 May '16

10 May '16

Hi Dave, This 2nd pull request includes one patch I missed, some cleanups and fixups. Summary: - expose HDMI-PHY clock to other drivers. . this patch was included in below patch series but I missed. http://www.spinics.net/lists/dri-devel/msg103097.html - some fixups about DECON5433 driver . this patch corrects vblank handling and fixes up trigger configuration. - use generic functions - gem_prime_mmap and dma_buf_mmap. - use DMA-Mapping API instead of specific one. - some code cleanups and fixeups. Please kindly let me know if there is any problem. Thanks, Inki Dae The following changes since commit 2e726dc4b4e2dd3ae3fe675f9d3af88a2d593ee1: Merge tag 'mediatek-drm-2016-05-09' of git://git.pengutronix.de/git/pza/linux into drm-next (2016-05-10 15:01:47 +1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git exynos-drm-next for you to fetch changes up to dd65a6867454117ecaeb8944dc231a4737681782: drm/exynos/decon5433: fix trigger configuration (2016-05-10 23:11:46 +0900) ---------------------------------------------------------------- Andrzej Hajda (5): drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock drm/exynos/decon5433: handle vblank in vblank interrupt drm/exynos/decon5433: do not use unnecessary software trigger drm/exynos: fix cancel page flip code drm/exynos/decon5433: fix trigger configuration Daniel Vetter (1): drm/exynos: Nuke dummy fb->dirty callback Javier Martinez Canillas (1): drm/exynos/hdmi: Don't print error on deferral due to regulators Joonyoung Shim (3): drm/exynos: support gem_prime_mmap drm/exynos: fix imported dma-buf to be mapped drm/exynos: use directly DMA mapping APIs on g2d Philipp Zabel (2): drm/exynos/dpi: use of_graph_get_endpoint_by_regs helper drm/exynos/dsi: use of_graph_get_endpoint_by_regs helper Tobias Jakobi (1): drm/exynos: fimd: harden fimd_calc_clkdiv() drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 16 +++--- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 15 ++--- drivers/gpu/drm/exynos/exynos_drm_dpi.c | 69 +---------------------- drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 + drivers/gpu/drm/exynos/exynos_drm_dsi.c | 57 +------------------ drivers/gpu/drm/exynos/exynos_drm_fb.c | 11 ---- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 9 ++- drivers/gpu/drm/exynos/exynos_drm_g2d.c | 10 ++-- drivers/gpu/drm/exynos/exynos_drm_gem.c | 70 ++++++++++++------------ drivers/gpu/drm/exynos/exynos_drm_gem.h | 12 +--- drivers/gpu/drm/exynos/exynos_hdmi.c | 73 ++++++++++++++++++------- 11 files changed, 120 insertions(+), 223 deletions(-)

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re: drm/amdgpu: add ELM/BAF DCE11 configs (v2)
by Dan Carpenter 10 May '16

10 May '16

Hello Alex Deucher, The patch d525eb8d2e67: "drm/amdgpu: add ELM/BAF DCE11 configs (v2)" from Oct 14, 2015, leads to the following static checker warning: drivers/gpu/drm/amd/amdgpu/dce_v11_0.c:1631 dce_v11_0_audio_init() error: buffer overflow 'pin_offsets' 7 <= 7 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 1589 static const u32 pin_offsets[] = 1590 { 1591 AUD0_REGISTER_OFFSET, 1592 AUD1_REGISTER_OFFSET, 1593 AUD2_REGISTER_OFFSET, 1594 AUD3_REGISTER_OFFSET, 1595 AUD4_REGISTER_OFFSET, 1596 AUD5_REGISTER_OFFSET, 1597 AUD6_REGISTER_OFFSET, This array always has 7 elements. 1598 }; 1599 1600 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1601 { 1602 int i; 1603 1604 if (!amdgpu_audio) 1605 return 0; 1606 1607 adev->mode_info.audio.enabled = true; 1608 1609 switch (adev->asic_type) { 1610 case CHIP_CARRIZO: 1611 case CHIP_STONEY: 1612 adev->mode_info.audio.num_pins = 7; 1613 break; 1614 case CHIP_POLARIS10: 1615 adev->mode_info.audio.num_pins = 8; We sometimes set num_pins to 8. 1616 break; 1617 case CHIP_POLARIS11: 1618 adev->mode_info.audio.num_pins = 6; 1619 break; 1620 default: 1621 return -EINVAL; 1622 } 1623 1624 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1625 adev->mode_info.audio.pin[i].channels = -1; 1626 adev->mode_info.audio.pin[i].rate = -1; 1627 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1628 adev->mode_info.audio.pin[i].status_bits = 0; 1629 adev->mode_info.audio.pin[i].category_code = 0; 1630 adev->mode_info.audio.pin[i].connected = false; 1631 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; ^^^^^^^^^^^^^^ So we're reading one step beyond the end of the array. 1632 adev->mode_info.audio.pin[i].id = i; 1633 /* disable audio. it will be set up later */ 1634 /* XXX remove once we switch to ip funcs */ 1635 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1636 } 1637 1638 return 0; 1639 } regards, dan carpenter

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[GIT PULL] drm/fsl-dcu: add pixel clock polarity support
by Stefan Agner 10 May '16

10 May '16

Hi Dave, This pull adds bus flags which allows to specify pixel clock polarity. It includes changes outside of fsl-dcu, the patch has been acked by Daniel. -- Stefan The following changes since commit 0552f7651bc233e5407ab06ba97a9d7c25e19580: drm/i915/mst: use reference counted connectors. (v3) (2016-05-05 12:52:07 +1000) are available in the git repository at: http://git.agner.ch/git/linux-drm-fsl-dcu.git for-next for you to fetch changes up to 2c80661d2ea9bac9bc7ba519097745829add1871: drm/fsl-dcu: use bus_flags for pixel clock polarity (2016-05-05 10:09:06 -0700) ---------------------------------------------------------------- Stefan Agner (2): drm: introduce bus_flags in drm_display_info drm/fsl-dcu: use bus_flags for pixel clock polarity drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 5 +++++ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 ++-- drivers/gpu/drm/panel/panel-simple.c | 5 ++++- include/drm/drm_crtc.h | 9 +++++++++ 4 files changed, 20 insertions(+), 3 deletions(-)

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re: drm/amdgpu: change ELM/BAF to Polaris10/Polaris11
by Dan Carpenter 10 May '16

10 May '16

Hello Flora Cui, The patch 2cc0c0b5cd4d: "drm/amdgpu: change ELM/BAF to Polaris10/Polaris11" from Mar 14, 2016, leads to the following static checker warning: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/polaris10_hwmgr.c:3620 polaris10_get_pp_table_entry_callback_func() warn: buffer overflow 'polaris10_power_state->performance_levels' 2 <= 7 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/polaris10_hwmgr.c 3592 power_state->temperatures.min = 0; 3593 power_state->temperatures.max = 0; 3594 3595 performance_level = &(polaris10_power_state->performance_levels 3596 [polaris10_power_state->performance_level_count++]); ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 3597 3598 PP_ASSERT_WITH_CODE( 3599 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ SMU74_MAX_LEVELS_GRAPHICS is 8 but ->performance_levels[] has POLARIS10_MAX_HARDWARE_POWERLEVELS which is 2 elements. What's the disconnect? 3600 "Performance levels exceeds SMC limit!", 3601 return -1); 3602 3603 PP_ASSERT_WITH_CODE( 3604 (polaris10_power_state->performance_level_count <= 3605 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3606 "Performance levels exceeds Driver limit!", 3607 return -1); 3608 3609 /* Performance levels are arranged from low to high. */ 3610 performance_level->memory_clock = mclk_dep_table->entries 3611 [state_entry->ucMemoryClockIndexLow].ulMclk; 3612 performance_level->engine_clock = sclk_dep_table->entries 3613 [state_entry->ucEngineClockIndexLow].ulSclk; 3614 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3615 state_entry->ucPCIEGenLow); 3616 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3617 state_entry->ucPCIELaneHigh); 3618 3619 performance_level = &(polaris10_power_state->performance_levels 3620 [polaris10_power_state->performance_level_count++]); regards, dan carpenter

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dri-devel May 2016